American Patents LLC v. Mediatek, Inc. et al

Western District of Texas, txwd-6:2018-cv-00339

Appendix A

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APPENDIX A Text of the Asserted Claims with Disputed Claim Terms Highlighted U.S. Patent No. 6,964,001 Asserted Claims: 5-6 5. An integrated circuit comprising: a multiplicity of logic blocks: an on-chip logic analyzer with a multiplicity of input ports: and a multiplicity of probe lines: wherein each of said probe lines is adapted to capture signals from said logic blocks and to propagate said signals to one of said multiplicity of input ports of said on-chip logic analyzer, said input ports of said on-chip logic analyzer comprising: means to capture said signals from said probe lines: means to align said signals propagated through said probe lines to create aligned signals: and means to capture said aligned signals. 6. The integrated circuit as in claim 5, wherein said on-chip logic analyzer further comprises means to transfer said aligned signals out of said integrated circuit. 1 U.S. Patent No. 7,836,371 Asserted Claims: 2, 7-10 1. An integrated circuit comprising: one or more logic blocks to generate one or more system-operation signals at one or more system-operation clock rates; and a service processor unit, said service processor unit comprising: a control unit; a buffer memory; and a multiplicity of selectable probes, wherein said service processor unit is adapted to perform capture and analysis of said system operation signals during normal system operation through said selectable probes. 2. The integrated circuit according to claim 1, further comprising at least one port selected from the group consisting of: a parallel I/O (PIO) port, a serial I/O (SIO) port, and a JTAG port; wherein data and instructions are to be sent through at least one of said ports to said service processor unit from an external diagnostics console, and wherein result data is to be sent through at least one of said ports from said service processor unit to said external diagnostics console. 1 7. An integrated circuit comprising: one or more logic blocks to generate one or more system-operation signals at one or more system-operation clock rates; a system bus; and a service processor unit, said service processor unit comprising: a control unit; a buffer memory; and a system bus interface, wherein said service processor unit is adapted to perform capture and analysis of system operation signals on said system bus during normal system operation through said system bus interface. 8. The integrated circuit according to claim 7, further comprising at least one port selected from the group consisting of: a parallel I/O (PIO) port, a serial I/O (SIO) port, and a JTAG port; wherein data and instructions are to be sent through at least one of said ports to said service processor unit from an external diagnostics console, and wherein result data is to be sent through at least one of said ports from said service processor unit to said external diagnostics console. 9. The integrated circuit according to claim 7, wherein said service processor unit is adapted to perform debug operations of said integrated circuit. 10. The integrated circuit according to claim 7, wherein said service processor unit is adapted to monitor said integrated circuit. 2 U.S. Patent No. 8,239,716 Asserted Claims: 1-3 1. An integrated circuit comprising: one or more logic blocks configured to generate one or more system operation signals at one or more system operation clock rates; a service processor unit configured to perform one or more debug operations on one or more of said logic blocks, the service processor unit comprising: a control unit, a buffer memory, an analysis engine, and a bus interface; and a multiplicity of probe lines configured to capture and propagate one or more of said one or more system operation signals from said logic blocks to said service processor unit during normal system operation; wherein said analysis engine is configured to align signals received from said probe lines during normal system operation. 2. The integrated circuit as in claim 1, wherein said analysis engine includes a variable first-in, first-out (FIFO) element. 3. The integrated circuit as in claim 1, wherein said analysis engine is configured to store aligned signals in said buffer memory. 1 U.S. Patent No. 8,996,938 Asserted Claims: 1-22 1. An integrated circuit comprising: one or more logic blocks configured to generate one or more system operation signals at one or more system operation clock rates; a service processor unit configured to perform one or more debug operations on one or more of the logic blocks, the service processor unit comprising: a control unit configured to control the service processor unit; a memory; an analysis engine; and a bus interface; and a multiplicity of probe lines configured to capture and propagate one or more of the one or more system operation signals from the logic blocks to the service processor unit. 2. The integrated circuit of claim 1, wherein the analysis engine is configured to align signals received from the probe lines. 3. The integrated circuit of claim 1, wherein the analysis engine includes a variable first- in, first-out (FIFO) element. 4. The integrated circuit of claim 1, wherein the analysis engine is configured to store aligned signals in buffer memory. 5. The integrated circuit of claim 1, wherein the service processor unit further comprises a parallel I/O port, wherein data and instructions are sent through the parallel I/O port to the service processor unit from an external console, and wherein result data is provided through the parallel I/O port to the external console. 6. The integrated circuit of claim 1, wherein the service processor unit further comprises a serial I/O port, wherein data and instructions are sent through the serial I/O port to the 1 service processor unit from an external console, and wherein result data is provided through the serial I/O port to the external console. 7. The integrated circuit of claim 1, wherein the service processor unit further comprises a JTAG port, wherein data and instructions are sent through the JTAG port to the service processor unit from an external console, and wherein result data is provided through the JTAG port to the external console. 8. The integrated circuit of claim 1, wherein the multiplicity of probe lines includes at least one analog probe line. 9. The integrated circuit of claim 1, wherein the multiplicity of probe lines includes at least one digital probe line. 10. The integrated circuit of claim 9, wherein the digital probe line comprises at least one storage element and is configured to move one or more of the system operation signals from one or more of the logic blocks to the service processor unit via the bus interface. 11. The integrated circuit of claim 10, wherein the at least one storage element is configured to use a system clock to move the one or more of the system operation signals. 12. The integrated circuit of claim 1, wherein the control unit is configured to execute instructions for providing test signals to one or more of the logic blocks and for retrieving one or more test signal results from one or more of the logic blocks. 13. The integrated circuit of claim 1, wherein the bus interface is a test bus interface. 14. The integrated circuit of claim 1, further comprising: a test access port controller. 2 15. An integrated circuit comprising: a multiplicity of logic blocks configured to generate one or more system operation signals; a logic analyzer coupled to at least one external interface; and a multiplicity of probe lines configured to propagate signals to the logic analyzer, wherein at least one of the probe lines is configured to propagate at least one of the system operation signals, and wherein the logic analyzer is configured to: store a selected set of the system operation signals for retrieval through the at least one external interface; and align the selected set of system operation signals. 16. The integrated circuit of claim 15, wherein the logic analyzer includes a variable first- in, first-out (FIFO) element. 17. The integrated circuit of claim 15, wherein at least one of the probe lines is configured to propagate at least one signal representing at least one analog event. 18. The integrated circuit of claim 17, wherein the at least one analog event comprises a ground bounce event. 19. The integrated circuit of claim 15, further comprising an analog-event detection circuit, wherein at least one of the probe lines is configured to propagate one or more signals from the analog-event detection circuit. 20. The integrated circuit of claim 19, wherein the analog-event detection circuit is configured to detect a voltage level. 21. The integrated circuit of claim 15, wherein the multiplicity of probe lines includes at least one digital probe line. 3 22. An integrated circuit comprising: one or more logic blocks configured to generate one or more system operation signals at one or more system operation clock rates; a service processor unit configured to perform one or more debug operations on one or more of the logic blocks, the service processor unit comprising: a control unit; a memory; an analysis engine; and a bus interface; and a multiplicity of probe lines configured to capture one or more of the one or more system operation signals from the logic blocks to the service processor unit, wherein the analysis engine is configured to align signals received from the probe lines. 4