American Patents LLC v. Mediatek, Inc. et al

Western District of Texas, txwd-6:2018-cv-00339

Appendix B

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APPENDIX B Defendants' Constructions for Disputed Claim Terms (terms ordered as they appear in Defendants' brief) Claim Term Defendants' Proposed Construction "align signals" / "align … "correct path delay differences between the probe points of signals" the multiplicity of probe lines" "aligned signals" "signals that result from being aligned (see 'align signals' construction)" "means to align said signals Means plus function: propagated through said probe lines to create aligned signals" Function: align said signals propagated through said probe lines to create aligned signals; Structure: no corresponding structure. Alternatively, if this means-plus-function term is not limited to being an element of the "input ports of said on-chip logic analyzer," the corresponding structure is the variable FIFO shift registers 804, as shown in Figs. 9a and 9b, and equivalents thereof. "means to capture said aligned Means plus function: signals" Function: capture said aligned signals; Structure: no corresponding structure. Alternatively, if this means-plus-function term is not limited to being an element of the "input ports of said on-chip logic analyzer," the corresponding structure is the output from the variable FIFO shift registers 804 (such output labeled 814 in Figs. 9a/9c, which is also an input to buffer memory 218), and equivalents thereof. 1 Claim Term Defendants' Proposed Construction "means to transfer said aligned Means plus function: signals out of said integrated circuit" Function: transfer said aligned signals out of said integrated circuit; Structure: no corresponding structure. Alternatively, if this means-plus-function term is not limited to being an element of the "on-chip logic analyzer," the corresponding structure is the TAP interface 217 and the SIO interface 210, as shown in Fig. 2, and equivalents thereof. "means to capture said signals Means plus function: from said probe lines" Function: capture said signals from said probe lines; Structure: channels of the logic analyzer 215, as shown in Fig. 11, and equivalents thereof. Alternatively, if this means-plus-function term is not limited to being an element of the "input ports of said on-chip logic analyzer," the corresponding structure is input terminals of analysis engine 215, and equivalents thereof. "debug operations "operations that identify errors in captured signals" "variable first-in, first-out "first-in, first-out (FIFO) element that delays the incoming (FIFO) element" signal by a programmable number of clock cycles" "result data" "data resulting from the execution of the instructions on the data received from the external [diagnostics] console" "during normal system Plain and ordinary meaning operation" The plain and ordinary meaning of "during normal system operation" includes operations under test constraints or in a test mode. 2 Claim Term Defendants' Proposed Construction The preamble of the asserted The preamble is not limiting claims: "An integrated circuit comprising:" 3