American Patents LLC v. Mediatek, Inc. et al

Western District of Texas, txwd-6:2018-cv-00339

BRIEF by Broadcom Corporation, Broadcom PTE. Ltd., MediaTek USA Inc., MediaTek, Inc., NXP B.V., NXP Semiconductors N.V., NXP USA, Inc., Qualcomm Incorporated, Qualcomm Technologies, Inc.

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0 IN THE UNITED STATES DISTRICT COURT FOR THE WESTERN DISTRICT OF TEXAS WACO DIVISION AMERICAN PATENTS LLC,)) Plaintiff,) v.) CIVIL ACTION No. 6:18-CV-339-ADA) MEDIATEK INC., MEDIATEK USA INC.,) JURY TRIAL DEMANDED BROADCOM PTE LTD, BROADCOM) CORPORATION, LENOVO (SHANGHAI)) ELECTRONICS TECHNOLOGY CO. LTD.,) LENOVO GROUP, LTD., NXP) SEMICONDUCTORS N.V., NXP B.V., NXP) USA, INC., QUALCOMM INCORPORATED) and QUALCOMM TECHNOLOGIES, INC.,) Defendants. DEFENDANTS' OPENING CLAIM CONSTRUCTION BRIEF 0 TABLE OF CONTENTS I. SUMMARY OF THE ARGUMENT ................................................................................ 1 II. BACKGROUND OF THE TECHNOLOGY OF THE ASSERTED PATENTS ............. 1 III. LEGAL STANDARDS FOR CLAIM CONSTRUCTION ............................................... 3 A. Proper claim construction focuses on the intrinsic evidence: the patent claims, the patent specification, and the prosecution history................................. 3 B. Extrinsic evidence may help in understanding the plain and ordinary meaning of claim terms .......................................................................................... 4 C. Construing "means-plus-function" claim terms is a two-step process that requires identification of the corresponding structure for performing the claimed function..................................................................................................... 4 D. A "plain and ordinary meaning" construction is inappropriate if there is a fundamental dispute over the meaning or scope of a claim term or if a term is a technical term .................................................................................................. 5 IV. CONSTRUCTIONS OF THE DISPUTED CLAIM TERMS .......................................... 7 A. The "align signals" terms: "align signals" ('716 Patent, claim 1; '938 Patent, claims 2, 22); "align. . . signals" ('001 Patent, claim 5; '938 Patent, claim 15); "aligned signals" ('001 Patent, claims 5-6; '716 Patent, claim 3; '938 Patent, claim 4) ................................................................................ 7 1. Defendants' construction of "align signals" is consistent with the plain language of the claims and the specification .................................... 7 2. Defendants' construction of "aligned signals" is consistent with the plain language of the claims ...................................................................... 9 3. Plaintiff's construction of "plain and ordinary meaning" does not resolve the Parties' dispute and does not account for the technical nature of the terms ..................................................................................... 9 B. The "means-plus-function" limitations of Claims 5-6 of the '001 Patent ........... 10 1. The "means-plus-function" limitations for aligning signals, capturing aligned signals, and transferring aligned signals ..................... 10 a. Claims 5-6 are directed to a specific embodiment of the "analysis engine" in the form of an "on-chip logic analyzer" ...................................................................................... 11 b. The "on-chip logic analyzer" to which claims 5 and 6 are directed does not align signals and, thus, there is no corresponding structure clearly linked to the claimed functions ....................................................................................... 13 c. There is no corresponding structure clearly linked to the "input ports of said on-chip logic analyzer" ................................ 15 i 0 2. "means to capture said signals from said probe lines" ('001 Patent, claim 5). ................................................................................................... 17 a. Defendants' construction correctly identifies the corresponding structure for performing the claimed function in the "on-chip logic analyzer" embodiment ................. 17 b. Plaintiff erroneously identifies the "input terminals of analysis engine 215" as the corresponding structure ................... 18 C. "debug operations" ('371 Patent, claim 9; '716 Patent, claim 1; '938 Patent, claims 1, 22) ............................................................................................. 19 1. Defendants' construction is consistent with the plain language of the claims, the specification, and the established meaning of "debug" .................................................................................................... 19 2. Plaintiff's "plain and ordinary meaning" construction does not account for the technical nature of the term, and does not address the Parties' dispute regarding the term .................................................... 20 D. "variable first-in, first-out (FIFO) element" ('716 Patent, claim 2; '938 Patent, claims 3, 16) ............................................................................................. 22 1. Defendants' construction is consistent with the plain language of the claims and the intrinsic evidence ....................................................... 22 2. Plaintiff's "plain and ordinary meaning" construction does not account for the technical nature of the term, and fails to address the "variable" aspect of the term.................................................................... 23 E. "result data" ('371 Patent, claims 2, 8; '938 Patent, claims 5-7) ......................... 24 1. Defendants' construction is consistent with the plain language of the claims and the specification ............................................................... 24 2. Plaintiff's "plain and ordinary meaning" proposal does not address the Parties' dispute, as shown by Plaintiff's "Alternative" (and improper) proposed construction ............................................................. 25 F. "during normal system operation" ('371 Patent, claims 1, 7; '716 Patent, claim 1) ................................................................................................................ 26 1. Defendants' construction is consistent with the previous construction of this term by the Patent Trial and Appeal Board.............. 26 2. Plaintiff's construction is inconsistent with the PTAB's previous construction .............................................................................................. 27 G. The preamble of the asserted claims: "An integrated circuit comprising:" ........ 28 V. CONCLUSION ................................................................................................................ 30 ii 0 TABLE OF AUTHORITIES Page(s) Cases Altiris, Inc. v. Symantec Corp., 318 F.3d 1363 (Fed. Cir. 2003)............................................................................................4, 11 Am. Med. Sys., Inc. v. Biolitec, Inc., 618 F.3d 1354 (Fed. Cir. 2010)................................................................................................28 Apple, Inc. v. Samsung Elecs. Co., 2014 U.S. Dist. LEXIS 8157 (N.D. Cal. Jan. 21, 2014) ..........................................................27 Catalina Mktg. Int'l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801 (Fed. Cir. 2002)............................................................................................28, 29 Clare v. Chrysler Grp. LLC, 819 F.3d 1323 (Fed. Cir. 2016)............................................................................................6, 25 Eon Corp. IP Holdings v. Silver Spring Networks, 815 F.3d 1314 (Fed. Cir. 2016)..............................................................................................5, 6 Erfindergemeinschaft Uropep GBR v. Eli Lilly & Co., Case No. 2:15-cv-1202-WCB, 2016 WL 7042234 (E.D. Tex. Aug. 11, 2016).........................6 Function Media, LLC v. Google Inc., 708 F.3d 1310 (Fed. Cir. 2013)........................................................................................ passim Fundamental Innovation Sys. Int'l LLC v. Samsung Elecs. Co., Ltd., Case No. 2:17-cv-145-JRG-RSP, 2018 WL 647734 (E.D. Tex. Jan. 31, 2018) ......................29 GEODynamics, Inc. v. DynaEnergetics US, Inc., Case No. 2:17-cv-00371-RSP, 2018 WL 2123616 (E.D. Tex. May 8, 2018) ...........7, 9, 20, 23 Lemaire Illumination Techs., LLC v. HTC Corp., Case No. 2:18-cv-00021-JRG, 2019 WL 1996676 (E.D. Tex. May 6, 2019) ...........6, 9, 20, 23 Markman v. Westview Instruments, Inc., 52 F.3d 967, 980 (Fed. Cir. 1995)..............................................................................................4 Mark I Marketing Corp. v. Donnelley Sons Co., 66 F.3d 285 (Fed. Cir. 1995)....................................................................................................27 MPHJ Tech. Invs., LLC v. Ricoh Americas Corp., 847 F.3d 1363 (Fed. Cir. 2017)..................................................................................................3 iii 0 Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359 (Fed. Cir. 2008)........................................................................................ passim Noah Sys., Inc. v. Intuit, Inc., 675 F.3d 1302 (Fed. Cir. 2012)........................................................................................ passim O2 Micro Int'l Ltd. v. Beyond Innovation Tech. Co., Ltd., 521 F.3d 1351 (Fed. Cir. 2008)........................................................................................ passim Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005)..........................................................................................3, 4, 6 Renishaw PLC v. Marposs Societa' per Azioni, 158 F.3d 1243, 1250 (Fed. Cir. 1998)..................................................................................3, 21 Vederi, LLC v. Google, Inc., 744 F.3d 1376 (Fed. Cir. 2014)..................................................................................................3 Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576 (Fed. Cir. 1996)....................................................................................................3 Whirlpool Corp. v. TST Water, LLC, Case No. 2:15-cv-1528-JRG, 2016 WL 3959811 (E.D. Tex. July 22, 2016) ............7, 9, 20, 23 Williamson v. Citrix Online, LLC, 792 F.3d 1339 (Fed. Cir. 2015)..................................................................................................5 Statutes 35 U.S.C. § 112 ¶ 2 ..........................................................................................................................5 35 U.S.C. § 112, ¶ 6 .....................................................................................................................4, 5 iv 0 TABLE OF EXHIBITS Exhibit No. Exhibit Description 1 U.S. Patent No. 6,964,001 2 U.S. Patent No. 7,836,371 3 U.S. Patent No. 8,239,716 4 U.S. Patent No. 8,996,938 Provisional Patent Application No. 60/079,316, entitled "On-Chip Service 5 Processor" filed March 25, 1998 Excerpts from Exhibit 4-1 to American Patents' Supplement to its Preliminary 6 Infringement Contentions, dated October 4, 2019 Excerpts from IEEE Standard Dictionary of Electrical and Electronics Terms, 7 Sixth Edition Board Decision in Inter Partes Reexamination No. 95/001,579 involving U.S. 8 Patent No. 7,080,301 v 0 TABLE OF APPENDICES Appendix A: Text of the asserted claims of the Asserted Patents with disputed claim terms highlighted Appendix B: Table of disputed claim terms and Defendants' proposed constructions Appendix C: Table of agreed constructions for identified claim terms vi 0 I. SUMMARY OF THE ARGUMENT The Parties have identified specific terms and limitations found in the asserted claims of U.S. Patent Nos. 6,964,001 ("'001 Patent" (Ex. 1)), 7,836,371 ("'371 Patent" (Ex. 2)), 8,239,716 ("'716 Patent" (Ex. 3)), and 8,996,938 ("'938 Patent (Ex. 4)) (collectively, the "Asserted Patents") that they contend require construction. Defendants' proposed constructions should be adopted because they are rooted in the intrinsic evidence and properly capture the scope of the claimed systems as understood by a person of skill in the art. In contrast, Plaintiff attempts to expand the scope of the asserted claims far beyond what was contemplated by—or disclosed in—the Asserted Patents. Additionally, Plaintiff asserts that some of the disputed claim terms should simply be given their "plain and ordinary meaning," without identifying what that "meaning" is. Such a (lack of) construction fails to resolve the Parties' disputes concerning the meaning of those terms. As the authorities presented herein show, Plaintiff's approach is improper, and the Court should therefore adopt Defendants' proposed constructions for the disputed claim terms of the Asserted Patents. II. BACKGROUND OF THE TECHNOLOGY OF THE ASSERTED PATENTS The Asserted Patents issued from continuation applications in the same patent family and all share a common specification and figures.1 The Asserted Patents relate "to the testing and debugging of electronic systems, and, in particular, to on-chip circuits for the test and diagnosis of problems in an integrated circuit." '938 Patent, Ex. 4, at 1:28-31. According to the Asserted Patents, "more and more digital systems, or parts of digital systems, are being integrated in a single component" and "[t]he resulting complexity and lack of observability of an integrated circuit poses 1 Unless otherwise noted, Defendants cite to the specification of the '938 Patent (Exhibit 4) in support of their positions. 0 serious problems for the test, debug and bring-up stages of the (IC)." Id. at 1:53-57. Additionally, "[t]he size of [ICs] has grown in gate count to the point where it has become inefficient and expensive to test and debug ICs using traditional scan techniques." Id. To account for these alleged problems, Applicants suggested that "[a]s IC technology continues to advance, it has become cost effective and desirable to include a service processor embedded within the IC itself." Prov. App. No. 60/079,316, Ex. 5, at 1. According to Applicants, prior art "service processors[] have often been incorporated into the circuit boards of [large electronic systems]." '938 Patent, Ex. 4, at 1:40-42. These prior art "[service] processors," Applicants explained, "have a number of useful functions, including the control of scan strings in the system; the origination of diagnostic signal probes to run on the system, and … also have diagnostic and scan debug features, including access to the internal registers and memory within the system." Id. at 1:42-48. Further, the Asserted Patents describe that "logic analyzer probes have often been used in the testing and debugging of electronic systems." Id. at 1:32-33. The specification notes, however, that "observation at the IC component pins of the behavior of an IC system is increasingly difficult." Id. at 1:58-59. According to Applicants, [t]he IC component pins may be very far (in terms of logic hierarchy) from the actual points of interest. The extremely high frequency of digital IC operations and the frequency filtering effects of the large capacitance of the external logic analyzer probes, often prevents a logic analyzer from capturing signals reliably and precisely. There is always an uncertainty regarding the accuracy of signals captured by an external logic analyzer compared to the actual signals values within the IC. Id. at 1:59-67. The alleged invention provides that "special on-chip circuits are used to observe the internal workings of an IC." Id. at 2:45-47. The specification notes that "[m]any more points in the IC system are accessed than is feasible with conventional external test and debug processors." 2 0 Id. at 2:49-51. Moreover, the specification notes that the alleged "invention also permits the coupling of probes to internal IC points. The points may be selected from a larger number of internal points that may be observed with an external logic analyzer. Besides the greater observability of the internal operations of the IC, the present invention also improves the accuracy of the observations, as compared to an external logic analyzer." Id. at 2:56-62. III. LEGAL STANDARDS FOR CLAIM CONSTRUCTION A. Proper claim construction focuses on the intrinsic evidence: the patent claims, the patent specification, and the prosecution history Claim construction seeks to ascribe the "ordinary and customary meaning" to claim terms as they would be understood by a person of ordinary skill in the art at the time of invention. Phillips v. AWH Corp., 415 F.3d 1303, 1313 (Fed. Cir. 2005) (en banc). The primary evidence for construing the claim terms is the intrinsic evidence—the claim language, the patent specification, and the prosecution history. The first step is to consider the claim language. Id. at 1312–14. Claim terms are not construed in a vacuum, however, as a person of ordinary skill in the art "is deemed to read the claim term not only in the particular claim in which the disputed term appears, but in the context of the entire patent, including the specification." Id. at 1313. A patent's specification "is the single best guide to the meaning of a disputed claim term," and "[u]sually, it is dispositive." Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996). "The construction that stays true to the claim language and most naturally aligns with the patent's description of the invention will be, in the end, the correct construction."2 Phillips, 415 F.3d at 1316 (quoting Renishaw PLC v. Marposs Societa' per Azioni, 158 F.3d 1243, 1250 (Fed. Cir. 1998)). 2 A provisional application can provide guidance as to the proper claim construction. MPHJ Tech. Invs., LLC v. Ricoh Americas Corp., 847 F.3d 1363, 1369 (Fed. Cir. 2017); Vederi, LLC v. Google, Inc., 744 F.3d 1376, 1383 (Fed. Cir. 2014). 3 0 A court must also look to the patent prosecution history because it is part of the public record and contains the complete record of proceedings before the Patent Office. Id. at 1317. The prosecution history "can often inform the meaning of the claim language by demonstrating how the inventor understood the invention and whether the inventor limited the invention in the course of prosecution, making the claim scope narrower than it would otherwise be." Id. B. Extrinsic evidence may help in understanding the plain and ordinary meaning of claim terms The Federal Circuit has "also authorized district courts to rely on extrinsic evidence, which 'consists of all evidence external to the patent and prosecution history, including expert and inventor testimony, dictionaries, and learned treatises.'" Id. (quoting Markman v. Westview Instruments, Inc., 52 F.3d 967, 980 (Fed. Cir. 1995) (en banc), aff'd, 517 U.S. 370 (1996)). For example, technical dictionaries may help the court "'better understand the underlying technology' and the way in which one of skill in the art might use the claim terms." Id. at 1318 (quoting Vitronics, 90 F.3d at 1584 n.6). C. Construing "means-plus-function" claim terms is a two-step process that requires identification of the corresponding structure for performing the claimed function When a claim uses the word "means" followed by a recited function, courts presume that 35 U.S.C. § 112, ¶ 6 applies. Altiris, Inc. v. Symantec Corp., 318 F.3d 1363, 1375 (Fed. Cir. 2003). Once a term is determined to be a means-plus-function limitation, the court must construe the term by identifying (1) "the function of the limitation" and then (2) "the corresponding structure in the written description that is necessary to perform that function." Id. Structure disclosed in the specification is "corresponding" structure only if the specification clearly links or associates that structure to the function recited in the claim. Id. The only structure that is relevant is that structure that the patent actually links to the claimed function. It does not matter that one of skill in the art might envision other structures that perform the 4 0 function. "A patentee cannot avoid providing specificity as to structure simply because someone of ordinary skill in the art would be able to devise a means to perform the claimed function." Function Media, LLC v. Google Inc., 708 F.3d 1310, 1319 (Fed. Cir. 2013); see also Williamson v. Citrix Online, LLC, 792 F.3d 1339, 1354 (Fed. Cir. 2015) ("The testimony of one of ordinary skill in the art cannot supplant the total absence of structure from the specification."). If there is no corresponding structure that is clearly linked to the claimed function, then the claim is indefinite and invalid. Function Media, 708 F.3d at 1318-19. Indeed, the Federal Circuit requires the Court to consider indefiniteness as part of claim construction. "Whether a claim complies with the definiteness requirement of 35 U.S.C. § 112 ¶ 2 is a matter of claim construction. . . . Means-plus-function claim limitations must satisfy the requirements of § 112 ¶ 2." Noah Sys., Inc. v. Intuit, Inc., 675 F.3d 1302, 1311 (Fed. Cir. 2012). That is the entire point of potential indefiniteness of means-plus-function limitations—i.e., the claims cannot be construed because they fail to comply with Section 112, paragraph 6. Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1364 (Fed. Cir. 2008) ("As part of its construction of the claim terms, the district court invalidated [specific asserted claims], which contain limitations in means-plus-function format, as lacking corresponding structure and thus indefinite under 35 U.S.C. § 112 ¶ 2."). D. A "plain and ordinary meaning" construction is inappropriate if there is a fundamental dispute over the meaning or scope of a claim term or if a term is a technical term It is for a court, not the jury, to make the legal determination of the proper construction of claim terms. Eon Corp. IP Holdings v. Silver Spring Networks, 815 F.3d 1314, 1319 (Fed. Cir. 2016); O2 Micro Int'l Ltd. v. Beyond Innovation Tech. Co., Ltd., 521 F.3d 1351, 1362-63 (Fed. Cir. 2008). In making that determination, claims generally must be construed according to their plain and ordinary meaning as understood by a person of skill in the art. O2 Micro, 521 F.3d at 1360. However, "in many cases, the meaning of a claim term as understood by persons of skill in 5 0 the art is not readily apparent." Id. (citing Phillips, 415 F.3d at 1312-13). When the parties dispute the meaning of a claim term, failing to construe the disputed term or determining that the term has a "plain and ordinary meaning" is inadequate, as such a determination fails to provide the necessary guidance to the jury on the meaning of the term and fails to resolve the parties' dispute. See Eon, 815 F.3d at 1318-19. Additionally, a court must provide a construction even if the parties do not dispute "the meaning of the words themselves, but [dispute] the scope" encompassed by the claim language. O2 Micro, 521 F.3d at 1361; see also Clare v. Chrysler Grp. LLC, 819 F.3d 1323, 1329- 30 (Fed. Cir. 2016) (finding it proper to construe claim terms because "[a]lthough those words may be readily apparent to a lay person there existed a fundamental dispute regarding the scope of those limitations"). In such situations, the Federal Circuit has found legal error when terms were construed as simply having their plain and ordinary meaning, thereby leaving it to the jury to decide the proper claim scope. See, e.g., Eon, 815 F.3d at 1319; O2 Micro, 521 F.3d at 1362-63; see also Erfindergemeinschaft Uropep GBR v. Eli Lilly & Co., Case No. 2:15-cv-1202-WCB, 2016 WL 7042234, at *2 (E.D. Tex. Aug. 11, 2016) (refusing to construe term as plain and ordinary meaning because it would violate the requirement to resolve a "fundamental dispute" over claim scope). As such, "[w]hen the parties present a fundamental dispute regarding the scope of a claim term, it is the court's duty to resolve it." O2 Micro, 521 F.3d at 1362. Further, when a disputed claim term is a technical term that would not be readily understood by a jury of laypersons, the court should construe the term to avoid any confusion. Indeed, courts routinely construe such technical terms, rather than applying the "plain and ordinary meaning," to assist the jury in understanding the claims. See, e.g., Lemaire Illumination Techs., LLC v. HTC Corp., Case No. 2:18-cv-00021-JRG, 2019 WL 1996676, at *7 (E.D. Tex. May 6, 6 0 2019) (construing term "pulsed power," rather than applying "plain and ordinary meaning," because the term "is a technical concept that would not be readily understood by a lay juror [and] the jury would benefit from a construction that help explains [sic] the term."); GEODynamics, Inc. v. DynaEnergetics US, Inc., Case No. 2:17-cv-00371-RSP, 2018 WL 2123616, at *6 (E.D. Tex. May 8, 2018) (construing the term "a green compacted particulate" because it was a technical term and construction would assist the jury in understanding the claims); Whirlpool Corp. v. TST Water, LLC, Case No. 2:15-cv-1528-JRG, 2016 WL 3959811, at *11 (E.D. Tex. July 22, 2016) (construing "proximal" and "distal" because they "are technical terms and are potentially confusing," and "construction. . . will assist the jury to understand the claims"). IV. CONSTRUCTIONS OF THE DISPUTED CLAIM TERMS 3 A. The "align signals" terms: "align signals" ('716 Patent, claim 1; '938 Patent, claims 2, 22); "align. . . signals" ('001 Patent, claim 5; '938 Patent, claim 15); "aligned signals" ('001 Patent, claims 5-6; '716 Patent, claim 3; '938 Patent, claim 4) Defendants' Proposed Construction Plaintiff's Proposed Construction align signals / align. . . signals – "correct Plain and ordinary meaning path delay differences between the probe points of the multiplicity of probe lines" aligned signals – "signals that result from being aligned (see 'align signals' construction)" 1. Defendants' construction of "align signals" is consistent with the plain language of the claims and the specification The claims including the "align signals" terms require "a multiplicity of probe lines configured to capture and propagate … signals from said logic blocks," and that the "analysis engine [be] configured to align signals received from [the] probe lines." '716 Patent, Ex. 3, at 3 Plaintiff has asserted the following claims: '001 Patent claims 5-6; '371 Patent claims 2, 7-10; '716 Patent claims 1-3; and '938 Patent claims 1-22. See Appendix A for the claim language. 7 0 Claim 1; '938 Patent, Ex. 4, at Claims 2, 22.4 The specification of the Asserted Patents makes clear that the claimed "analysis engine configured to align signals" is meant to "compensate[] for the path delay differences among the different probe points by realigning capture times of signals captured in the analysis engine 215." 5 '938 Patent, Ex. 4, at 10:56-58; see also 4:13-15, 10:17-58 (describing the "Analysis Engine's input aligner" shown in Figs. 9a and 9b). Likewise, in the Provisional Application to which the Asserted Patents claim priority, the Applicants explained that "[t]he output from the [analysis engine] are realigned in time so the designer or user can detect timing and cycle errors easily," and further explained that the analysis engine "essentially compensates for the path delay differences from the different probe points being accessed." Prov. App. No. 60/079,316, Ex. 5, at 5-6. Construing "align signals" to "correct" for such "path delay differences" is necessary as the individual probe points along the multiple probe lines may be at different "sequential depths." '938 Patent, Ex. 4, at 5:14-16. Thus, respective signals generated at probe points will not be received simultaneously by the analysis engine, i.e., they will have different path delays. To compensate for the path delay differences among the different probe points, the specification explains that the capture times of signals captured in the analysis engine are subsequently realigned. Id. at 10:56-58, 10:17-58, 12:62-65, Figs. 9a, 9b (disclosing signal alignment to correct path delay differences in every disclosed embodiment); see also Prov. App. No. 60/079,316, Ex. 5, at 5-6 ("The output from the [analysis engine] are realigned in time so the designer or user can detect timing and cycle errors easily."). 4 Claim 15 of the '938 Patent similarly claims a "logic analyzer … configured to … align the selected set of system operation signals." Ex. 4 at Claim 15. 5 Unless otherwise noted, all emphasis has been added. 8 0 The intrinsic record thus makes clear that "alignment" in the Asserted Patents is specific to aligning the signals to correct path delay differences between the probe points of the multiplicity of probe lines where the individual probe points may be at different "sequential depths" in the integrated circuit. As such, Defendants' proposed construction should be adopted by the Court. 2. Defendants' construction of "aligned signals" is consistent with the plain language of the claims The plain language of the claims makes clear that "aligned signals" are the result of the means to align or the analysis engine "align[ing] signals." '001 Patent, Ex. 1, at Claim 5 ("means to align said signals. . . to create aligned signals"); '716 Patent, Ex. 3, at Claims 1, 3 ("analysis engine is configured to align signals" and "store aligned signals"); '938 Patent, Ex. 4, at Claims 2, 4 (same). Thus, the claims confirm that the "aligned signals" are simply the "signals that result from being aligned"—that is, after the signals go through the aligning process (i.e., after path delay differences are corrected), the signals are properly "aligned." 3. Plaintiff's construction of "plain and ordinary meaning" does not resolve the Parties' dispute and does not account for the technical nature of the terms In its Supplemental Preliminary Infringement Contentions, Plaintiff suggests the scope of what is required to "align signals" in the context of the asserted claims is broader than the proper construction Defendants propose herein. See, e.g., Supp. Prelim. Inf. Cont., Ex. 6, at 37 (inferring that captured signals are "aligned" in the accused functionality by simply inserting a time stamp into "trace streams"). As such, there is a fundamental dispute regarding the scope of these terms, and the Court must construe the "align" terms to resolve that dispute. See O2 Micro, 521 F.3d at 1362. Further, "align signals" and "aligned signals" are technical terms that may not be readily understood by a jury of laypersons. See Lemaire Illumination Techs, 2019 WL 1996676, at *7; GEODynamics, 2018 WL 2123616, at *6; Whirlpool, 2016 WL 3959811, at *11. Thus, the Court 9 0 should construe these terms consistently with the language of the claims and the specification (as outlined above) to allow the jury to apply these terms in its infringement and validity analyses. B. The "means-plus-function" limitations of Claims 5-6 of the '001 Patent 1. The "means-plus-function" limitations for aligning signals, capturing aligned signals, and transferring aligned signals "means to align said signals propagated through said probe lines to create aligned signals" ('001 Patent, claim 5) Defendants' Proposed Construction Plaintiff's Proposed Construction FUNCTION: align said signals propagated FUNCTION: align said signals propagated through said probe lines to create aligned through said probe lines to create aligned signals; signals; STRUCTURE: no corresponding structure. STRUCTURE: input aligner portion of analysis engine 215 (as shown in Fig. 9a) or Alternatively, if this means-plus-function term probe storage elements 1000 (as shown in Fig. is not limited to being an element of the "input 11), and equivalents thereof. ports of said on-chip logic analyzer," the corresponding structure is the variable FIFO shift registers 804, as shown in Figs. 9a and 9b, and equivalents thereof. "means to capture said aligned signals" ('001 Patent, claim 5) Defendants' Proposed Construction Plaintiff's Proposed Construction FUNCTION: capture said aligned signals; FUNCTION: capture said aligned signals; STRUCTURE: no corresponding structure. STRUCTURE: variable FIFO 804 (as shown in Fig. 9a), probe storage elements 1000 or Alternatively, if this means-plus-function term buffer memory 218 (as shown in Fig. 11), and is not limited to being an element of the "input equivalents thereof. ports of said on-chip logic analyzer," the corresponding structure is the output from the variable FIFO shift registers 804 (such output labeled 814 in Figs. 9a/9c, which is also an input to buffer memory 218), and equivalents thereof. "means to transfer said aligned signals out of said integrated circuit" ('001 Patent, claim 6) Defendants' Proposed Construction Plaintiff's Proposed Construction FUNCTION: transfer said aligned signals out FUNCTION: transfer said aligned signals out of of said integrated circuit; said integrated circuit; STRUCTURE: no corresponding structure. STRUCTURE: TAP interface 217, SIO interface 210, PIO interface 216, or scan data output terminal SO. 10 0 Alternatively, if this means-plus-function term is not limited to being an element of the "on- chip logic analyzer," the corresponding structure is the TAP interface 217 and the SIO interface 210, as shown in Fig. 2, and equivalents thereof. The Parties agree that the identified "means" limitations of claims 5 and 6 of the '001 Patent are written in means-plus-function format. As such, the Court must construe the terms by identifying (1) "the function of the limitation," and then (2) "the corresponding structure in the written description that is necessary to perform that function." Altiris, 318 F.3d at 1375. As to the first step, the Parties agree on the claimed functions. Thus, the only dispute is whether the specification clearly links a corresponding structure to the claimed function and, if so, the identification of that structure. a. Claims 5-6 are directed to a specific embodiment of the "analysis engine" in the form of an "on-chip logic analyzer" Although the specification of the Asserted Patents discloses multiple embodiments, claims 5 and 6 of the '001 Patent are directed to a specific embodiment. In particular, claims 5 and 6 recite "an on-chip logic analyzer with a multiplicity of input ports," wherein "said input ports of said on-chip logic analyzer" comprise the "means to capture said signals from said probe lines," the "means to align said signals. . . to create aligned signals," and the "means to capture said aligned signals," and wherein the on-chip logic analyzer also comprises "means to transfer said aligned signals out of said integrated circuit." '001 Pat., Ex. 1, at Claims 5, 6. The "on-chip logic analyzer" language is the key language that limits these claims to a specific embodiment in the '001 Patent. The '001 Patent provides a specific description for that embodiment starting at column 12, line 37. The specific embodiment discloses that the analysis engine 215 "is implemented in the form of an on-chip logic analyzer (OLA) which captures sequential snapshots 11 0 of sets of signals [that] form the digital probes 202." Id. at 12:45-48. Thus, claims 5 and 6 claim a specific type of analysis engine – i.e., an "on-chip logic analyzer." This is important because, while both the "analysis engine" and "on-chip logic analyzer" are "components that capture signals for analysis" (as agreed by the Parties), there are several critical differences between the disclosed embodiments that use each respective component. In the embodiments using the "analysis engine" disclosed in column 10 (hereinafter "analysis engine embodiment"), signal alignment is done on-chip. Id. at 10:19-61, Figs. 9a, 9b. On the other hand, in the embodiment using the "on-chip logic analyzer" disclosed in column 12, signal alignment is done off-chip. Id. at 12:45-13:7. This is a crucial distinction that results from differences in the disclosed structure and function of the respective embodiments. Specifically, the analysis engine embodiment relies on circuitry that is programmable by the service processor unit (SPU) and microprocessor to align the signals. See, e.g., id. at 10:20-22 ("Fig. 9a shows an embodiment of the analysis engine 215, which under the control of the microprocessor 211, captures logic signals…."), 10:54-56 ("The shift depth of each variable FIFO 804 is programmable by the SPU 101 by setting a count register 810 for each bit feeding the analysis engine 215.") In contrast, in the on-chip logic analyzer embodiment, the specification makes clear that "the SPU 101 does not include an embedded microprocessor 211." Id. at 12:37-39; see also 12:37- 13:3. Instead, in the on-chip logic analyzer embodiment, "the channels of the logic analyzer 215 … form a distributed serial shift register which acts as a pipeline to move data captured at a probe point towards the end of the logic analyzer channel where the data are stored in buffer memory 218." Id. at 12:53-58, Fig. 11. The specification explains that "[s]ubsequently, after the captured data has been transported to the external diagnostics console 103, software processes use the 12 0 number of PSEs 1000 on each channel of the analysis engine 215 to align the data with respect to one another." Id. at 13:4-7. In other words, the on-chip logic analyzer embodiment does not have any circuitry necessary to perform on-chip signal alignment. Nevertheless, claims 5-6 are directed to an on- chip logic analyzer that includes specific "means" for aligning signals, for capturing aligned signals, and for transferring aligned signals out of the integrated circuit. Because there is no support for this claim in the specification, there is no corresponding structure in the claimed on- chip logic analyzer clearly linked to the claimed functions. As a result, claims 5 and 6 of the '001 Patent are indefinite. See Function Media, 708 F.3d at 1318-19; Noah Sys., 675 F.3d at 1311; Net MoneyIN, 545 F.3d at 1364. Plaintiff's proposed constructions seemingly acknowledge this fatal defect by providing alternative structures for the "means" limitations from both the claimed on- chip logic analyzer embodiment and the traditional (unclaimed) analysis engine embodiment. b. The "on-chip logic analyzer" to which claims 5 and 6 are directed does not align signals and, thus, there is no corresponding structure clearly linked to the claimed functions The specification discloses that the on-chip logic analyzer is used to capture sequential snapshots of sets of signals that form the digital probes 202. '001 Patent, Ex. 1, at 12:45-58. As explained above in Section IV.A.1, the individual probe points may be at different "sequential depths." Thus, once data is captured, it must be aligned for further analysis. For the claimed on-chip logic analyzer embodiment, however, the specification clearly and unequivocally discloses that signal alignment only occurs off-chip in the external diagnostics console. Id. at 13:4-7 ("Subsequently, after the captured data has been transported to the external diagnostics console 103, software processes use the number of PSEs 1000 on each channel of the [logic analyzer] 215 to align the data with respect to one another."). The specification clearly links "software processes" within the "external diagnostics console 103" as 13 0 the structure used to perform the claimed function of "align[ing] said signals propagated through said probe lines to create aligned signals." No other structures are clearly linked to this function when an on-chip logic analyzer is used. The specification therefore fails to clearly link any structure of the on-chip logic analyzer to performing the claimed function of the "means to align said signals propagated through said probe lines to create aligned signals." As a result, claim 5 is indefinite. See Function Media, 708 F.3d at 1318-19; Noah Sys., 675 F.3d at 1311; Net MoneyIN, 545 F.3d at 1364. Likewise, because the signals are not aligned until "after the captured data has been transported to the external diagnostics console 103" ('001 Patent, Ex. 1, at 13:4-7), there are no "aligned signals" within the claimed on-chip logic analyzer—the aligned signals only exist off- chip within the external diagnostics console. Thus, there are no aligned signals to be captured by the on-chip logic analyzer, and the specification fails to clearly link any structure of the on-chip logic analyzer to the claimed function of "captur[ing] said aligned signals." As such, the "means to capture said aligned signals" limitation is indefinite, and claim 5 is invalid for this reason as well. See Function Media, 708 F.3d at 1318-19; Noah Sys., 675 F.3d at 1311; Net MoneyIN, 545 F.3d at 1364. Similarly, dependent claim 6 of the '001 Patent adds the limitation: "wherein said on-chip logic analyzer further comprises means to transfer said aligned signals out of said integrated circuit." '001 Patent, Ex. 1, at Claim 6. But again, because the signals are not aligned until "after the captured data has been transported to the external diagnostics console 103" ('001 Patent, Ex. 1, at 13:4-7), there are no "aligned signals" within the claimed on-chip logic analyzer. Thus, there are no aligned signals to be transferred out of the integrated circuit, and the specification fails to clearly link any structure of the on-chip logic analyzer to the claimed function of "transfer[ing] 14 0 said aligned signals out of said integrated circuit." As such, the "means to transfer said aligned signals out of said integrated circuit" limitation is indefinite, and claim 6 is also invalid. See Function Media, 708 F.3d at 1318-19; Noah Sys., 675 F.3d at 1311; Net MoneyIN, 545 F.3d at 1364. c. There is no corresponding structure clearly linked to the "input ports of said on-chip logic analyzer" Even assuming arguendo that the specification of the '001 Patent clearly linked appropriate structure to the claimed functions of the identified means-plus-function limitations (which it does not), any such structure is not part of the "input ports of said on-chip logic analyzer" as recited by claim 5. See '001 Patent, Ex. 1, at Claim 5 (claiming the "means to align said signals. . ." and the "means to capture said aligned signals" as part of the "input ports of said on-chip logic analyzer"). Claim 5 recites that each of the claimed probe lines "is adapted to capture signals from said logic blocks and to propagate said signals to one of said multiplicity of input ports of said on-chip logic analyzer." Id. The plain language of the claim makes clear that the signals must first be captured and transmitted to the on-chip logic analyzer, where they are received through the input ports of the on-chip logic analyzer, before the signals can be aligned. There is no disclosure in the specification, however, of any corresponding structure within the "input ports of the on-chip logic analyzer" that actually performs the subsequent function of "align[ing] said signals propagated through said probe lines to create aligned signals."6 Disregarding this fact, Plaintiff identifies "input aligner portion of analysis engine 215 (as shown in Fig. 9a)" as the corresponding structure that performs the function of "align[ing] said signals propagated through said probe lines to create aligned signals." However, the "input aligner 6 This is not surprising given that the specification discloses that such alignment occurs off- chip in the claimed on-chip logic analyzer embodiment. '001 Patent, Ex. 1, at 13:4-7. 15 0 portion of analysis engine 215" is disclosed with respect to the analysis engine embodiment only, and does not exist in the on-chip logic analyzer embodiment. Compare '001 Patent, Ex. 1, at 10:19-11:9, Figs. 9a, 9b with id. at 12:37-14:16, Figs. 11-13. Thus, such structure is not part of the "input ports of the on-chip logic analyzer." Likewise, there is no disclosure in the specification of any corresponding structure within the "input ports of the on-chip logic analyzer" that actually performs the additional function of "captur[ing] said aligned signals." Again, disregarding this fact, Plaintiff identifies a hodge-podge of structures – including "variable FIFO 804 (as shown in Fig. 9a), probe storage elements 1000 or buffer memory 218 (as shown in Fig. 11)."7 However, the "variable FIFO 804" is only disclosed with respect to the analysis engine embodiment, and does not exist in the on-chip logic analyzer embodiment. Compare '001 Patent, Ex. 1, at 10:19-11:9, Figs. 9a, 9b with id. at 12:37-14:16, Figs. 11-13. Similarly, "buffer memory 218" is not part of the "input ports of the on-chip logic analyzer." See id. at 12:53-13:3 (disclosing that the non-aligned data is transmitted through the channels of the on-chip logic analyzer to the end of the channels where data is stored in buffer memory 218), Fig. 11 (showing the buffer memory 218 as a separate component from the on-chip logic analyzer channels). Thus, because the specification fails to clearly link any structure of the "input ports of said on-chip logic analyzer" to the claimed function of "align[ing] said signals. . ." and "captur[ing] said aligned signals," the "means to align said signals. . ." and the "means to capture said aligned 7 For both the "means to align" and the "means to capture said aligned signals" limitations, Plaintiff alternatively proposes that "probe storage elements 1000 (as shown in Fig. 11)" are the corresponding structure that performs the claimed functions. Because signal alignment is expressly disclosed as occurring off-chip in the claimed on-chip logic analyzer embodiment, there is no disclosure in the specification that supports Plaintiff's position that the "probe storage elements 1000" perform the claimed functions in the on-chip logic analyzer. 16 0 signals" limitations are indefinite,8 and claim 5 is invalid for this reason as well.9 See Function Media, 708 F.3d at 1318-19; Noah Sys., 675 F.3d at 1311; Net MoneyIN, 545 F.3d at 1364. 2. "means to capture said signals from said probe lines" ('001 Patent, claim 5). Defendants' Proposed Construction Plaintiff's Proposed Construction FUNCTION: capture said signals from said FUNCTION: capture said signals from said probe lines; probe lines; STRUCTURE: channels of the logic STRUCTURE: input terminals of analysis analyzer 215, as shown in Figure 11, and engine 215 (as shown in Fig. 9a) or channels equivalents thereof. of the logic analyzer 215 (as shown in Fig. 11), and equivalents thereof. Alternatively, if this means-plus-function term is not limited to being an element of the "input ports of said on-chip logic analyzer," the corresponding structure is input terminals of analysis engine 215, and equivalents thereof. The Parties agree that this limitation is written in mean-plus-function format and that the claimed function is to "capture signals from said probe lines." Thus, the only dispute is what structure in the specification is clearly linked to that claimed function. a. Defendants' construction correctly identifies the corresponding structure for performing the claimed function in the "on-chip logic analyzer" embodiment This term is part of the "on-chip logic analyzer" embodiment of claim 5 of the '001 Patent. The specification clearly links the channels of logic analyzer 215 (as shown in Figure 11) to the function of "captur[ing] said signals from said probe lines." See '001 Patent, Ex. 1, at 12:48-53 8 Out of an abundance of caution, Defendants provide an "alternative" construction identifying structure found in the traditional analysis engine embodiment in the event the identified means-plus-function terms are not limited to being an element of the "on-chip logic analyzer." 9 Plaintiff identifies "TAP interface 217, SIO interface 210, PIO interface 216, or scan data output terminal SO" as the corresponding structure for the "means to transfer said aligned signals out of said integrated circuit." However, for the claimed on-chip logic analyzer embodiment, the specification does not disclose how the aligned signals are transferred out of the integrated circuit and, thus, does not clearly link any structure to the claimed function. See '001 Patent, Ex. 1, at 12:37-14:16. 17 0 ("coupling the signals for digital probes 202 to the channels of the [on-chip logic analyzer] 215. . . to allow the signals on the digital probes 202 value to be captured onto channels of the logic analyzer 215"), 12:53-58 ("As shown in FIG. 11, the channels of the logic analyzer 215 are formed from probe storage elements (PSE) 1000 to form a distributed serial shift register which acts as a pipeline to move data captured at a probe point towards the end of the logic analyzer channel where the data are stored in buffer memory 218."), 12:65-66 ("This way all signals captured on the [on- chip logic analyzer] 215 channels. . . ."), 13:4-7 ("Subsequently, after the captured data has been transported to the external diagnostics console 103, software processes use the number of PSEs 1000 on each channel of the [on-chip logic analyzer] 215 to align the data with respect to one another."). Consistent with the Parties' agreed construction for the term "capture," the referenced passages in the specification disclose capturing signals/data – i.e., acquiring data in a form that is capable of storage – in the channels of logic analyzer 215, which are depicted in Figure 11. b. Plaintiff erroneously identifies the "input terminals of analysis engine 215" as the corresponding structure Plaintiff's proposed structure again ignores that claim 5 of the '001 Patent is directed to the "on-chip logic analyzer" embodiment. It is evident Plaintiff is relying on the wrong embodiment given that it identifies the corresponding structure as "input terminals of analysis engine 215 (as shown in Fig. 9a)," which is not relevant to the embodiment covered by claim 5. Thus, Plaintiff's construction fails to link a corresponding structure found in the "on-chip logic analyzer" to the claimed function, and Plaintiff's identification of the "input terminals of analysis engine 215" should be disregarded.10 10 Consistent with Defendants' construction, Plaintiff's construction also identifies "channels of the logic analyzer 215 (as shown in Fig. 11)" as the corresponding structure for performing the claimed function of "captur[ing] said signals from said probe lines." As set forth in Section IV.B.2, that is the structure that is clearly linked to performing the claimed function and should be included in the construction of "means to capture said signals from said probe lines." 18 0 C. "debug operations" ('371 Patent, claim 9; '716 Patent, claim 1; '938 Patent, claims 1, 22) Defendants' Proposed Construction Plaintiff's Proposed Construction "operations that identify errors in captured Plain and ordinary meaning signals" Alternatively: "diagnostic operations" 1. Defendants' construction is consistent with the plain language of the claims, the specification, and the established meaning of "debug" The asserted claims containing the term "debug operations" require, among other things, "one or more logic blocks [that] generate one or more system operation signals" and "a multiplicity of probe lines [that] capture and propagate one or more of the. . . system operation signals from the logic blocks to the service processor unit." '938 Patent, Ex. 4, at Claims 1, 22; see also '371 Patent, Ex. 2, at Claim 7 ("wherein said service processor unit is adapted to perform capture and analysis of system operation signals on said system bus. . ."). The plain language of the claims also requires that the "service processor unit" (SPU) is configured or adapted "to perform one or more debug operations" on the logic blocks of the integrated circuit. '716 Patent, Ex. 3, at Claim 1; '938 Patent, Ex. 4, at Claims 1, 22, '371 Patent, Ex. 2, at Claim 9. The specification explains that it is the signals from the logic blocks that have been captured and sent to the SPU that are processed during the "debug operations." See, e.g., '938 Patent, Ex. 4, at 2:66–3:49. Specifically, the specification explains that "scan lines. . . are loaded with the test signals for the logic blocks. . . The logic blocks are then operated. . . and the resulting test signal results are retrieved from the logic blocks. . . The test signal results are stored in the memory. . . and the stored test results signals are processed in the control unit [of the SPU] . . . to perform test and debug operations of the logic blocks." Id. at 3:37-49. As such, the plain language of the claims and the specification require that the SPU perform the "debug operations" utilizing the captured signals. 19 0 While the specification does not expressly identify what types of operations constitute "debug operations," it does shed light on the meaning of this term when it generally discusses "testing" and "debugging" of the integrated circuit. Specifically, the specification explains that "[t]he present invention is related to the testing and debugging of electronic systems, and, in particular, to on-chip circuits for the test and diagnosis of problems in an integrated circuit." Id. at 1:28-31. Extrinsic evidence also confirms that the meaning of the term "debug" is "[t]o examine or test a procedure, routine, or equipment for the purpose of detecting and correcting errors." IEEE STANDARD DICTIONARY OF ELECTRICAL AND ELECTRONICS TERMS, Ex. 7, at 260. Detecting, or identifying, errors is exactly what is done when one "diagnos[es] problems" in an integrated circuit. Coupling the plain language of the claims and the teachings of the specification with the ordinary meaning of "debug," the claimed "debug operations" are "operations that identify errors in captured signals," as Defendants' construction proposes. 2. Plaintiff's "plain and ordinary meaning" construction does not account for the technical nature of the term, and does not address the Parties' dispute regarding the term Plaintiff's proposed construction of "plain and ordinary meaning" disregards that the term "debug operations" is a technical term that may not be readily understood by a jury of laypersons, and therefore should be construed. See Lemaire Illumination Techs, 2019 WL 1996676, at *7; GEODynamics, 2018 WL 2123616, at *6; Whirlpool, 2016 WL 3959811, at *11. Additionally, Plaintiff's proposed construction of "plain and ordinary meaning" does not address the Parties' dispute as to the proper scope of "debug operations," as shown by Plaintiff's "alternative" proposed construction of "diagnostic operations." Plaintiff's alternative construction is imprecise and incomplete, as such construction simply substitutes the word "diagnostic" for "debug," but does not shed any light as to what such "diagnostic operations" actually are—thereby failing to provide the jury with any guidance as to what qualifies as a "debug operation." In 20 0 contrast, Defendants' construction specifically identifies what "debug operations" are— "operations that identify errors"—and specifically identifies where such errors are identified—"in captured data." Thus, Defendants' construction provides the guidance the jury needs as to the proper meaning and scope of this term. Plaintiff's alternative construction is also contrary to the specification. The specification uses the word "diagnostic" twenty times and never equates "diagnostic" with "debug." Specifically, the specification discloses that "[t]he SPU 101 provides a connection for an external diagnostics console 103 to view and test the internal workings of the IC 100." '938 Patent, Ex. 4, at 6:27-29, Fig. 1b. Likewise, in addressing prior art "service processors," the specification states that such "separate processors have a number of useful functions, including … the origination of diagnostic signal probes to run on the system…. The service processors also have diagnostic and scan debug features, including access to the internal registers and memory within the system." Id. at 1:43-48. Thus, the specification does not use "diagnostic" and "debug" interchangeably, but rather suggests a distinction between "diagnostic" features and "debug" features. Plaintiff's alternative construction improperly broadens the scope of the claims by equating "diagnostic" with "debug," which according to the specification are different. As such, Plaintiff's alternative construction does not accurately reflect the meaning of "debug operation," and should be rejected. See Renishaw PLC v. Marposs Societa' per Azioni, 158 F.3d 1243, 1250 (Fed. Cir. 1998) ("The construction that stays true to the claim language and most naturally aligns with the patent's description of the invention will be, in the end, the correct construction.") 21 0 D. "variable first-in, first-out (FIFO) element" ('716 Patent, claim 2; '938 Patent, claims 3, 16) Defendants' Proposed Construction Plaintiff's Proposed Construction "first-in, first-out (FIFO) element that delays Plain and ordinary meaning the incoming signal by a programmable number of clock cycles" 1. Defendants' construction is consistent with the plain language of the claims and the intrinsic evidence The claims in which this term appears require that the "analysis engine [or logic analyzer] includes a variable first-in, first-out (FIFO) element." '716 Patent, Ex. 3, at Claim 2; '938 Patent, Ex. 4, at Claims 3, 16. A "first-in, first-out (FIFO) element" is a well-known term in the relevant art. As its name implies, a FIFO element "pertain[s] to a system in which the next item to exit the system is the item that has been in the system for the longest time" and is synonymous with "first- come, first-served." IEEE STANDARD DICTIONARY OF ELECTRICAL AND ELECTRONICS TERMS, Ex. 7, at 412. The claim limitation, however, is not simply a "FIFO element," but is a "variable first- in, first-out (FIFO) element," and the word "variable" in this term must be given meaning. The claims do not offer any guidance as to how a FIFO can be "variable." The specification makes clear, however, that the "variable FIFO" is the "Analysis Engine's input aligner" shown in Figure 9b. '938 Patent, Ex. 4, at 4:14-15, 10:45:58. In particular, the specification uses "variable FIFO" in a single context: FIG. 9b shows the circuit details of each variable First-In-First-Out shift register (FIFO) 804, each having a number of serially-connected register stages 812. Each register stage 812 has a multiplexer which, under control of a decoder 811, selects between the signal held in a flip-flop of that stage or the incoming signal to the stage to place on the stage's output terminal. The shift depth of each variable FIFO 804 is programmable by the SPU 101 by setting a count register 810 for each bit feeding the analysis engine 215. The value in the count register 810 is decoded by the decoder 811. The result controls the number of register stages 812 which are bypassed. This compensates for the path delay differences among the different probe points by realigning capture times of signals captured in the analysis engine 215. 22 0 Id. at 10:45-58. In other words, if two signals to be received by the analysis engine have a "shift depth" difference of, for example, five (i.e., the first signal will be received five clock cycles before the second signal), the variable FIFO associated with the second signal will be programmed to bypass five more register stages than the variable FIFO associated with the first signal. When the first signal is received, the variable FIFO will select signals held in flip-flops (rather than the first signal) for five clock cycles. As a result, the first signal will be delayed such that the first and second signals will be input into and output from their respective variable FIFOs simultaneously. Thus, consistent with the description of a "variable" FIFO in the specification, this term should be construed to mean a "first-in, first-out (FIFO) element that delays the incoming signal by a programmable number of clock cycles." 2. Plaintiff's "plain and ordinary meaning" construction does not account for the technical nature of the term, and fails to address the "variable" aspect of the term Plaintiff's proposed construction of "plain and ordinary meaning" does not account for the fact that the term "variable first-in, first-out (FIFO) element" is a technical term that may not be readily understood by a jury of laypersons. See Lemaire Illumination Techs, 2019 WL 1996676, at *7; GEODynamics, 2018 WL 2123616, at *6; Whirlpool, 2016 WL 3959811, at *11. Thus, the Court should construe this term consistent with how it is described in the specification (as outlined above). Additionally, Plaintiff's construction breeds confusion as it sheds no light on the "variable" component of the term, and should be rejected. Plaintiff's proposed "plain and ordinary meaning" construction presumably relies on the fact that a "first-in, first-out (FIFO) element" has an understood meaning in the art. As noted, however, this does not account for the word "variable" in this term. Applicants specifically chose to claim a "variable first-in, first-out (FIFO) element"—and not simply a "first-in, first-out (FIFO) element." As such, the "variable" nature of 23 0 the FIFO element must be given meaning, and failing to address such meaning improperly fails to resolve the Parties' dispute. See O2 Micro, 521 F.3d at 1361. E. "result data" ('371 Patent, claims 2, 8; '938 Patent, claims 5-7) Defendants' Proposed Construction Plaintiff's Proposed Construction "data resulting from the execution of the Plain and ordinary meaning instructions on the data received from the external [diagnostics] console" Alternatively: "data resulting from a testing process" 1. Defendants' construction is consistent with the plain language of the claims and the specification The plain language of the claims makes clear that "result data" is the product of instructions executing on data in a service processor unit that were originally sent to the SPU from an external console. For example, as shown in claim 5 of the '938 Patent, "data and instructions are sent through the parallel I/O port to the service processor unit from an external console." '938 Patent, Ex. 4, at Claim 5. After the instructions are executed on that data, "result data is provided through the parallel I/O port [back] to the external console." Id. This process is consistent in each of the relevant claims, the only difference being the "port" through which the initial instructions and data are initially sent, and through which the "result data" is sent back. See, e.g., '371 Patent, Ex. 2, at Claim 2 ("… wherein data and instructions are to be sent through at least one of said ports to said service processor unit from an external diagnostics console, and wherein result data is to be sent through at least one of said ports from said service processor unit to said external diagnostics console."). Thus, Defendants' construction of "data resulting from the execution of the instructions on the data received from the external [diagnostics] console" is consistent with and grounded in the plain language of the claims. The specification further supports Defendants' proposed construction. The specification states that "[p]rogram instructions and initial data values for executing programs to implement 24 0 the functions of the SPU 101 are loaded from the diagnostics console 103 (see FIG 1b) into the buffer memory 218 of the SPU 101." '938 Patent, Ex. 4, at 12:1-4. After the instructions are executed on the initial data, the SPU then "send[s] said data out to the diagnostic console 103. Typically, a separate program executed on the diagnostic console 103 displays this information in a human readable format as may be appropriate for the given application" Id. at 12:10-13. Thus, in light of the plain language of the claims and the specification, the term "result data" should be construed as "data resulting from the execution of the instructions on the data received from the external [diagnostics] console," as Defendants propose. 2. Plaintiff's "plain and ordinary meaning" proposal does not address the Parties' dispute, as shown by Plaintiff's "Alternative" (and improper) proposed construction Plaintiff's "plain and ordinary meaning" construction does not address the Parties' dispute as to the proper scope of the term "result data." According to Plaintiff, any data coming from the service processor unit as the result of "a testing process" would qualify as the disputed "result data." However, the plain language of all the relevant claims makes clear that "result data" must result from the execution of "data and instructions [that] are sent through [a] port to the service processor unit from an external console." See, e.g., id. at Claim 5. Because Plaintiff's proposed construction fails to capture this requirement, there is a significant dispute between the Parties, and thus a construction of "plain and ordinary meaning" is inappropriate for this term. See O2 Micro, 521 F.3d at 1361; see also Clare, 819 F.3d at 1329-30 (finding that district court was correct to construe claim terms because "[a]lthough those words may be readily apparent to a lay person there existed a fundamental dispute regarding the scope of those limitations" (citing O2 Micro, 521 F.3d at 1361)). Further, because Plaintiff's "alternative" construction fails to capture this requirement, it is broader than the plain language of the relevant claims and inconsistent with the 25 0 description in the specification. Plaintiff's "alternative" construction for "result data" should therefore be rejected. F. "during normal system operation" ('371 Patent, claims 1, 7; '716 Patent, claim 1) Defendants' Proposed Construction Plaintiff's Proposed Construction Plain and ordinary meaning. Plain and ordinary meaning The plain and ordinary meaning of "during The plain and ordinary meaning of "during normal system operation" includes operations normal system operation" may include test under test constraints or in a test mode. and debug operations. 1. Defendants' construction is consistent with the previous construction of this term by the Patent Trial and Appeal Board The Parties agree that the "normal system operation" term should be accorded its plain and ordinary meaning. The Parties dispute, however, whether such plain and ordinary meaning includes operations under test constraints or in a test mode. This term was previously construed by the Patent Trial and Appeal Board ("Board"), and the Court should adopt the Board's previous construction and find that the plain and ordinary meaning of "during normal system operation" includes operations under test constraints or in a test mode. Specifically, after a thorough claim construction analysis, the Board construed this term in Inter Partes Reexamination No. 95/001,579 ("the '301 Reexam"), relating to U.S. Patent No. 7,080,301 ("the '301 Patent," which is the parent of the '371 Patent and grandparent of the '716 Patent). Decision, Ex. 8, at 16-38 (correctly focusing on language in the '301 Patent at 14:22-45 (corresponding to the '716 Patent at 14:8-30), as well as Figures 4a, 4b, 5, and 9a). There, the Board found that "normal system operation" does not "preclude[] the application of test data or operation in a test mode." Id., at 35, 38. In other words, a system can still be exhibiting "normal system operation" when it is under test constraints or in a test mode. Indeed, the Board found that the specification contemplates a scenario where an integrated circuit is exhibiting normal system 26 0 operation under test constraints. See id. at 27-32 (citing '716 Patent at 14:8-30). Accordingly, the Board construed the term "normal system operation" in the '301 Patent to "not exclude the IC or portions of the IC from being under test or in a test mode."11 Id. at 37-38. Because the '301 Patent shares a substantively identical specification with the '371 and '716 Patents, the "during normal system operation" term should be construed consistently with how the Board construed it in the '301 Reexam. See Mark I Marketing Corp. v. Donnelley Sons Co., 66 F.3d 285, 291 (Fed. Cir. 1995) (relevant prosecution history includes not only the current application but also the parent and grandparent applications); Apple, Inc. v. Samsung Elecs. Co., 2014 U.S. Dist. LEXIS 8157, at *117-18 (N.D. Cal. Jan. 21, 2014) (construing "heuristic" based on how "heuristic algorithm" was construed in a related patent with a virtually identical specification). There is no reason to depart from the Board's previous analysis of this term in the context of the '301 Patent. Accordingly, "normal system operation" should be accorded its plain and ordinary meaning, which includes operation under test constraints or in a test mode. 2. Plaintiff's construction is inconsistent with the PTAB's previous construction Plaintiff refuses to concede that the plain and ordinary meaning of "normal system operation" includes operations under test constraints or in a test mode, instead only agreeing that the term "may include test and debug operations." This is improper because it appears to leave open the possibility that Plaintiff could argue that "normal system operation" excludes operations under test constraints or in a test mode, contrary to the Board's construction in the '301 Reexam. Because "test and debug operations" could arguably still occur in a normal mode of operation 11 In reaching that construction, the Board specifically rejected the patentee's argument that "normal system operation occurs during normal mode and not during test mode when the IC is performing testing operations …." Decision, Ex. 8, at 17. Rather, the Board found that "[t]he term 'normal system operation' as used in the. . . claims and specification is not the same as 'a normal mode of operation of an integrated circuit (IC)' in the context of a normal mode and a test mode." Id. 27 0 without test constraints, Plaintiff's suggestion that the plain and ordinary meaning may include "test and debug operations" does not address the key issue, i.e., whether the term encompasses operation under test constraints or in a test mode. To the extent that Plaintiff intends to argue that "normal system operation" excludes operations under test constraints or in a test mode, that argument should be foreclosed now through the claim construction process. G. The preamble of the asserted claims: "An integrated circuit comprising:" Defendants' Proposed Construction Plaintiff's Proposed Construction The preamble is not limiting The preamble is limiting Generally, a preamble does not limit the claims. Am. Med. Sys., Inc. v. Biolitec, Inc., 618 F.3d 1354, 1358 (Fed. Cir. 2010). A preamble will only be construed as limiting "if it recites essential structure or steps, or if it is necessary to give life, meaning, and vitality to the claim." Catalina Mktg. Int'l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 808 (Fed. Cir. 2002) (internal quotation marks omitted). For each of the asserted claims, the preamble is the same – "[a]n integrated circuit comprising." See, e.g., '938 Patent, Ex. 4, Claims 1-22. As shown below, this preamble does not recite "essential structure," nor is it "necessary to give life, meaning, and vitality to the claim." Thus, the preamble of the asserted claims should not be limiting. While there is no "litmus test" for whether a preamble is limiting, a preamble is generally not limiting if "the claim body describes a structurally complete invention such that deletion of the preamble phrase does not affect the structure or steps of the claimed invention." Catalina, 289 F.3d. at 809. Here, the term "integrated circuit" in the preamble provides no structural support for the body of the asserted claims, and thus can be deleted from the claim without affecting the structure of the alleged invention. As one example, claim 1 of the '938 Patent recites "one or more logic blocks configured to generate one or more system operation signals," "a service processor unit … comprising … a control unit … a memory … an analysis engine … and a bus interface," 28 0 and a "multiplicity of probe lines configured to capture and propagate one or more … system operation signals from the logic blocks to the service processor unit." '938 Patent, Ex. 4, at Claim 1. The presence or absence of the "integrated circuit" preamble has no impact on the structure of the alleged invention. Thus, the preamble should not be limiting. As further evidence that the respective bodies of each of the asserted claims set forth a structurally complete invention without the preamble, the term "integrated circuit" does not appear in the body of any of the independent claims, and thus does not provide antecedent basis for any of the terms in those claims. When a preamble provides antecedent basis for a term later used in the claim, it "may limit claim scope because it indicates a reliance on both the preamble and claim body to define the claimed invention." Catalina, 289 F.3d. at 808 (finding that a preamble term that appeared in the body of the claim was limiting, but was not limiting where it did not appear in the body of a different claim). However, even when a preamble provides antecedent basis, the preamble is not limiting if it uses generic technological terms and does not provide detail necessary to understand what is claimed by the later use of those same terms. Fundamental Innovation Sys. Int'l LLC v. Samsung Elecs. Co., Ltd., Case No. 2:17-cv-145-JRG-RSP, 2018 WL 647734, at *22 (E.D. Tex. Jan. 31, 2018) (finding that the term "mobile device" appearing as part of the preamble was not limiting despite providing antecedent basis later in the claim because the preamble did not "recite[] any additional relevant detail regarding the 'mobile device'"). Here, like the term "mobile device" in the Fundamental Innovation case, "integrated circuit" is a generic term. It does not connote any specific structure beyond what is provided in the body of the claims. The figures of the Asserted Patents confirm that this was purposeful, as the figures identify the "integrated circuit" as merely a rectangular-shaped dotted line. See '938 Patent, Ex. 4, at 6:12-13, Figs. 1a, 1b. That Plaintiff did not attempt to construe the term 29 0 "integrated circuit," even though Plaintiff claims the preamble of the asserted claims is limiting, is even further evidence that the term "integrated circuit" is not "essential structure," nor is it "necessary to give life, meaning, and vitality to the claim." As such, the preamble of the asserted claims should not be construed as limiting. V. CONCLUSION Based on the foregoing arguments, evidence, and authorities, the Court should construe each term as Defendants propose and should reject Plaintiff's erroneous constructions and improper reliance on "plain and ordinary meaning" for its proposed constructions. 30 0 Dated: October 25, 2019 Respectfully submitted, /s/ Tyler T. VanHoutan Tyler T. VanHoutan Texas Bar No. 24033290 Eric S. Schlichter Texas Bar No. 24007994 MCGUIREWOODS LLP 600 Travis St., Suite 7500 Houston, TX 77002 (713) 571-9191 (713) 571-9652 (Fax) tvanhoutan@mcguirewoods.com eschlichter@mcguirewoods.com Rebecca Levinson (Admitted Pro Hac Vice) MCGUIREWOODS LLP 2001 K Street N.W., Suite 400 Washington, DC 20006 (202) 828-2816 (202) 828-3322 (Fax) rlevinson@mcguirewoods.com Paige Arnette Amstutz Texas Bar No. 00796136 SCOTT, DOUGLASS & MCCONNICO, LLP 303 Colorado St., Suite 2400 Austin, TX 78701 (512) 495-6300 (512) 495-6399 (Fax) pamstutz@scottdoug.com Counsel for MediaTek Inc., MediaTek USA Inc., Broadcom Pte Ltd., Broadcom Corporation, NXP Semiconductors N.V., NXP B.V., NXP USA, Inc., Qualcomm Incorporated and Qualcomm Technologies, Inc. 31 0 Gilbert A. Greene Jonah D. Mitchell (Admitted Pro Hac Vice) Texas Bar No. 24045976 Doyle B. Johnson (Admitted Pro Hac Vice) Pierre J. Hubert Osman Mohammed (Admitted Pro Hac Vice) Texas Bar No. 24002317 REED SMITH LLP DUANE MORRIS LLP 101 2nd St., Suite 1800 900 S. Capital of Texas Hwy, Suite 300 San Francisco, CA 94105 Austin, TX 78746 (415) 543-8700 (512) 277-2300 (415) 391-8269 (Fax) (512) 277-2301 (Fax) jmitchell@reedsmith.com BGreene@duanemorris.com dbjohnson@reedsmith.com PJHubert@duanemorris.com omohammed@reedsmith.com Kevin Anderson (Admitted Pro Hac Vice) R. Jeffrey Layne DUANE MORRIS, LLP Texas Bar No. 00791083 505 9th St., N.W., Suite 1000 Megan Alter Hudgeons Washington, DC 20004-2166 Texas Bar No. 24001645 (202) 776-7800 REED SMITH LLP kpanderson@duanemorris.com 111 Congress Ave., Suite 400 Austin, TX 78701 Counsel for NXP Semiconductors N.V., (512) 563-1816 NXP B.V., NXP USA, Inc., (512) 623-1802 (Fax) Qualcomm Incorporated and mhudgeons@reedsmith.com Qualcomm Technologies, Inc. jlayne@reedsmith.com Counsel for Qualcomm Incorporated and Qualcomm Technologies, Inc. Eric W. Schweibenz (Admitted Pro Hac Vice) John S. Kern (Admitted Pro Hac Vice) Alexander B. Englehart (Admitted Pro Hac Vice) Oblon, McClelland, Maier & Neustadt, LLP 1940 Duke Street Alexandria, VA 22314 (703) 413-3000 eschweibenz@oblon.com jkern@oblon.com aenglehart@oblon.com Counsel for MediaTek Inc. and MediaTek USA Inc. 32 0 CERTIFICATE OF SERVICE Pursuant to the Federal Rules of Civil Procedure and Local Rule CV-5, I hereby certify that all counsel of record who have appeared in this case are being served on this 25th day of October 2019, with a copy of the foregoing via the Court's CM/ECF system. /s/ Tyler T. VanHoutan Tyler T. VanHoutan 33