American Patents LLC v. Mediatek, Inc. et al

Western District of Texas, txwd-6:2018-cv-00339

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9 EXHIBIT 2 Case 6:18-CV-00339-ADA Document MHITA US007836371B2 (12) United States Patent Dervisoglu et al. (10) Patent No.: (45) Date of Patent: US 7,836,371 B2 *Nov. 16, 2010 (54) ON-CHIP SERVICE PROCESSOR (76) Inventors: Bulent Dervisoglu, 495 Sleeper Ave., Mountain View, CA (US) 94040; Laurence H. Cooke, 25399 Spanish Ranch Rd., Los Gatos, CA (US) 95033; Vacit Arat, 4093 Robin Hill Rd., La Canada Flintridge, CA (US) 91011 (56) References Cited U.S. PATENT DOCUMENTS 3,761,695 A 9/1973 Eichelberger 3,783,254 A 1/1974 Eichelberger 3,784,907 A 1/1974 Eichelberger 4,495,629 A 1/1985 Zasio et al. 4,667,339 A 5/1987 Tubbs et al. 4,817,093 A 3/1989 Jacobs et al. 5,065,090 A 11/1991 Gheewala 5,068,881 A 11/1991 Dervisoglu et al. (*) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 904 days. (Continued) OTHER PUBLICATIONS This patent is subject to a terminal dis- claimer. (21) Appl. No.: 11/424,610 (22) Filed: Jun. 16, 2006 (65) Prior Publication Data US 2008/0168309 A1 Jul. 10, 2008 "BIST TPG for Faults in System Backplanes"; Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997, pp. 406-413. (Continued) Primary Examiner-David Ton (74) Attorney, Agent, or Firm Connolly Bove Lodge & Hutz LLP (57) ABSTRACT Related U.S. Application Data (63) Continuation of application No. 11/261,762, filed on Oct. 31, 2005, now Pat. No. 7,080,301, which is a continuation of application No. 10/767,265, filed on Jan. 30, 2004, now Pat. No. 6,964,001, which is a continuation of application No. 09/275,726, filed on Mar. 24, 1999, now Pat. No. 6,687,865. (60) Provisional application No. 60/079,316, filed on Mar. 25, 1998. An integrated circuit is described that includes a stored pro- gram processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable cir- cuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits. (51) Int. CI. GOIR 31/28 (2006.01) (52) U.S. Cl. ........... ............ 714/733; 714/726 (58) Field of Classification Search ........ ....... 714/30 714/39, 733, 726, 727, 729 See application file for complete search history. 10 Claims, 16 Drawing Sheets SPU 101 210 215 c211 212 222 Scan Control SIO Analysis Engine micro- processor BIST engine Parallel 1/0 TAP Test Test 216 Range Check Interrupt Handler -219 Bus Interface Buffer Memory Bus Interface 220 — 213 218 221 - - - - - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - 203 204' Trigger Test Bus 201 Analog Probes 704 System Bus 105 Scan string 403 202 Digital Probes Core Block 106 Test Wrapper 102 U.S. Patent Scan chain 403 315 v probe put scap out 316 - --- 311 Nov. 16, 2010 Data in H d ScanFH: Data2 Data out 320 SFL 317 - - - - - - - - - - - 312 > 313 probe in scan in 314 Sheet 8 of 16 9 Figure 4b Preferred Embodiment of Block Scan Connector US 7,836,371 B2 Scan Cik B Scan Clk A U.S. Patent Scan in Master Scan Slave Scan out Sean---- Data Nov. 16, 2010 Data in Data Slave Data out System Clk 9 Figure 5 Sheet 9 of 16 Internal Scan Element with Separate Scan-Slave and Data-Slave: (prior art) US 7,836,371 B2 9 U.S. Patent | Nov. 16, 2010 Sheet 10 of 16 US 7,836,371 B2 O Threshold check 600 -1 +y Figure 6a | 601 | A+ | 09 | Figure 6b Figure 6c | | 튼 IT | | 603 602 601 - 9 U.S. Patent Nov. 16, 2010 Sheet 11 of 16 US 7,836,371 B2,700 Ground bounce 701 a - - - - -- - - Quiet Ground __705 set 204 704 - Figure 7 OA+ . - Reset o 706 703 Local Ground U.S. Patent 712 Mask Shift Register T EIL 715 Pattern Shift Register Nov. 16, 2010 - - - - - - - - - - -- -- - - - - - - - - - - - -- Mixed BIST / Functional → Scan Vectors --------------------------------- Sheet 12 of 16 9 714 Polynomial Register 711 Figures US 7,836,371 B2 805 U.S. Patent Scan H Variable FIFO. Variable FIFO. Scan & Probe Inputs 804 813 -1- T 801_ 4 Variable FIEO Variable FIFO 804 Nov. 16, 2010 802 - Digital PLL 803 814 Figure 9a 812 9 Sheet 13 of 16 „Variable FIFO 0 2 Decode 811 Count Register #810 804 Figure 9b US 7,836,371 B2 U.S. Patent 822 - Load Buffer Memory Data input Address: | 218 From + Address Counter Variable 814 FIFO 804 7 Stop Counter Start Address 820 Figure 9c -------- 831 Latched Trigger 824 Nov. 16, 2010 -821 835 832 DS 834 - 9 Pro Probe "D Probe NT D Sheet 14 of 16 oday OO Probe NA 1 830 833 836 ST 835 7837 - - - - - - - - - - - - - T[O] Trigger T[n-114 T[n] 838 824 US 7,836,371 B2 Figure 9d Buffer Memory 218 U.S. Patent Data input clk Address From Probes 822 Address Counter Load 824 Latched trigger 902 Clock - - Stop Counter Nov. 16, 2010 SO 4 Start Address ext Stop Count Figure 10 814 9 Sheet 15 of 16 1000 Functional SRL PSE 1001 - Inserted SRL 6 Buffer in Memory B $ Combinational Logic LA Buffer Memory 1001 Direct-Probe Pipeline US 7,836,371 B2 Figure 11 par ponude Direct-Probe Channels - 70-bits U.S. Patent Buffer pati Memory 218 TO Mux'ed-Probe Channel 1001 LA Buffer Memory Nov. 16, 2010 Figure 12 1105 1109 P1 P200 1110 - D 9 1107 Sheet 16 of 16 1108 1111 A_clk -1101 1104 - A_clk 1101 1102 - B_clk - 1109 P_clk -1111 1106 Scan_Mode 1.103 - 1112 1000 US 7,836,371 B2 Figure 13 9 US 7,836,371 B2 vo 1 ON-CHIP SERVICE PROCESSOR selected points of the IC, are also connected to form a serial shift register when the IC is configured in a test mode. CROSS-REFERENCE TO RELATED Straightforward serial shift (i.e., scan) operations are utilized APPLICATIONS to load the flip-flops with desired values, or to read out their 5 present values reflective of the logic states of the selective IC This application is a continuation of U.S. patent applica points. Such ICs require special features to reset the flip-flops tion Ser. No. 11/261,762, filed Oct. 31, 2005 (which issued as (i.e., bring the IC to a known starting state). However, the size U.S. Pat. No. 7,080,301), commonly-assigned, and incorpo of integrated circuits has grown to the point where it has rated by reference in its entirety. That application is a con- become inefficient and expensive to test and debug ICs using tinuation of U.S. patent application Ser. No. 10/767,265, 10 solely conventional scan techniques. entitled, "On-Chip Service Processor," filed on Jan. 30, 2004 Furthermore, variations of the serial scan technique (which issued as U.S. Pat. No. 6,964,001), commonly-as include the use of so-called shadow registers." IC internal signed, and incorporated by reference herein in its entirety. signal states are captured in a duplicate copy, i.e., the shadow That application is a continuation of U.S. patent application register, of certain internal registers. The shadow registers are Ser. No. 09/275,726, entitled, "On-Chip Service Processor," 15 interconnected by a dedicated internal scan chain. A prede- filed on Mar. 24, 1999 (which issued as U.S. Pat. No. 6,687, termined event can trigger a snapshot of the internal state 865), commonly-assigned, and also incorporated by refer values in the shadow registers and the dedicated scan chain ence herein in its entirety. That application, in turn, is entitled shifts the captured signal state without affecting the system to the priority of U.S. Provisional Patent Application No. operation of the IC. However, this approach has several defi- 60/079,316, filed on Mar. 25, 1998. 20 ciencies. First, only a single snapshot can be captured and shifted out with each trigger event. This greatly hampers BACKGROUND OF THE INVENTION debugging the IC since there is not much visibility of the system activity around a point of interest identified by the The present invention is related to the testing and debug trigger event. Secondly, the snapshots can be taken only of ging of electronic systems, and, in particular, to on-chip cir- 25 those signals in registers which have a shadow register coun- cuits for the test and diagnosis of problems in an integrated terpart. Since a shadow register effectively doubles the cir- circuit. cuitry for the register, this approach is very costly to imple- Heretofore, logic analyzer probes have often been used in ment on a large scale in the IC. the testing and debugging of electronic systems. The logic Another test and debug design for ICs is found in a stan- analyzer probes were coupled to the external pins of compo- 30 dard, the IEEE 1149.1 Test Access Port and Boundary-Scan nents of a digital system in order to capture the sequence of Architecture, which prescribes a test controller which signals after a predefined event (or time stamp) occurs. The responds to a set of predetermined instructions and an instruc- captured signals can then be examined to verify correct sys tion register which holds the present instruction which the tem behavior or, alternatively, to identify the time and the controller executes. Each instruction is first loaded into the nature of erroneous behavior in the system. 35 instruction register from a source outside the IC and then that Furthermore, in the designs of large electronic systems, instruction is executed by the controller. While having some separate consoles, or service processors, have often been advantages of versatility and speed, the standard still binds incorporated into the circuit boards of the system. These test and debug procedures to the world external to the IC and separate processors have a number of useful functions, thus, limits its performance. including the control of scan strings in the system; the origi- 40 The present invention recognizes that while the advances in nation of diagnostic signal probes to run on the system, and so IC technology have helped to create the problems forth. The service processors also have diagnostic and scan and debugging an IC, the advances also point the way toward debug features, including access to the internal registers and solving these problems. In accordance with the present inven- memory within the system. The service processors have also tion, special on-chip circuits are used to observe the internal been used to bring-up the main system during its power up 45 workings of an IC. These circuits operate at internal IC clock phase. All of these functions have been useful to system rates so that the limitations of the frequency of signals at the designers for the design, test and debugging of electronic IC input and output (1/0) boundary are avoided. Many more systems. points in the IC system are accessed than is feasible with On the other hand, more and more digital systems, or parts conventional external test and debug processors. Thus the of digital systems, are being integrated in a single component. 50 present invention offers advantages which exceed the The resulting complexity and lack of observability of an straight-forward savings in chip space due to miniaturization. integrated circuit poses serious problems for the test, debug Additionally, the present invention reduces the amount of test and bring-up stages of the integrated circuit (IC). For logic which might have been required elsewhere on the chip. example, observation at the IC component pins of the behav- The present invention also permits the coupling of probes ior of an IC system is increasingly difficult. The IC compo- 55 to internal IC points. The points may be selected from a larger nent pins may be very far (in terms of logic hierarchy) from number of internal points that may be observed with an exter- the actual points of interest. The extremely high frequency of nal logic analyzer. Besides the greater observability of the digital IC operations and the frequency filtering effects of the internal operations of the IC, the present invention also large capacitance of the external logic analyzer probes, often improves the accuracy of the observations, as compared to an ents a logic analyzer from capturing signals reliably and 60 external logic analyzer. precisely. There is always an uncertainty regarding the accu- racy of signals captured by an external logic analyzer com- SUMMARY OF THE INVENTION pared to the actual signals values within the IC. To address the problems of the testing of integrated cir To achieve these ends, the present invention provides for an cuits, special features are being included in many IC designs. 65 integrated circuit logic blocks, a control unit, a memory asso- For example, one standard technique is "scan" whereby, cer ciated with the control unit and a plurality of scan lines. The tain internal flip-flops, which are connected to various memory holds instructions for the control unit to perform test 9 US 7,836,371 B2 449 and debug operations of the logic blocks. The scan lines are FIG. 5 is a circuit diagram of a scan flip-flop in the FIG. 4b responsive to the control unit for loading test signals for the circuit diagram; logic blocks and retrieving test signal results from the logic FIG. 6a is a circuit which generates an out-of-range detec- blocks. The test signals and the test signal results are stored in tion probe signals for range probes; FIGS. 65 and 6c are the the memory so that the loading and retrieving operations are 5 transistor-level circuits of inverters in FIG. 6a; performed at one or more clock signal rates internal to the FIG. 7 is a circuit which generates ground-bounce detec- integrated circuit. The integrated circuit also has a plurality of tion probe signals for range probes; probe lines which are responsive to the control unit for car- FIG. 8 is a block diagram of a Built In Self-Test (BIST) rying system operation signals at predetermined probe points engine of the FIG. 2 SPU; of the logic blocks. The system operation signals are also 10 stored in the memory so that the system operation signals are FIG. Ia is a block diagram of an input aligner portion of retrieved at one or more clock signal rates internal to the Analysis Engine of the FIG. 2 SPU; FIG. 9b is a detail of the FIG. 9a Analysis Engine's input aligner; FIG. 9c is a block integrated circuit. diagram of the Analysis Engine's memory addressing struc- The present invention also provides for an integrated cir ture; FIG.9d is a block diagram of the trigger logic portion of cuit which has an interface for coupling to an external diag- 15 the Analysis Engine; and nostic processor, a unit responsive to instructions from the FIG. 10 is a block diagram of another embodiment of the external diagnostics processor, a plurality of probe lines coupled to the unit, and a memory coupled to the unit and to Analysis Engine's memory addressing structure; the interface. In response to the unit, the probe lines carry FIG. 11 shows a probe string connection of probe points to sequential of sets of system operation signals at predeter- 20 the buffer memory using logic analyzer channels that are mined probe points of the integrated circuit and the system implemented with probe storage elements (PSE); operation signals are stored in the memory at one or more FIG. 12 shows an alternative probe string connection with clock signal rates internal to the integrated circuit. The system improved multiplexed PSEs which combine probe selection operation signals are retrieved from the memory through the and data capture functions; and interface to the external diagnostic processor at one or more 25 FIG.13 is a block diagram of the improved PSE ofFIG. 12. clock signal rates external to the integrated circuit. This allows the external diagnostics processor to process the cap- DESCRIPTION OF THE SPECIFIC tured system operation signals. EMBODIMENTS The present invention further provides for a method of operating an integrated circuit which has logic blocks, a con- 30 General Organization of the Present Invention trol unit, a memory and a plurality of scan lines of the logic blocks. The memory is loaded with test signals and instruc- In accordance with the present invention, a Service Proces- tions for the control unit and the scan lines responsive to the sor Unit (SPU) is incorporated within an integrated circuit. control unit are loaded with the test signals for the logic Besides addressing the problems of testing and debugging the blocks at one or more clock signal rates internal to the inte-- IC, the availability of a programmable unit, such as the SPU, grated circuit. The logic blocks are then operated at one or which may load or unload the state variables into and from the more clock signal rates internal to the integrated circuit and user-definable logic in an IC, greatly simplifies the problem the resulting test signal results are retrieved from the logic of resetting the IC and observing its current state. The SPU is blocks along the scan lines at one or more clock signal rates implemented in the form of a basic stored-program control internal to the integrated circuit. The test signal results are 4 unit, such as a microprocessor, with a predefined instruction stored in the memory at one or more clock signal rates internal set, a number of extended function units (EFUS), program, to the integrated circuit; and the stored test results signals are data, and scratch pad memories, plus an input/output circuit processed in the control unit responsive to the stored instruc- for loading and unloading the SPU memories with data/pro- tions in the memory to perform test and debug operations of grams from the outside world. This allows the SPU to be the logic blocks. programmed to execute a control program which interacts with the various extended functional units to control various BRIEF DESCRIPTION OF THE DRAWINGS test and debug related activities on the IC. Each EFU is designed to control a specific test or debug FIG. la shows a high-level diagram of an exemplary large so feature and the EFU provides the control unit a general. and complex integrated circuit; FIG. 1b shows the FIG. 1a programmable access to that feature. For example, one EFU integrated circuit with a Service Processor Unit (SPU), may be designed to control the execution of serial shift opera- according to one embodiment of the present invention; tions along some or all of the internal scan chains of the IC. FIG. 2 illustrates one embodiment for the architecture for The other EFUs may be enabled to interact with the scan the SPU of FIG. 1b; 55 chains, such as a predetermined algorithm to provide a Built- FIG. 3a illustrates the coupling between test wrappers, In Self-Test (BIST) for an embedded Random Access scan strings, probe strings and range probes to a test bus; FIG. Memory (RAM) block. The existing scan chains load and 3b is a circuit diagram of a test bus connector of FIG. 3a; FIG. unload the BIST patterns and results to/from the RAM 3c is an exemplary connection of multiple test bus connec- The EFUs provide the control unit with a straight forward, tors; 60 programmable means for controlling the functions of the FIG. 4a is a circuit diagram of a block input/output con- EFU such that knowledge of low level details of the scan or nector for test wrappers for observing test points outside a BIST functions become unnecessary. block along a boundary-scan chain (for example, IEEE With its program and data memories, the SPU acts autono- 1149.1 standard Test Access Port and Boundary Scan Archi- mously once its program memory has been loaded with the tecture); FIG. 4b is a circuit diagram of a block scan connector 65 desired instruction sequence. The SPU's program memory for scan strings for observing test points inside a block along may be loaded with the desired program instructions through a scan chain; the SPU's interface to the external environment. Alterna- 45 gram 9 US 7,836,371 B2 tively, the instructions may be stored in an on-chip Read Only The benefits of the logic analyzer EFU are such that for Memory (ROM) that has been provided to work as the SPU's certain ICs, only the EFU portion of the SPU is implemented program memory. on the IC. In this alternate embodiment of the present inven- In one embodiment of the present invention, an EFU car- tion, the digital and analog probes are selectively enabled by 5 a scan-chain which allows specific control signals to be ries out certain functions of a logic analyzer. A logic analyzer loaded into these probe circuits. The scan chain also carries captures and stores signal state values in a digital system other control signals to be loaded into a trigger circuit which following the occurrence of a pre-defined event. The logic starts and stops the data capture operations. Once the desired analyzer then analyzes the captured data and displays the data has been captured into an on-chip RAM, the data is results for perusal. With the present invention, the capture and 10 transported outside the IC for subsequent analysis and dis- storage functions are incorporated into the IC. The EFU play. which implements these functions captures and stores not a single snapshot but a sequence (i.e., history of signal values Implementations of the Present Invention using logic probes which are selectively coupled to desired points in the IC logic circuits. The logic analyzer EFU is 15 As a starting point. FIG. 1a is a diagram of an exemplary configurable to select the location, number and sequential integrated circuit. The IC 100 is complex having a host pro- depth of signal channels from a predetermined set of choices. cessor connected by a system bus to various circuit blocks, Thus, each logic analyzer channel may be selectively coupled including a third party core and other blocks adapted to the to more than one predetermined capture point by program- application of the IC. The IC also has a peripheral bus which ming the control unit and hence, the EFU. A solution is 20 is connected to the system bus by a bridge. The peripheral bus provided for capturing the history of signal values at the is connected to other functional blocks, such as a user-devel- internal points of the IC without having to provide each one of oped core and so on. these points with their shadow register counterpart. The cap- A preferred embodiment of the present invention to test tured data are stored in an on-chip Random Access Memory and debug the complex IC of FIG. la is shown in FIG. 1b. (RAM). Transportation of the captured data out of the IC is 25. Added to the IC 100 is a Service Processor Unit (SPU) 101 performed later for analysis by an external computer which which is coupled to the IC system bus 105 and an added test can reformat and display as required for diagnostics. The bus 104. Connected to the test bus 104 are test wrappers 102 present invention has the benefit of enhanced data accuracy which provide test communication channels into selected with minimal cost overhead by separating the signal capture/ blocks 106. More details of the test bus 104 and test wrappers storage function of a logic analyzer into the IC. 30 102 are provided below. The SPU 101 provides a connection Two different types of logic probes may be used with the for an external diagnostics console 103 to view and test the logic analyzer EFU. One type of logic probe, termed the internal workings of the IC 100. digital probe, captures sequences of digital signals from inter As shown in FIG. 2, the SPU 101 has several extended nal points of the IC. Digital signal values flow from the function units (EFUS), including a control unit, such as a internal capture point to a logic analyzer channel through the 35 microprocessor 211, a buffer memory unit 218, an analysis digital probe. In its simplest form each digital probe has at engine 215, a scan control unit 222, an interrupt handler 221, least two input ports, a selection means and an output port that which is further connected to a range check unit 220, a system is directly coupled to a logic analyzer channel. Digital probes bus interface 214, a test bus interface 213 and a built-in self may also be constructed from a series of internal storage test (BIST) engine 212, which are all interconnected by a elements (i.e., flip-flops or latches) to form a pipeline to move 40 processor bus 219. The various EPUs are coupled to the the data from the capture points towards the logic analyzer processor bus 219 in any desired combination and order. To channels. In this case, the movement of the data along the provide communication between the external world and the digital probe flip-flops is synchronized with an on-chip clock SPU 101, the bus 219 is also connected to a serial input/output signal. Since the clock frequency also defines the maximum (SIO) interface 210, a parallel input/output interface (PIO) capture rate, the particular clock signal is selected based on 45 216, and a test access port (TAP) 217. For example, the the maximum desired capture rate. The digital probes used for coupling between the IC 100 and the external diagnostics the logic analyzer EFU operate with the same electrical and console 103, typically implemented using another computer, timing characteristics of the native signals of the IC. The uses the TAP 217, the SIO interface 210 or the PIO interface digital probes are implemented in the same technology, with 216. the same functional logic circuitry, and under the same clock 50 Analog probe lines 201 are connected to the range check timing, as the rest of the IC. Signals are therefor captured and unit 220 which processes their values to detect out-of-range propagated along the digital probes in exactly the same way conditions which are then signaled to the interrupt handler as they are operated upon by the functional circuitry of the IC. 221. The interrupt handler 221 also receives signals from This assures much greater accuracy of signal states captured trigger event lines 204 directly or from test bus 104 by way of by the digital probes. In contrast, logic probes used with an 55 test bus connections 203 to the interrupt handler 221. The external logic analyzer must use trigger events and signal signals on the trigger event lines 204 or test connections 203 values that are visible external to the IC. The captured signal are used to capture signal state values when predetermined values may differ significantly from the original (internal) (i.e., triggering) events occur. The interrupt handler 221 values. passes the captured values to the analysis engine 215. The test The logic analyzer EFU may use a second type of logic 60 bus 104 is further coupled to test wrap probe, termed an analog probe, which captures signal events individually wrapped around a number of predetermined representing the detection of signal integrity conditions, such blocks 106 on the IC 100. Each test wrapper 102 accesses the as ground bounce. Desired signal observation points are input and output signals of a block 106. The test bus 104 is coupled to analog detection circuits which produce digital also connected to scan string lines 403, which are connected signals when particular signal conditions are detected. The 65 to internal elem analog probe records these digital signal states in the logic As shown in FIG. 3a, the test bus 104 forms a unidirec- analyzer EFU. tional loop with test bus connectors 401 selectively transfer- 9 US 7,836,371 B2 8 sa ring data between the test bus 104 and a test wrapper 102. The the output of the scan flip-flop 301 (and is connected to one test bus 104 is made up of multiple bit lines, where the number input of the multiplexer 308). The control input of the multi- of the bits is determined by the requirements of the test plexer 308 is a test control line 300 from the control unit 311 plexer 30 system. Through test bus connector 401, the test bus 104 is of the SPU 101. The control signal on the line 300 selects selectively connected to test wrappers 102, scan string lines 5 whether the functional signal at data-in terminal 302 or the 403, probe string lines 402 and trigger lines 204. signal held in the scan flip-flop 301 is passed onto the data-out A test bus connector 401 which handles a one bit connec- terminal 307. When the control signal of the line 300 signal is tion between the test bus 104 and a test wrapper 102 is not-asserted, i.e., normal mode, there is normal operational illustrated in FIG. 3b. A first multiplexer 421 has one of its signal flow between the data-in terminal 302 and the data-out input terminals connected to one of the lines of the test bus 10 terminal 307. On the other hand, when the control signal on 104. The other input terminal is connected to a signal line of the line 300 is in asserted state, i.e., test mode, the current state the test wrapper 102. The output terminal of the multiplexer of the scan flip-flop 301 is passed onto the data-out terminal 421 is connected to an input terminal of a flip-flop 426 and to 307; the data-in terminal 302 and the data-out terminal 307 an input terminal of a second multiplexer 422, which has a second input terminal connected to the output terminal of the 15 are isolated from one another. The state stored in the scan flip-flop 426. The output terminal of the flip-flop 426 is also flip-flop 301 is also controls whether the signal at the data-in connected to the line of the test wrapper 102, which is also in terminal 302 or the probe-in terminal 303 is passed onto the the form of a unidirectional loop. The multiplexer 421 selects probe-out terminal 305. In this manner, data from another either the data from the test bus 104 or the test wrapper 102; probe point which is connected to the probe-in terminal 303 the second multiplexer 422 selects between the data selected 20 are selectively passed onto the probe-out terminal 305. The by the first multiplexer 431 or the data captured in the flip-flop signal state in the scan flip-flop 301 value is controlled and 426 to place back onto the test bus 104. These selections are observed using regular scan operations of the test wrapper done under the control of SPU 101. The test bus connector 102 through the scan-in and scan-out terminals 304 and 306. 401 is also be used for coupling a trigger line 204, probe string Of course, if observation of an input or output signal of the line 402 or scan string line 403 to a test bus 104 by connecting 25 block 106 by a probe string 402 is not required, the multi- the desired signal line in place of the line of the test wrapper plexer 309 can be eliminated from the circuit 310. 102 port as shown in FIG. 3b. A scan string 403 is formed by serially connecting block FIG. 3c shows an embodiment of coupling a trigger line scan connector circuits 320. One such circuit 320, which 204, probe string 402, test wrapper 102 and scan string line couples an internal element of a block 106 to the scan string 403 to three lines of the test bus 104. Other possible configu- 30 403, is illustrated in FIG. 4b. The connector circuit 320 has a rations for the couplings include coupling the test wrapper 102 and scan string 403 onto separate lines of the test bus 104. scan-in terminal 314 and a scan-out terminal 316. The scan-in A test wrapper 102 is formed by serially connecting block terminal 314 of one connector circuit is connected to the I/O connector circuits 310. One such circuit 310, which scan-out terminal 316 of another connector circuit 320 to couples an input or output signal of a block 106 to the test 35 form a serial scan string 403. The block scan connector circuit wrapper 102, is illustrated in FIG. 4a. The connector circuit 320 also has a data-in terminal 312 and a data-out terminal 310 has a scan-in terminal 304 and a scan-out terminal 306. 317 which provide an interstitial connection between internal The scan-in terminal 304 of one circuit 301 is connected to the elements of the block 106. In the normal operation of the IC scan-out terminal 306 of another circuit 301 to form the serial 100, the connector circuit 320 is a simple path between the chain of a test wrapper 102. The connector circuit 310 also has 40 internal elements in the block 106. The connector circuit 320 a data-in terminal 302 and a data-out terminal 307 which also has a probe-in terminal 313 and a probe-out terminal 315 provide an interstitial connection between a block 106 and the which provide a path for probe signals from selected portions rest of the IC 100. In the normal operation of the IC, the of the block 106 through the connector circuit 320 to observe connector circuit 310 provides a simple path between the operations in the block 106. block 106 and the rest of the IC 100. If the connector circuit 45 The block scan connector circuit 320 has a scan flip-flop 310 is to provide an input signal to the block 106 during test 311 and a multiplexer 319. The data-in terminal 312 and the operations, the data out terminal 307 is connected to the block scan-in terminal 314 form the inputs to the scan flip-flop 311. 106 and the data in terminal is connected to the rest of the IC The output from the flip-flip 311 include the scan out terminal 100. If the block I/O connector circuit 310 is to receive an 316 and the data-out terminal 317. The data-in terminal 302 is output signal from the block 106 during test operations, the 50 also connected to one input to the multiplexer 319. The probe- data-out terminal 307 is connected to the rest of the IC 100 in terminal 313 forms a second input to the multiplexer 319 and the data-in terminal is connected to the block 106. The whose output forms the probe-out terminal 315. A special connector circuit 310 also has a probe-in terminal 303 and a circuit is used for the scan flip-fi probe-out terminal 305 which provide a path for probe signals ofFIG. 4a). The circuit, which is shown in FIG. 5 and is found from selected portions of the block 106 through the connector 55 in previous IC scan designs, has separate scan-slave and circuit 310 to observe operations in the block 106. data-slave sections. The separation allows a state signal The elements of the connector circuit 310 include a scan which has been scanned into the scan flip-flop 311 to remain flip-flop 301 and two multiplexers 308 and 309. The data in unaffected by functional clock pulses that cause the flip-flop terminal 302 and the scan-in terminal 304 form the inputs to 311 to capture signals on the data in terminal 312 so that they the flip-flop 301. The output from the flip-flip 301 include the 60 appea scan out terminal 306 and one input to the multiplexer 308 317. The connector circuit 320 acts as a simple conduit for having an output which forms the data-out terminal 307. The signals within the block 106. At the same time, the previously second input to the multiplexer 308 is connected to the data-in scanned-in signal, which appears in the scan-slave section, terminal 302, which is also connected to one input to the selects whether signals at the data in terminal 312 or the multiplexer 309. The probe-in terminal 303 forms a second 65 output from another probe point which has been connected to input to the multiplexer 309 whose output forms the probe the probe-in terminal 313 is to be passed onto the probe-out out terminal 305. The control input of the multiplexer 309 is terminal 315. A probe string 402 is created. Of course, if an the UP 9 Sven US 7,836,371 B2 10 internal scan string 403 need not be connected to a probe which also initializes contents of the LSFR 714. The output of string 402, the multiplexer 319 can be eliminated from the the LSFR 717 is connected to the inputs of a multiplexer 715 circuit 320. which also receives the outputs of a mask shift register 712 A probe string 402 is formed by serially connecting the and a pattern shift register 713. The output of the multiplexer probe-in terminal of a connector circuit 310 and 320 to the 5 715 is an input to the LSFR 714. The mask shift register 712 probe-out terminal of another connector circuit 310 and 320. identifies the bit positions whose values are selected from The probe string 402 typically has a set of selectively con- predetermined bit patterns in mask shift register 713 versus nected probe points. However, only one probe point along the bit positions which receive the pseudo-random values each probe string 402 may be actively probed at any given generated by the LFSR 714. The output of the multiplexer 715 time. Thus the IC designer selects the probe points which are 10 is a combination of built-in-self-test and functional scan vec- to be connected along the same probe string 402 and deter- tors. These features are useful because random vectors work mines the total number of probe strings 402 that are to be well only when the controls allow the random vectors to connected to the individual bits of the test bus 104. This exercise most of the IC section under test. If there are more structure allows the IC designer great flexibility to optimize than a few control lines, the probability of properly exercising the number oftest bus 104 lines with respect to the number of 15 the logic under test with random vectors is very low. These simultaneously observable probe points in the IC. features also allow the SPU 101 to generate regularly repeat- The probes described above are digital probes. Two analog ing patterns; for example, periodic patterns that may be useful probes are illustrated in FIGS. 6a, 6b, 6c and 7. The range in a memory test may be generated by the SPU 101 that may check unit 220 receives inputs from the analog probes that output the data to the section of logic under test via the test bus comprise signals on a threshold check line 600 and a ground 20 or the system bus, whichever has been provided with a con- bounce line 700. The unit transmits these signals to the SPU nection to the SPU 101. how the circuit which generate the Another EFU of the SPU 101 is the analysis engine 215. signal for the threshold check line 600. The circuit is used for FIG. 9a shows an embodiment of the analysis engine 215 detecting extended intermediate voltage levels. Such voltage which, under the control of the microprocessor 211, captures levels are most likely to occur on an on-chip bus which is in 25 logic signals from the test bus 104. This is achieved by first contention among multiple circuit drivers. The analog probe setting either the scan flip-flops 301 of the block I/O connec- has two inverters 601 and 602, which are both coupled to an tor circuits 310 (FIG. 4a) or the scan flip-flops 311 of the Exclusive-NOR logic gate circuit. FIG. 6b is a transistor block scan connector circuit 320 (FIG. 4b) so that a boundary diagram depicting the low threshold inverter 601, and FIG. 6C connection or an internal point connection of the target block is a transistor diagram depicting the high threshold inverter 30 106 is selected for probing, respectively. Next, all flip-flops 602. These inverters 601 and 602 exhibit switching properties along the same probe string 402 are programmed (by the SPU characteristic of a very low internal voltage, and a very high 101) so that only signals from the selected probe point are internal voltage device, respectively. Normally, the circuit in allowed to flow through the probe string 402 and arrive at the FIG. 6a has a logic one (1) output level, but during transitions test bus connector 401. The multiplexer 421 and the multi- of the input signal, the outputs of inverters 601 and 602 may 35 plexer 422 in the test bus connector 401 (FIG. 3a) are con- remain in opposite states for a period sufficient to cause the trolled by the SPU 101 so that the signals on the probe string circuit to go to a logic zero (0) output level before returning to 402 are passed along to the test bus 104. Finally, all remaining the logic one (1) output level. This negative pulse can be test bus connector circuits 401 along the same bit line of the captured by the SPU 101. test bus 104 are controlled by the SPU 101 so that they pass FIG. 7 shows a schematic diagram of a ground bounce 40 the probe signals along test bus 104. This allows the selected detector circuit which generates the signals for a ground probe signal to arrive at the analysis engine 215 where bounce line 700. In this circuit, a quiet (and true) ground captured for subsequent off-line analysis. The input terminals terminal 701 is connected to an N-channel transistor 702, of a plurality of flip-flops 805, one for each bit line of the test which gate is driven by a local ground connection terminal bus 104, form the input port 802 of the analysis engine 215. A 703. A periodic clock on a Reset terminal 706, which is 45 digital phase locked loop (PLL) 802 has selectable clock controlled from the range check 220, clears a pair of NAND outputs 803 to each flip-flop 805 to tune when the data from gates configured as a SR latch 704, and charges a capacitor each probe point is to be captured. The output terminal of each 705 having one terminal connected to the Set input of the SR flip-flop 905 is connected to the input terminal of a variable latch. The second terminal of the capacitor 705 is connected First-In-First-Out shift register (FIFO) 804. to the quiet ground terminal 701. The N-channel transistor 50 FIG. 9b shows the circuit details of each variable First-In- 702 which is gated by the local ground discharges the Set line First-Out shift register (FIFO) 804, each having a number of of the SR latch 704, which flips the state of the SR latch 704 serially-connected register stages 812. Each register stage if the local ground falls above threshold. For example, a 812 has a multiplexer which, under control of a decoder 811, ground spike on the local ground may drive the local ground selects between the signal held in a flip-flop of that stage or below threshold. The frequency and duty cycle of the Reset 55 the incoming signal to the stage to place on the stage's output signal determines the magnitude and duration of a ground terminal. The shift depth of each variable FIFO 804 is pro- spike on the local ground to trigger the probe. A variety of grammable by the SPU 101 by setting a count register 810 for frequencies and duty cycles are created by the range check each bit feeding the analysis engine 215. The value in the 220 to determine the severity of ground spikes. When the count register 810 is decoded by the decoder 811. The result probe is triggered, the probe produces a negative (0) value 60 controls the number of register stages 812 which are until reset by the Reset signal on the terminal 706. bypassed. This compensates for the path delay differences Returning to the components of the SPU 101, FIG. 8 is a among the different probe points by realigning capture times preferred embodiment of the BIST engine 212. A polynomial of signals captured in the analysis engine 215. register 711 identifies the bits in a linear feedback shift reg- The analysis engine 215 also has trigger logic which con- ister (LSFR) 714 which are used to form an Exclusive-OR 65 trols the capture of data. FIGS. 9c and 9d show sections of the (XOR) function which generates pseudo-random values. The trigger logic, a programmable circuit which detects one or polynomial register 711 is set by the microprocessor 211, more events to stop the analysis engine 215 from capturing 9 US 7,836,371 B2 11 new data. The data that has been captured up to that point is conditions. The buffer memory 218 is utilized more effi- preserved in the buffer memory 218 of the SPU 101. The ciently as the storage of unwanted cycles of data between the buffer memory 218 resides in the same address space as the trigger points is not required. It is also possible to program the RAM used by the SPU 101 but may be mapped to use high trigger logic so it uses an externally generated trigger condi- memory space in order to prevent interference with the 5 tion 902 in place of an internally programmed event. instructions and data stored in low memory space. When the Program instructions and initial data values for executing analysis-engine 215 collects data, it may be allowed to write programs to implement the functions of the SPU 101 are over old data, keeping only as many most-recent cycles of data as the buffer memory 218 can hold. The size of the buffer loaded from the diagnostics console 103 (see FIG. 1b) into the buffer memory 218 of the SPU 101. Some of these programs memory 218 for the analysis engine 215 is determined by the 10 designer of the IC. may access the system bus 105 or the test bus 104. A program The trigger logic has a start address counter 820 and a stop can control which test wrapper 102 is accessed by using the counter 821, which are shown in FIG.9c. These counters are test bus interface 213 in order to set control signals on the test loaded by the microprocessor 211. The trigger circuit also has bus 104. This allows the SPU 101 to read data from a test an address counter 822 which is designed to overflow at the 15 wrapper 102 via the test bus 104 into the buffer memory 218 highest memory address of the buffer memory 218. At that and then send said data out to the diagnostic console 103. point the start address is reloaded with the beginning address Typically, a separate program executed on the diagnostic of the high memory space which is reserved for the buffer console 103 displays this information in a human readable 218. This converts a random access memory into a FIFO format as may be appropriate for the given application. register. The stop counter 821 decrements when a latched 20 Programs executed by the SPU 101 can also read data from trigger signal line 824 becomes set. Subsequently the analysis the diagnostics console 103 via the SIO interface 210 or TAP engine 215 collects data into the buffer memory 218 from the interface 217, as shown in FIG. 2b, and write data out to variable FIFOs 804 for as many cycles as defined by the value individual scan flip-flops on the test wrappers 102 via the test loaded into the stop counter 821. The system IC designer uses bus 104. Significant processing, for example, expansion, the buffer memory size and the value in the stop counter 821 25 compaction, or intermediate storage of data can be done by as two parameters to control the amount of data collected the SPU 101 utilizing the buffer memory 218. In other before and after an event has been detected. embodiments, control functions may be supplied directly Also part of the trigger logic is a circuit which generates the from the TAP interface 217 or SIO interface 210 to the analy- triggering signals on the trigger signal line 824. As shown in sis engine 215 or BIST engine 212, via the processor bus 219 FIG. 9d, the generating circuit is structured to form Boolean 30 without involving the microprocessor 211. The SPU 101 may AND-OR logic 831 out of individually selectable terms 832. be coupled to either the system bus 205, or a separate test bus The terms 832 are fed from a polarity programming logic 104, or both. The coupling to the diagnostics console 103 may circuit 833 that accepts individual trigger variables, Probe 1 be via the TAP interface 217 or the SIO interface 210. The test through Probe N. In addition, the true or the complemented bus 104 may be coupled to one or more test wrappers 102. value for the output function can be selected through a final 35 Another embodiment of the invention is defined in which level circuit 830. In one embodiment (shown in FIG.9d), the the SPU 101 does not include an embedded microprocessor result is also shifted into three successive flip-flops 834. Each 211. In this case, the analysis engine 215 and the BIST engine of the flip-flops 834 drives one input of each of a plurality of 212 can access the buffer memory 218 and system bus inter- multiplexers 835. The other inputs of the multiplexers 835 are face 214 directly, following instructions received from the set to a logic one (1) level. Each multiplexer 835 is individu- 40 external diagnostics console 103. In this case, the loading of ally controlled through programmable bits and the multi the configuration information and transfer of data to and from plexer outputs are logically ANDed together to form a signal, the analysis engine 215 is controlled using hardwired control T[i], which represents the presence of the trigger condition signals. In this embodiment, the analysis engine 215 is imple- over four consecutive clock periods. The output from the mented in the form of an on-chip logic analyzer (OLA) which AND gate 836 is passed to an AND gate 837 with inputs from 45 captures sequential snapshots of sets of signals. The selected the corresponding AND gates 836 of duplicate circuits that signals form the digital probes 202. The selections are produce T[O], T[1], through T[n] signals. The output of AND achieved by coupling the signals for digital probes 202 to the gate 837 is stored in a latch 838 to form the latched trigger channels of the analysis engine 215 and turning-on enabling signal on the line 824. Once the signal is set, the latched circuits, if provided, to allow the signals on the digital probes trigger signal maintains its value until it is reset through 50 202 value to be captured onto channels of the logic analyzer reprogramming by the microprocessor 211. In other embodi- 215. As shown in FIG. 11, the channels of the logic analyzer ments, there may be more or fewer latches, and additional 215 are formed from probe storage elements (PSE) 1000 to logic to make adjustments to the phases (i.e., the relative form a distributed serial shift register which acts as a pipeline clock cycle when signal is received) of the individual signals. to move data captured at a probe point towards the end of the Another embodiment of the trigger logic is shown in FIG. 55 logic analyzer channel where the data 10. This embodiment provides for the capability of reversing memory 218. Each channel of the analysis engine 215 con- the data capturing function of the analysis engine 215 from tains zero or more number of PSEs 1000 which are clocked by continually capturing new data until the trigger is detected, to a common periodic clock signal labeled "Cf" on a clock not capturing any data until a trigger is received. In the latter signal line 1001. The clock signal is chosen (at design time) case, each time a trigger signal on the line 824 is received, the 60 from among the fastest frequency of clock signals analysis engine 215 captures new data for a preprogrammed used in generating source signals to be captured by the number of cycles and then stops until the next latched signal probes. This way all signals captured on the analysis engine on the line 824 is received. To enable this mode of operation, 215 channels arrive at the end of the channels after a fixed, the trigger circuit shown in FIG. 10 causes the previous trig- predetermined number of clock cycles so that their cycle ger condition to be cleared so that it may be recognized again. 65 relationship to one another is preserved, regardless of the This mode is very useful since it enables the capture of signals length (i.e., number of bits) of the individual channels of around (i.e., before and after) multiple occurrences of trigger analysis engine 215. пе 9 13 do a US 7,836,371 B2 14 Subsequently, after the captured data has been transported plexer 1109 to the latch 1106 by a clock signal 1110. The latch to the external diagnostics console 103, software processes 1106 captures the signals from the latch 1105 and the multi- use the number of PSEs 1000 on each channel of the analysis plexer 1108 at the Cf clock rate and passes the signals out to engine 215 to align the data with respect to one another. The the output terminal. The multiplexed-PSEs shown in FIGS. lengths (i.e. number of bits) of the serial shift registers on the 5 12 and 13 build cost efficient logic analyzer channels. individual channels of the analysis engine 215 are determined Once enabled, the analysis engine 215 captures new values at design time so that signal delays due to physical distances first into the flip-flops along the OLA channels and subse- among the PSEs 1000 are sufficiently short to allow data to be quently into the buffer memory 218 using trigger signals that shifted between consecutive bits of the shift registers in a have been pre-programmed and implemented as shown in single clock cycle. If necessary, the number of stages of the 10 FIGS. 9c, 9d and 10. shift registers may be increased to satisfy this condition. Each In one mode of operation of the IC 100 shown in FIG. 1b. channel of the analysis engine 215 is coupled to a different the human engineer may use the diagnostics console 103 to data input port of the buffer memory 218. The collective data initialize both of the system logic and the SPU 101. In this applied to the ports of the buffer memory 218 is written to an manner, the SPU 101 may be programmed to perform logic address in memory which is identified by a common address 15 analyzer functions and specific probe points may be enab register 822 that advances under control of the periodic clock so that a history of data values appearing at the selected probe signal "C" on the line 1001. points can be captured by SPU 101. Additionally, the trigger FIG. 12 shows a preferred embodiment of a channel of the logic shown in FIGS. 9 and 10 may be programmed to select OLA 215 which uses multiplexed PSES 1000 to combine the a desired trigger event in order to stop the data capture opera- selection of probe points and pipelining captured data into a 20 tions. Next, the diagnostics console 103 invoke the IC 10 single, efficient design. This enables the coupling one PSE execute its normal system operations. If and when the 1000 to two probe points or another PSE 1000. Scan opera- selected trigger event is detected and the analysis engine 215 tions shift a control signal into the PSE 1000 to program itself has captured the required data, the diagnostics console 103 to select one or the other of its input ports. instructs the SPU 101 to transfer the captured data values out The details of a multiplexed PSE are shown in FIG. 13. The 25 of the IC 100 and into the diagnostics console 103 where the PSE 1000, illustrated by a dotted line, is connected to a data may be formatted and presented for analysis and inter- multiplexer 1108 which has two input terminals connected to pretation. The diagnostics console 103 and the SPU 101 can two input probe paths, P1 and P2, for the logic analyzer constrain some of the signals on one or more test wrappers channels. Besides the probe clock signal line 1001, which 102 in order to affect the behavior of the IC 100 and perform carries the Cf signal, the PSE 1000 is connected to a first scan 30 logic analysis under these conditions. For example, this clock signal line 1101, which carries an A_clk signal, a sec- approach may be useful to determine how the overall behav- ond scan clock signal line 1102, which carries a B_clk signal, ior of the IC 100 is affected when some of the functionality of and a scan control line 1103, which carries a Scan_mode any one of the blocks 106 is disabled. signal. The PSE 1000 has three latches 1105, 1106 and 1107. In a different mode of operation automatic test equipment The output terminal of the latch 1105 is connected to one 35 (ATE) may access the IC 100 through its TAP interface 217 in input terminal of the latch 1106 and to one input terminal of order to initialize the SPU 101 so that internal scan strings 403 the latch 1107. One input terminal of the latch 1105 is con- and test wrappers 102 are loaded with predetermined test nected to the output terminal of the multiplexer 1108 and a values. The response of the blocks 106 is observed using the second input terminal of the latch 1105 forms a scan data scan strings 403 and test wrappers 102. Furthermore, the ATE input terminal 1104, SI. The output terminal of the latch 1107 40 may be programmed to instruct the SPU 101 to execute BIST forms a scan data output terminal, SO, and is also connected or other buffer memory 218 test functions and to check the to the control terminal of the multiplexer 1108. The output results to determine pass or fail conditions. terminal of the latch 1106 forms an output probe path, Q, for In yet another mode of operation, it is possible to use an the logic analyzer channels. in-circuit test (ICT) or similar board-level test equipment to The scan clock signals, A_clk and B_clk respectively, and 45 access the IC 100 through its TAP interface 217 in order to the Scan_mode signal configure the PSE 1000. For serial shift instruct the SPU 101 to turn-on its external memory test operations, the serial input (SI) on the line 1104 is captured function. In this mode, patterns are generated by the SPU 101 into the latch 1105 when the A_clk signal is applied and the and made to appear at specific I/O pins of the IC 100 which are output of the latch 1105 is captured into the latch 1106 when coupled to external memory. For example, the IC 100 may the B_clk signal is applied. If the Scan_mode signal on the 50 generate the data and address values that are applied to the line 1103 is set to a logic 1, the B clk signal on the line 1102 external memory. The data responses received are captured in is also passed through a multiplexer 1109 and an AND gate order to determine if the external memory is functioning 1112 to the latch 1107 by a clock signal line 1111. Thus, correctly. non-overlapping A_clk and B_clk signals on the clock signal While the description above provides a full and complete lines 1101 and 1102 respectively clock serial shift operations 55 disclosure of the preferred embodiments of the present inven- in the PSE 1000. Signals scanned into the latch 1105 through tion, various modifications, alternate constructions, and line 1104 are also scanned into the latch 1107 (and the latch equivalents will be obvious to those with skill in the art. Thus, 1106) and the SO output terminal. This completes the pro- the scope of the present invention is limited solely by the gramming of the PSE 1000 such that value that has been metes and bounds of the appended claims. loaded into the latch 1107 controls input multiplexer 1108 60 which selects between two input ports 1109 and 1110. Once the PSE 1000 has been programmed, the Scan_mode signal What is claimed is: on control line 1103 signal is set to and maintained at logic 0 until the PSE 1000 is programmed with a new value. When 1. An integrated circuit comprising: the Scan_mode signal is set to logic 0, the PSE 1000 performs 65 one or more logic blocks to generate one or more system- its normal data capture function using the clock signal Cfon operation signals at one or more system-operation clock the line 1001. The Cf clock signals are passed by the multi- rates; and 9 US 7,836,371 B2 15 16 a service processor unit, said service processor unit com 7. An integrated circuit comprising: prising: one or more logic blocks to generate one or more system- a control unit; operation signals at one or more system-operation clock a buffer memory; and rates; 5 a system bus; and a multiplicity of selectable probes, a service processor unit, said service processor unit com- wherein said service processor unit is adapted to perform prising: capture and analysis of said system operation signals a control unit; during normal system operation through said selectable a buffer memory; and probes. 10 a system bus interface, 2. The integrated circuit according to claim 1, further com wherein said service processor unit is adapted to perform prising at least one port selected from the group consisting of: capture and analysis of system operation signals on said a parallel 1/0 (PIO) port, system bus during normal system operation through said a serial I/O (SIO) port, and system bus interface. 15 8. The integrated circuit according to claim 7, further com- a JTAG port; prising at least one port selected from the group consisting of: wherein data and instructions are to be sent through at least a parallel I/O (PIO) port, one of said ports to said service processor unit from an a serial I/O (SIO) port, and external diagnostics console, and wherein result data is a JTAG port; to be sent through at least one of said ports from said 20 wherein data and instructions are to be sent through at least service processor unit to said external diagnostics con- one of said ports to said service processor unit from an sole. external diagnostics console, and wherein result data is 3. The integrated circuit according to claim 1, wherein said to be sent through at least one of said ports from said selectable probes are selectable digital probes. service processor unit to said external diagnostics con- 4. The integrated circuit according to claim 1, wherein said 25 sole. selectable probes are selectable analog probes. 9. The integrated circuit according to claim 7, wherein said 5. The integrated circuit according to claim 1. wherein said service processor unit is adapted to perform debug operations service processor unit is adapted to perform debug operations of said integrated circuit. of said integrated circuit. 10. The integrated circuit according to claim 7, wherein 30 said service processor unit is adapted to monitor said inte- 6. The integrated circuit according to claim 1, wherein said grated circuit. service processor unit is adapted to monitor said integrated circuit. 9 (12) INTER PARTES REVIEW CERTIFICATE (1016th) United States Patent (10) Number: US 7,836,371 K1 Dervisoglu et al. (45) Certificate Issued: Jun. 28, 2018 (54) ON-CHIP SERVICE PROCESSOR (75) Inventors: Bulent Dervisoglu; Laurence H. Cooke; Vacit Arat (73) ee: INTELLECTUAL VENTURES I LLC Trial Number: IPR2014-00310 filed Dec. 30, 2013 Inter Partes Review Certificate for: Patent No.: 7,836,371 Issued: Nov. 16, 2010 Appl. No.: 11/424,610 Filed: Jun. 16, 2006 The results of IPR2014-00310 are reflected in this inter partes review certificate under 35 U.S.C. 318(b). 9 INTER PARTES REVIEW CERTIFICATE U.S. Patent 7,836,371 K1 Trial No. IPR2014-00310 Certificate Issued Jun. 28, 2018 AS A RESULT OF THE INTER PARTES REVIEW PROCEEDING, IT HAS BEEN DETERMINED THAT: Claims 2 and 7-10 are found patentable. Claims 1 and 3-6 are cancelled. 9 US 7,836,371 B2 Page 2 U.S. PATENT DOCUMENTS 5,155,432 A 5,202,624 A 5,202,625 A 5,206,862 A 5,254,482 A 5,329,471 A 5,369,648 A 5,418,470 A 5,423,050 A 5,428,629 A 5,479,652 A 5,495,486 A 5,590,354 A 5,617,531 A * 5,630,048 A 5,642,478 A 5,724,505 A 5,737,520 A * 5,761,489 A 5,771,240 A 5,805,792 A 5,838,163 A 5,850,512 A 5,854,996 A 5,905,738 A 5,936,876 A 5,941,995 A * 5,944,841 A 5,991,898 A 6,003,107 A 714/30 6,003,142 A 12/1999 Mori 6,035,262 A 3/2000 Gibson et al. 6,094,729 A 7/2000 Mann 6,107,821 A 8/2000 Kelem et al. 6,125,464 A 9/2000 Jin 6,131,171 A 10/2000 Whetsel 6,167,536 A 12/2000 Mann 6,182,247 B1 1/2001 Herrmann et al. 6,189,140 B1 2/2001 Madduri 6,247,147 B16/2001 Beenstra et al. 6,321,320 B1 11/2001 Fleischman et al. 6,374,370 B14/2002 Bockhaus et al. 6,460,148 B210/2002 Veenstra et al. 6,499,123 B112/2002 McFarland et al. 6,522,985 B1 2/2003 Swoboda et al. 6,564,347 B1 5/2003 Mates 6,687,865 B1 2/2004 Dervisoglu et al. 6,704,889 B2 3/2004 Veenstra et al. 6,782,498 B2 8/2004 Tanizaki et al. 6,964,001 B2 11/2005 Dervisoglu et al. 2006/0064615 A1 3/2006 Dervisoglu et al. 10/1992 Mahoney 4/1993 Gheewala et al. 4/1993 Farwell 4/1993 Chandra et al. 10/1993 Fisch 7/1994 Swoboda et al. 11/1994 Nelson 5/1995 Dagostino et al. 6/1995 Taylor et al. 6/1995 Gutman et al. 12/1995 Dreyer et al. 2/1996 Gheewala 12/1996 Klapproth et al. 4/1997 Crouch et al. 5/1997 La Joie et al. 6/1997 Chen et al. 3/1998 Argade et al. 4/1998 Gronlund et al. 6/1998 Broseghini et al. 6/1998 Tobin et al. 9/1998 Swoboda et al. 11/1998 Rostoker et al. 12/1998 Song 12/1998 Overhage et al. 5/1999 Whetsel 8/1999 Sugasawara 8/1999 Morrison 8/1999 Christie 11/1999 Rajski et al. 12/1999 Ranson et al. 714/39 OTHER PUBLICATIONS "Design of Self-Diagnostic Boards by Multiple Signature Analysis"; IEEE Transactions on Computers, vol. 42, No. 9, Sep. 1993, pp. 1035-1044. "Using Scan Technology for Debug and Diagnostics in a Workstation Environment"; Proceedings of the International Test Conference, 1988, Sep. 1988, pp. 976-986. 714/39 * cited by examiner 9 U.S. Patent Nov. 16, 2010 Sheet 1 of 16 US 7,836,371 B2 105 System Bus ...Peripheral.Bus. 100 WITUIT User-Developed Core System IC Figure la (prior art) 3rd-Party Core' Bus Interface Black Bridge Host Processor 9 U.S. Patent Nov. 16, 2010 Sheet 2 of 16 US 7,836,371 B2 104 100 103 - - 105 System Bus 101 TUDI Peripheral Bus - 106 User-Developed Core TITUTUMUTITTI Figure 1b 100 Bridge System IC 3rd-Party Core Bus Interface Black 102 sy 102 Host Processor SPU 101 - U.S. Patent - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 215 211 210 - 212 222 Sdan Control SIO micro- Analysis Engine BIST engine processor 5217 Parallel I/O TAP Test 216 Range Check Interrupt Handler Test Bus Interface Buffer Memory Nov. 16, 2010 Bus Interface 220 - 213 218 221 203 204' Trigger 201 Analog Probes Test Bus 9 Sheet 3 of 16 704 System Bus 405 Scan string403 202 Digital Probes Core Block 106 Test Wrapper -102 US 7,836,371 B2 Figure 2 9 U.S. Patent Nov. 16, 2010 Sheet 4 of 16 US 7,836,371 B2 101 -213 SPU Test bus Interface probe string 402 - 401 403 Scan string Core block 106 401 102 Test wrapper Figure 3a 401 Test bus connector Trigger \401 204 Test bus 104 9 U.S. Patent Nov. 16, 2010 Sheet 5 of 16 US 7,836,371 B2 Test bus 104 425 Test wrapper 102 404 SPU 101 1 - 426 Figure 3b 104 SPU 101 Test bus Preferred Embodiment of Test Bus Connector a SPU 101 Test wrapper 102 Test bus 1047 Test bus 104 421 Probe String 402 U.S. Patent,-4011.. = = = = = = = = = - - - - - - - - - - - - - - - - - - Trigger 204 - Test Bus 104 - - - - - - - - - - - - Test Bus 104 - Nov. 16, 2010 4011 Test wrapper 102 401 Core block Sheet 6 of 16 9 106 Scan string 403,-.401. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Figure 3c Connecting Probe String, Test Wrapper or Scan String to Test Bus US 7,836,371 B2 Test wrapper 102 U.S. Patent 309 305 - 306c probelout Yscan Tout 310 " Nov. 16, 2010 Scan |FF 300 Data in 302 Data in 9 .- brobe.. ---scan. If 303_Zinzo, Lin 304 Q Data out 307 9 Sheet 7 of 16 - 308 Figure 4a US 7,836,371 B2 Preferred Embodiment of Block Input/Output Port Connector