American Patents LLC v. Mediatek, Inc. et al

Western District of Texas, txwd-6:2018-cv-00339

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9 EXHIBIT 3 Case 6:18-CV-00339-ADA Document US008239716B2 (12) United States Patent Dervisoglu et al. (10) Patent No.: (45) Date of Patent: US 8,239,716 B2 *Aug. 7, 2012 (54) ON-CHIP SERVICE PROCESSOR (56) References Cited (75) Inventors: Bulent I. Dervisoglu, Mountain View, CA (US); Laurence H. Cooke, Los Gatos, CA (US); Vacit Arat, Los Altos Hills, CA (US) (73) Assignee: Intellectual Ventures I LLC, Wilmington, DE (US) U.S. PATENT DOCUMENTS 3,761,695 A 9/1973 Eichelberger 3,783,254 A 1/1974 Eichelberger 3,784,907 A 1/1974 Eichelberger 4,357,703 A 11/1982 Van Brunt 4,495,629 A 1/1985 Zasio et al. 4,667,339 A 5/1987 Tubbs et al. 4,749,947 A * 6/1988 Gheewala 714/734 4,817,093 A 3/1989 Jacobs et al. 5,065,090 A * 11/1991 Gheewala ....................... 714/32 (Continued) (*) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days. This patent is subject to a terminal dis- claimer. OTHER PUBLICATIONS (21) Appl. No.: 12/717,391 "BIST TPG for Faults in System Backplanes"; Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997, pp. 406-413. (Continued) (22) Filed: Mar. 4, 2010 (65) Prior Publication Data US 2010/0162046 A1 Jun. 24, 2010 Primary Examiner — David Ton (74) Attorney, Agent, or Firm — Novak Druce + Quigg LLP (57) ABSTRACT Related U.S. Application Data Continuation of application No. 11/424,610, filed on Jun. 16, 2006, which is a continuation of application No. 11/261,762, filed on Oct. 31, 2005, now Pat. No. 7,080,301, which is a continuation of application No. 10/767,265, filed on Jan. 30, 2004, now Pat. No. 6,964,001, which is a continuation of application No. 09/275,726, filed on Mar. 24, 1999, now Pat. No. 6,687,865. Provisional application No. 60/079,316, filed on Mar. 25, 1998. An integrated circuit is described that includes a stored pro- gram processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable cir- cuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits. (60) (51) Int. Cl. GOIR 31/28 (2006.01) (52) U.S. CI. ............ 714/726; 714/727; 714/729 (58) Field of Classification Search .................... 714/30, 714/39, 733, 726, 727, 729, 734, 32; 703/28 See application file for complete search history. 3 Claims, 16 Drawing Sheets Probe String 402 4012 Trigger 204 4012. Test Bus 104 Test Bus 104 401 Test wrapper 102 -401 401 Core block 106 Scan string 403 Connecting Probe String, Test Wrapper or Scan String to Test Bus Test wrapper 102 U.S. Patent - 306d scan 309 305 - probelout--- Tout 310; ScanN i 300 Data in FF * Data out 3027 probe ------scan. -307 303_jn 2017 bin 304 - 308 Aug. 7, 2012 Sheet 7 of 16 9 Figure 4a US 8,239,716 B2 D SA AN Preferred Embodiment of Block Input/Output Port Connector 9 U.S. Patent Aug. 7, 2012 Sheet 8 of 16 US 8,239,716 B2 311 Scan chain 403 Scania 311 Data out 317 314 scap out_316 ScanFF, scan in 320 315 _ probe out Data in DT 320L probe in 312 313 Preferred Embodiment of Block Scan Connector I Figure 4b 9 U.S. Patent Aug. 7, 2012 Sheet 9 of 16 US 8,239,716 B2 I Scan out Data out Scan Slave Data Slave Figure 5 Internal Scan Element with Separate Scan-Slave and Data-Slave: (prior art) Master Scan-- Data Scan Cik B Scan Clk A Scan in Data in System Clk 9 U.S. Patent Aug. 7, 2012 Sheet 10 of 16 US 8,239,716 B2 Threshold check 600 – A+6 Figure 6a 601 A+6 602 Figure 6b ollaHH 튼 Figure 6c -JH N 603 602 601 9 U.S. Patent Aug. 7, 2012 Sheet 11 of 16 US 8,239,716 B2,700 Ground bounce 701 AS Quiet Ground P debito -705 set -702 Figure 7 704 MAINBOW Reset 706 703 Local Ground 9 U.S. Patent Aug. 7, 2012 Sheet 12 of 16 US 8,239,716 B2 Mixed BIST/ Functional Scan Vectors 715 714 Web 111 712 - 713 GAWAI Mask Shift Register Pattern Shift Register (HHHHHHO BUS Polynomial Register Figures S EIS అదనంతరం రాశానురావాదనను m U.S. Patent Variable FIFO. Variable FIFO Scan & Probe Inputs 8014 804 Seria T_ I D SE. Variable FIFO_ Variable FIEO. Variable FIFO. 804 ADRES Aug. 7, 2012 BROODSOUDILO 802 Digital PLL BBS 814 803 WRON Figure 9a 812 9 Sheet 13 of 16 ..Variable FIFO Decode SEASEROS Count Register RASPORERA ERE ERANOS 810 804 Figure 9b US 8,239,716 B2 U.S. Patent G em SENS 822 Buffer Memory Data input Address. 218) From > Address Counter Variable 814 Load FIFO 804 Stop Counter _Start Address - 821 Figure 9c Latched Trigger 824 Aug. 7, 2012 BER 820 835 831 * r 831 834 - 9 Probe 1 Probe 129 Probe NTD LOD Sheet 14 of 16. 830 1 836 833 835 837 T[0] Trigger T(n-11 838 824 T[n] Figure 9d US 8,239,716 B2 2013 Buffer Memory 218 U.S. Patent Data input clk Address From Probes 822 Address Counter Load 824 Latched trigger 902 Clock wel Stop Counter 820 so Start Address Aug. 7, 2012 ext Stop Count Figure 10 814 Sheet 15 of 16 1000 9 Functional SRL PSE -2185 1001 CEL Buffers Gray Inserted SRL Memony prices on TER BMW Combinational Logic LA Buffer Memory CF 1001 Direct-Probe Pipeline US 8,239,716 B2 Figure 11 Direct-Probe Channels > >n-bits U.S. Patent Buffer Memory ... Pi L ** 418 Mux'ed-Probe Channel 1001 LA Buffer Memory Aug. 7, 2012 Figure 12 B ROS. ARSIMICURAR 1109 P10 P20 9 1107 Sheet 16 of 16 1105 1110 1108 SO 1111 Cf 1141, D A_clk --1101 1104 - A_clk 1102 B_clk - 1109 9 LDP_clk -1111 1106 Scan_Mode 1103 -1112 1000 Figure 13 US 8,239,716 B2 9 US 8,239,716 B2 1 ON-CHIP SERVICE PROCESSOR For example, one standard technique is "scan" whereby, cer- tain internal flip-flops, which are connected to various CROSS-REFERENCE TO RELATED selected points of the IC, are also connected to form a serial APPLICATIONS shift register when the IC is configured in a test mode. 5 Straightforward serial shift (i.e., scan) operations are utilized This application is a continuation of co-pending U.S. to load the flip-flops with desired values, or to read out their patent application Ser. No. 11/424,610, filed Jun. 16, 2006, present values reflective of the logic states of the selective IC which is a continuation of U.S. patent application Ser. No. points. Such ICs require special features to reset the flip-flops 11/261,762, filed Oct. 31, 2005 (which issued as U.S. Pat. No. (i.e., bring the IC to a known starting state). However, the size 7,080,301), commonly-assigned, and incorporated by refer- 10 of integrated circuits has grown to the point where it has ence in its entirety. That application is a continuation of U.S. become inefficient and expensive to test and debug ICs using patent application Ser. No. 10/767,265, entitled, "On-Chip solely conventional scan techniques. Service Processor," filed on Jan. 30, 2004 (which issued as Furthermore, variations of the serial scan technique U.S. Pat. No. 6,964,001), commonly-assigned, and incorpo- include the use of so-called "shadow registers." IC internal rated by reference herein in its entirety. That application is a 15 signal states are captured in a duplicate copy, i.e., the shadow continuation of U.S. patent application Ser. No. 09/275,726, register, of certain internal registers. The shadow registers are entitled, "On-Chip Service Processor," filed on Mar. 24, 1999 interconnected by a dedicated internal scan chain. A prede- (which issued as U.S. Pat. No. 6,687,865), commonly-as- termined event can trigger a snapshot of the internal state signed, and also incorporated by reference herein in its values in the shadow registers and the dedicated scan chain entirety. That application, in turn, is entitled to the priority of 20 shifts the captured signal state without affecting the system U.S. Provisional Patent Application No. 60/079,316, filed on operation of the IC. However, this approach has several defi- Mar. 25, 1998. ciencies. First, only a single snapshot can be captured and shifted out with each trigger event. This greatly hampers BACKGROUND OF THE INVENTION debugging the IC since there is not much visibility of the 25 system activity around a point of interest identified by the The present invention is related to the testing and debug trigger event. Secondly, the snapshots can be taken only of ging of electronic systems, and, in particular, to on-chip cir- those signals in registers which have a shadow register coun- cuits for the test and diagnosis of problems in an integrated terpart. Since a shadow register effectively doubles the cir- circuit. cuitry for the register, this approach is very costly to imple- Heretofore, logic analyzer probes have often been used in 30 ment on a large scale in the IC. the testing and debugging of electronic systems. The logic Another test and debug design for ICs is found in a stan- analyzer probes were coupled to the external pins of compo dard, the IEEE 1149.1 Test Access Port and Boundary-Scan nents of a digital system in order to capture the sequence of Architecture, which prescribes a test controller which signals after a predefined event (or time stamp) occurs. The responds to a set of predetermined instructions and an instruc- captured signals can then be examined to verify correct sys- 35 tion register which holds the present instruction which the tem behavior or, alternatively, to identify the time and the controller executes. Each instruction is first loaded into the nature of erroneous behavior in the system. instruction register from a source outside the IC and then that Furthermore, in the designs of large electronic systems, instruction is executed by the controller. While having some separate consoles, or service processors, have often been advantages of versatility and speed, the standard still binds incorporated into the circuit boards of the system. These 40 test and debug procedures to the world external to the IC and separate processors have a number of useful functions, thus, limits its performance. including the control of scan strings in the system; the origi- The present invention recognizes that while the advances in nation of diagnostic signal probes to run on the system, and so IC technology have helped to create the problems of testing forth. The service processors also have diagnostic and scan and debugging an IC, the advances also point the way toward debug features, including access to the internal registers and 45 solving these problems. In accordance with the present inven- memory within the system. The service processors have also tion, special on-chip circuits are used to observe the internal been used to bring-up the main system during its power up workings of an IC. These circuits operate at internal IC clock phase. All of these functions have been useful to system rates so that the limitations of the frequency of signals at the designers for the design, test and debugging of electronic IC input and output (1/0) boundary are avoided. Many more systems. 50 points in the IC system are accessed than is feasible with On the other hand, more and more digital systems, or parts conventional external test and debug processors. Thus the of digital systems, are being integrated in a single component. present invention offers advantages which exceed the The resulting complexity and lack of observability of an straight-forward savings in chip space due to miniaturization. integrated circuit poses serious problems for the test, debug Additionally, the present invention reduces the amount of test and bring-up stages of the integrated circuit (IC). For 55 logic which might have been required elsewhere on the chip. example, observation at the IC component pins of the behav- The present invention also permits the coupling of probes ior of an IC system is increasingly difficult. The IC compo to internal IC points. The points may be selected from a larger nent pins may be very far (in terms of logic hierarchy) from number of internal points that may be observed with an exter- the actual points of interest. The extremely high frequency of nal logic analyzer. Besides the greater observability of the digital IC operations and the frequency filtering effects of the 60 internal operations of the IC, the present invention also large capacitance of the external logic analyzer probes, often improves the accuracy of the observations, as compared to an prevents a logic analyzer from capturing signals reliably and external logic analyzer. precisely. There is always an uncertainty regarding the accu- racy of signals captured by an external logic analyzer com- SUMMARY OF THE INVENTION pared to the actual signals values within the IC. 65 To address the problems of the testing of integrated cir- To achieve these ends, the present invention provides for an cuits, special features are being included in many IC designs. integrated circuit logic blocks, a control unit, a memory asso- 9 US 8,239,716 B2 30 Hans. ciated with the control unit and a plurality of scan lines. The tecture); FIG. 4b is a circuit diagram of a block scan connector memory holds instructions for the control unit to perform test for scan strings for observing test points inside a block along and debug operations of the logic blocks. The scan lines are a scan chain; responsive to the control unit for loading test signals for the FIG. 5 is a circuit diagram of a scan flip-flop in the FIG. 4b logic blocks and retrieving test signal results from the logic 5 circuit diagram; blocks. The test signals and the test signal results are stored in FIG. 6a is a circuit which generates an out-of-range detec- the memory so that the loading and retrieving operations are tion probe signals for range probes; FIGS. 65 and 6c are the performed at one or more clock signal rates internal to the transistor-level circuits of inverters in FIG. 6a; integrated circuit. The integrated circuit also has a plurality of FIG. 7 is a circuit which generates ground-bounce detec- probe lines which are responsive to the control unit for car- r. 10 tion probe signals for range probes; FIG. 8 is a block diagram of a Built In Self-Test (BIST) rying system operation signals at predetermined probe points engine of the FIG. 2 SPU; of the logic blocks. The system operation signals are also FIG. Sa is a block diagram of an input aligner portion of stored in the memory so that the system operation signals are Analysis Engine of the FIG. 2 SPU; FIG. 9b is a detail of the. retrieved at one or more clock signal rates internal to the 15 15 FIG. Ia Analysis Engine's input aligner; FIG. 9c is a block integrated circuit. diagram of the Analysis Engine's memory addressing struc- The present invention also provides for an integrated cir- ture; FIG.9d is a block diagram of the trigger logic portion of cuit which has an interface for coupling to an external diag- the Analysis Engine; and nostic processor, unit responsive to instructions from the FIG. 10 is a block diagram of another embodiment of the external diagnostics processor, a plurality of probe lines 20 Analysis Engine's memory addressing structure; coupled to the unit, and a memory coupled to the unit and to FIG. 11 shows a probe string connection of probe points to the interface. In response to the unit, the probe lines carry the buffer memory using logic analyzer channels that are sequential of sets of system operation signals at predeter- implemented with probe storage elements (PSE); mined probe points of the integrated circuit and the system FIG. 12 shows an alternative probe string connection with operation signals are stored in the memory at one or more 25 improved multiplexed PSEs which combine probe selection clock signal rates internal to the integrated circuit. The system and data capture functions; and operation signals are retrieved from the memory through the FIG. 13 is a block diagram of the improved PSE of FIG. 12. interface to the external diagnostic processor at one or more DESCRIPTION OF THE SPECIFIC clock signal rates external to the integrated circuit. This EMBODIMENTS allows the external diagnostics processor to process the cap- tured system operation signals. General Organization of the Present Invention The present invention further provides for a method of In accordance with the present invention, a Service Proces- operating an integrated circuit which has logic blocks, a con- sor Unit (SPU) is incorporated within an integrated circuit. trol unit, a memory and a plurality of scan lines of the logic 35 Besides addressing the problems of testing and debugging the blocks. The memory is loaded with test signals and instruc- IC, the availability of a programmable unit, such as the SPU, tions for the control unit and the scan lines responsive to the which may load or unload the state variables into and from the control unit are loaded with the test signals for the logic user-definable logic in an IC, greatly simplifies the problem blocks at one or more clock signal rates internal to the inte- of resetting the IC and observing its current state. The SPU is grated circuit. The logic blocks are then operated at one or 40 implemented in the form of a basic stored-program control more clock signal rates internal to the integrated circuit and unit, such as a microprocessor, with a predefined instruction the resulting test signal results are retrieved from the logic set, a number of extended function units (EFUS), program, blocks along the scan lines at one or more clock signal rates data, and scratch pad memories, plus an input/output circuit internal to the integrated circuit. The test signal results are for loading and unloading the SPU memories with data/pro- stored in the memory at one or more clock signal rates internal 45 grams from the outside world. This allows the SPU to be to the integrated circuit; and the stored test results signals are programmed to execute a control program which interacts processed in the control unit responsive to the stored instruc with the various extended functional units to control various tions in the memory to perform test and debug operations of test and debug related activities on the IC. the logic blocks. Each EFU is designed to control a specific test or debug 50 feature and the EFU provides the control unit a general, BRIEF DESCRIPTION OF THE DRAWINGS programmable access to that feature. For example, one EFU may be designed to control the execution of serial shift opera- FIG. la shows a high-level diagram of an exemplary large tions along some or all of the internal scan chains of the IC. and complex integrated circuit; FIG. 1b shows the FIG. 1a The other EFUs may be enabled to interact with the scan integrated circuit with a Service Processor Unit (SPU), 55 chains, such as a predetermined algorithm to provide a Built- according to one embodiment of the present invention; In Self-Test (BIST) for an embedded Random Access FIG. 2 illustrates one embodiment for the architecture for Memory (RAM) block. The existing scan chains load and the SPU of FIG. 1b; unload the BIST patterns and results to/from the RAM block. FIG. 3a illustrates the coupling between test wrappers, The EFUs provide the control unit with a straight forward, scan strings, probe strings and range probes to a test bus; FIG. 60 programmable mean 3b is a circuit diagram of a test bus connector of FIG. 3a; FIG. EFU such that knowledge of low level details of the scan or 3c is an exemplary connection of multiple test bus connec BIST functions become unnecessary. tors; With its program and data memories, the SPU acts autono- FIG. 4a is a circuit diagram of a block input/output con- mously once its program memory has been loaded with the nector for test wrappers for observing test points outside a 65 desired instruction sequence. The SPU's program memory block along a boundary-scan chain (for example, IEEE may be loaded with the desired program instructions through 1149.1 standard Test Access Port and Boundary Scan Archi the SPU's interface to the external environment. Alterna- 9 US 8,239,716 B2 tively, the instructions may be stored in an on-chip Read Only The benefits of the logic analyzer EFU are such that for Memory (ROM) that has been provided to work as the SPU's certain ICs, only the EFU portion of the SPU is implemented program memory. on the IC. In this alternate embodiment of the present inven- In one embodiment of the present invention, an EFU car- tion, the digital and analog probes are selectively enabled by ries out certain functions of a logic analyzer. A logic analyzer 5 a scan-chain which allows specific control signals to be captures and stores signal state values in a digital system loaded into these probe circuits. The scan chain also carries following the occurrence of a pre-defined event. The logic other control signals to be loaded into a trigger circuit which analyzer then analyzes the captured data and displays the starts and stops the data capture operations. Once the desired results for perusal. With the present invention, the capture and data has been captured into an on-chip RAM, the data is ỉ 10 transported outside the IC for subsequent analysis and dis- storage functions are incorporated into the IC. The EFU- which implements these functions captures and stores not a play. Implementations of the Present Invention single snapshot but a sequence (i.e., history) of signal values As a starting point, FIG. 1a is a diagram of an exemplary using logic probes which are selectively coupled to desired integrated circuit. The IC 100 is complex having a host pro- the iC logic circuits. The logic analyzer EFU IS 15 cessor connected by a system bus to various circuit blocks, configurable to select the location, number and sequential including a third party core and other blocks adapted to the depth of signal channels from a predetermined set of choices application of the IC. The IC also has a peripheral bus which Thus, each logic analyzer channel may be selectively coupled is connected to the system bus by a bridge. The peripheral bus to more than one predetermined capture point by program is connected to other functional blocks, such as a user-devel- ming the control unit and hence, the EFU. A solution is 20 oped core and so on. provided for capturing the history of signal values at the A preferred embodiment of the present invention to test internal points of the IC without having to provide each one of and debug the complex IC of FIG. 1a is shown in FIG. 1b. these points with their shadow register counterpart. The cap Added to the IC 100 is a Service Processor Unit (SPU) 101 tured data are stored in an on-chip Random Access Memory which is coupled to the IC system bus 105 and an added test (RAM). Transportation of the captured data out of the IC is 25 bus 104. Connected to the test bus 104 are test wrappers 102 performed later for analysis by an external computer which which provide test communication channels into selected can reformat and display as required for diagnostics. The blocks 106. More details of the test bus 104 and test wrappers present invention has the benefit of enhanced data accuracy 102 are provided below. The SPU 101 provides a connection with minimal cost overhead by separating the signal captured for an external diagnostics console 103 to view and test the storage function of a logic analyzer into the IC. 30 internal workings of the IC 100. Two different types of logic probes may be used with the As shown in FIG. 2, the SPU 101 has several extended logic analyzer EFU. One type of logic probe, termed the function units (EFUS), including a control unit, such as a digital probe, captures sequences of digital signals from inter microprocessor 211, a buffer memory unit 218, an analysis nal points of the IC. Digital signal values flow from the engine 215, a scan control unit 222, an interrupt handler 221, internal capture point to a logic analyzer channel through the 35 which is further connected to a range check unit 220, a system digital probe. In its simplest form each digital probe has at bus interface 214, a test bus interface 213 and a built-in self least two input ports, a selection means and an output port that test (BIST) engine 212, which are all interconnected by a is directly coupled to a logic analyzer channel. Digital probes processor bus 219. The various EPUs are coupled to the may also be constructed from a series of internal storage processor bus 219 in any desired combination and order. To elements (i.e., flip-flops or latches) to form a pipeline to move 40 provide communication between the external world and the the data from the capture points towards the logic analyzer SPU 101, the bus 219 is also connected to a serial input/output channels. In this case, the movement of the data along the (SIO) interface 210, a parallel input/output interface (PIO) digital probe flip-flops is synchronized with an on-chip clock 216, and a test access port (TAP) 217. For example, the signal. Since the clock frequency also defines the maximum coupling between the IC 100 and the external diagnostics capture rate, the particular clock signal is selected based on 45 console 103, typically implemented using another computer, the maximum desired capture rate. The digital probes used for uses the TAP 217, the SIO interface 210 or the PIO interface the logic analyzer EFU operate with the same electrical and 216. timing characteristics of the native signals of the IC. The Analog probe lines 201 are connected to the range check digital probes are implemented in the same technology, with unit 220 which processes their values to detect out-of-range the same functional logic circuitry, and under the same clock 50 conditions which are then signaled to the interrupt handler timing, as the rest of the IC. Signals are therefore captured and 221. The interrupt handler 221 also receives signals from propagated along the digital probes in exactly the same way trigger event lines 204 directly or from test bus 104 by way of as they are operated upon by the functional circuitry of the IC. test bus connections 203 to the interrupt handler 221. The This assures much greater accuracy of signal states captured signals on the trigger event lines 204 or test connections 203 by the digital probes. In contrast, logic probes used with an 55 are used to capture signal state values when predetermined external logic analyzer must use trigger events and signal (i.e., triggering) events occur. The interrupt handler 221 values that are visible external to the IC. The captured signal passes the captured values to the analysis engine 215. The test values may differ significantly from the original (internal) bus 104 is further coupled to test wrappers 102, which are values. individually wrapped around a number of predetermined The logic analyzer EFU may use a second type of logic 60 blocks 106 on the IC 100. Each test wrapper 102 accesses the probe, termed an analog probe, which captures signal events input and output signals of a block 106. The test bus 104 is representing the detection of signal integrity conditions, such also connected to scan string lines 403, which are connected as ground bounce. Desired signal observation points are to internal elements of a block 106. coupled to analog detection circuits which produce digital As shown in FIG. 3a, the test bus 104 forms a unidirec- signals when particular signal conditions are detected. The 65 tional loop with analog probe records these digital signal states in the logic ring data between the test bus 104 and a test wrapper 102. The analyzer EFU. test bus 104 is made up of multiple bit lines, where the number 9 US 8,239,716 B2 of the bits is determined by the requirements of the test plexer 308 is a test control line 300 from the control unit 311 system. Through test bus connector 401, the test bus 104 is of the SPU 101. The control signal on the line 300 selects selectively connected to test wrappers 102, scan string lines whether the functional signal at data-in terminal 302 or the 403, probe string lines 402 and trigger lines 204. signal held in the scan flip-flop 301 is passed onto the data-out A test bus connector 401 which handles a one bit connec- 5 terminal 307. When the control signal of the line 300 signal is tion between the test bus 104 and a test wrapper 102 is not-asserted, i.e., normal mode, there is normal operational illustrated in FIG. 3b. A first multiplexer 421 has one of its signal flow between the data-in terminal 302 and the data-out input terminals connected to one of the lines of the test bus terminal 307. On the other hand, when the control signal on 104. The other input terminal is connected to a signal line of the line 300 is in asserted state, i.e., test mode, the current state the test wrapper 102. The output terminal of the multiplexer 10 of the scan flip-flop 301 is passed onto the data-out terminal 421 is connected to an input terminal of a flip-flop 426 and to 307; the data-in terminal 302 and the data-out terminal 307 an input terminal of a second multiplexer 422, which has a second input terminal connected to the output terminal of the are isolated from one another. The state stored in the scan flip-flop 426. The output terminal of the flip-flop 426 is also flip-flop 301 is also controls whether the signal at the data-in connected to the line of the test wrapper 102, which is also in 15 terminal 302 or the probe-in terminal 303 is passed onto the the form of a unidirectional loop. The multiplexer 421 selects probe-out terminal 305. In this manner, data from another either the data from the test bus 104 or the test wrapper 102; probe point which is connected to the probe-in terminal 303 the second multiplexer 422 selects between the data selected are selectively passed onto the probe-out terminal 305. The by the first multiplexer 431 or the data captured in the flip-flop signal state in the scan flip-flop 301 value is controlled and 426 to place back onto the test bus 104. These selections are 20 observed using regular scan operations of the test wrapper done under the control of SPU 101. The test bus connector 102 through the scan-in and scan-out terminals 304 and 306. 401 is also be used for coupling a trigger line 204, probe string Of course, if observation of an input or output signal of the line 402 or scan string line 403 to a test bus 104 by connecting block 106 by a probe string 402 is not required, the multi- the desired signal line in place of the line of the test wrapper p lexer 309 can be eliminated from the circuit 310. 102 port as shown in FIG. 3b. 25 A scan string 403 is formed by serially connecting block FIG. 3c shows an embodiment of coupling a trigger line scan connector circuits 320. One such circuit 320, which 204, probe string 402, test wrapper 102 and scan string line couples an internal element of a block 106 to the scan string 403 to three lines of the test bus 104. Other possible configu 403, is illustrated in FIG. 4b. The connector circuit 320 has a rations for the couplings include coupling the test wrapper scan-in terminal 314 and a scan-out terminal 316. The scan-in 102 and scan string 403 onto separate lines of the test bus 104. 30 terminal 314 of one connector circuit is connected to the A test wrapper 102 is formed by serially connecting block scan-out terminal 316 of another connector circuit 320 to I/O connector circuits 310. One such circuit 310, which form a serial scan string 403. The block scan connector circuit couples an input or output signal of a block 106 to the test 320 also has a data-in terminal 312 and a data-out terminal wrapper 102, is illustrated in FIG. 4a. The connector circuit 317 which provide an interstitial connection between internal 310 has a scan-in terminal 304 and a scan-out terminal 306. 35 elements of the block 106. In the normal operation of the IC The scan-in terminal 304 of one circuit 301 is connected to the 100, the connector circuit 320 is a simple path between the scan-out terminal 306 of another circuit 301 to form the serial internal elements in the block 106. The connector circuit 320 chain of a test wrapper 102. The connector circuit 310 also has also has a probe-in terminal 313 and a probe-out terminal 315 a data-in terminal 302 and a data-out terminal 307 which which provide a path for probe signals from selected portions provide an interstitial connection between a block 106 and the 40 of the block 106 through the connector circuit 320 to observe rest of the IC 100. In the normal operation of the IC, the operations in the block 106. connector circuit 310 provides a simple path between the The block scan connector circuit 320 has a scan flip-flop block 106 and the rest of the IC 100. If the connector circuit 311 and a multiplexer 319. The data-in terminal 312 and the 310 is to provide an input signal to the block 106 during test scan-in terminal 314 form the inputs to the scan flip-flop 311. operations, the data out terminal 307 is connected to the block 45 The output from the flip-flip 311 include the scan out terminal 106 and the data in terminal is connected to the rest of the IC 316 and the data-out terminal 317. The data-in terminal 302 is 100. If the block I/O connector circuit 310 is to receive an also connected to one input to the multiplexer 319. The probe- output signal from the block 106 during test operations, the in terminal 313 forms a second inpu data-out terminal 307 is connected to the rest of the IC 100 whose output forms the probe-out terminal 315. A special and the data-in terminal is connected to the block 106. The 50 circuit is used for the scan flip-flop 311 (and the flip-flop 301 connector circuit 310 also has a probe-in terminal 303 and a ofFIG. 4a). The circuit, which is shown in FIG.5 and is found probe-out terminal 305 which provide a path for probe signals in previous IC scan designs, has separate scan-slave and from selected portions of the block 106 through the connector data-slave sections. The separation allows a state signal circuit 310 to observe operations in the block 106. which has been scanned into the scan flip-flop 311 to remain The elements of the connector circuit 310 include a scan 55 unaffected by functional clock pulses that cause the flip-flop flip-flop 301 and two multiplexers 308 and 309. The data-in 311 to capture signals on the data in terminal 312 so that they terminal 302 and the scan-in terminal 304 form the inputs to appear in the data-slave section and on the data out terminal the flip-flop 301. The output from the flip-flip 301 include the 317. The connector circuit 320 acts as a simple conduit for scan out terminal 306 and one input to the multiplexer 308 signals within the block 106. At the same time, the previously having an output which forms the data-out terminal 307. The 60 scanned-in signal, which appears in the scan-slave section, second input to the multiplexer 308 is connected to the data-in selects whether signals at the data in terminal 312 or the terminal 302, which is also connected to one input to the output from another probe point which has been connected to multiplexer 309. The probe-in terminal 303 forms a second the probe-in terminal 313 is to be passed onto the probe-out input to the multiplexer 309 whose output forms the probe terminal 315. A probe string 402 is created. Of course, if an out terminal 305. The control input of the multiplexer 309 is 65 internal scan string 403 need not be connected to a probe the output of the scan flip-flop 301 (and is connected to one string 402, the multiplexer 319 can be eliminated from the input of the multiplexer 308). The control input of the multi circuit 320. 10. 9 US 8,239,716 B2 10 A probe string 402 is formed by serially connecting the and a pattern shift register 713. The output of the multiplexer probe-in terminal of a connector circuit 310 and 320 to the 715 is an input to the LSFR 714. The mask shift register 712 probe-out terminal of another connector circuit 310 and 320. identifies the bit positions whose values are selected from The probe string 402 typically has a set of selectively con predetermined bit patterns in mask shift register 713 versus nected probe points. However, only one probe point along 5 the bit positions which receive the pseudo-random values each probe string 402 may be actively probed at any given generated by the LFSR 714. The output of the multiplexer 715 time. Thus the IC designer selects the probe points which are is a combination of built-in-self-test and functional scan vec- to be connected along the same probe string 402 and deter- tors. These features are useful because random vectors work mines the total number of probe strings 402 that are to be well only when the controls allow the random vectors to connected to the individual bits of the test bus 104. This 10 exercise most of the IC section under test. If there are more structure allows the IC designer great flexibility to optimize than a few control lines, the probability of properly exercising the number of test bus 104 lines with respect to the number of the logic under test with random vectors is very low. These simultaneously observable probe points in the IC. features also allow the SPU 101 to generate regularly repeat- The probes described above are digital probes. Two analog ing patterns; for example, periodic patterns that may be useful probes are illustrated in FIGS. 6a, 6b, 6c and 7. The range 15 in a memory test may be generated by the SPU 101 that may check unit 220 receives inputs from the analog probes that output the data to the section of logic under test via the test bus comprise signals on a threshold check line 600 and a ground or the system bus, whichever has been provided with a con- bounce line 700. The unit transmits these signals to the SPU nection to the SPU 101. 101. FIGS. 6a, 6b and 6c show the circuit which generate the Another EFU of the SPU 101 is the analysis engine 215. signal for the threshold check line 600. The circuit is used for 20 FIG. 9a shows an embodiment of the analysis engine 215 detecting extended intermediate voltage levels. Such voltage which, under the control of the microprocessor 211, captures levels are most likely to occur on an on-chip bus which is in logic signals from the test bus 104. This is achieved by first contention among multiple circuit drivers. The analog probe setting either the scan flip-flops 301 of the block I/O connec- has two inverters 601 and 602, which are both coupled to an tor circuits 310 (FIG. 4a) or the scan flip-flops 311 of the Exclusive-NOR logic gate circuit. FIG. 6b is a transistor 25 block scan connector circuit 320 (FIG. 4b) so that a boundary diagram depicting the low threshold inverter 601, and FIG. 6c connection or an internal point connection of the target block is a transistor diagram depicting the high threshold inverter 106 is selected for probing, respectively. Next, all flip-flops 602. These inverters 601 and 602 exhibit switching properties along the same probe string 402 are programmed (by the SPU characteristic of a very low internal voltage, and a very high 101) so that only signals from the selected probe point are internal voltage device, respectively. Normally, the circuit in 30 allowed to flow through the probe string 402 and arrive at the FIG. 6a has a logic one (1) output level, but during transitions test bus connector 401. The multiplexer 421 and the multi- of the input signal, the outputs of inverters 601 and 602 may plexer 422 in the test bus connector 401 (FIG. 3a) are con- remain in opposite states for a period sufficient to cause the trolled by the SPU 101 so that the signals on the probe string circuit to go to a logic zero (0) output level before returning to 402 are passed along to the test bus 104. Finally, all remaining the logic one (1) output level. This negative pulse can be 35 test bus connector circuits 401 along the same bit line of the captured by the SPU 101. test bus 104 are controlled by the SPU 101 so that they pass FIG. 7 shows a schematic diagram of a ground bounce the probe signals along test bus 104. This allows the selected detector circuit which generates the signals for aground probe signal to arrive at the analysis engine 215 where it is bounce line 700. In this circuit, a quiet (and true) ground captured for subsequent off-line analysis. The input terminals terminal 701 is connected to an N-channel transistor 702, 40 of a plurality of flip-flops 805, one for each bit line of the test which gate is driven by a local ground connection terminal bus 104, form the input port 802 of the analysis engine 215. A 703. A periodic clock on a Reset terminal 706, which is digital phase locked loop (PLL) 802 has selectable clock controlled from the range check 220, clears a pair of NAND outputs 803 to each flip-flop 805 to tune when the data from gates configured as a SR latch 704, and charges a capacitor each probe point is to be captured. The output terminal of each 705 having one terminal connected to the Set input of the SR 45 flip-flop 905 is connected to the input terminal of a variable latch. The second terminal of the capacitor 705 is connected First-In-First-Out shift register (FIFO) 804 to the quiet ground terminal 701. The N-channel transistor FIG. 9b shows the circuit details of each variable First-In- 702 which is gated by the local ground discharges the Set line First-Out shift register (FIFO) 804, each having a number of of the SR latch 704, which flips the state of the SR latch 704 serially-connected register stages 812. Each register stage if the local ground falls above threshold. For example, a 50 812 has a multiplexer which, under control of a decoder 811, ground spike on the local ground may drive the local ground selects between the signal held in a flip below threshold. The frequency and duty cycle of the Reset the incoming signal to the stage to place on the stage's output signal determines the magnitude and duration of a ground terminal. The shift depth of each variable FIFO 804 is pro- spike on the local ground to trigger the probe. A variety of grammable by the SPU 101 by setting a count register 810 for frequencies and duty cycles are created by the range check 55 each bit feeding the analysis engine 215. The value in the 220 to determine the severity of ground spikes. When the count register 810 is decoded by the decoder 811. The result probe is triggered, the probe produces a negative (0) value controls the number of register stages 812 which are until reset by the Reset signal on the terminal 706. bypassed. This compensates for the path delay differences Returning to the components of the SPU 101, FIG. 8 is a among the different probe points by realigning capture times preferred embodiment of the BIST engine 212. A polynomial 60 of signals captured in the analysis engine 215. register 711 identifies the bits in a linear feedback shift reg The analysis engine 215 also has trigger logic which con- ister (LSFR) 714 which are used to form an Exclusive-OR trols the capture of data. FIGS. 9c and 9d show sections of the (XOR) function which generates pseudo-random values. The trigger logic, a programmable circuit which detects one or polynomial register 711 is set by the microprocessor 211, more events to stop the analysis engine 215 from capturing which also initializes contents of the LSFR 714. The output of 65 new data. The data that has been captured up to that point is the LSFR 717 is connected to the inputs of a multiplexer 715 preserved in the buffer memory 218 of the SPU 101. The which also receives the outputs of a mask shift register 712 buffer memory 218 resides in the same address space as the 9 1 US 8,239,716 B2 11 RAM used by the SPU 101 but may be mapped to use high trigger logic so it uses an externally generated trigger condi- memory space in order to prevent interference with the tion 902 in place of an internally programmed event. instructions and data stored in low memory space. When the Program instructions and initial data values for executing analysis-engine 215 collects data, it may be allowed to write programs to implement the functions of the SPU 101 are over old data, keeping only as many most-recent cycles of 5 loaded from the diagnostics console 103 (see FIG.1b) into the data as the buffer memory 218 can hold. The size of the buffer buffer memory 218 of the SPU 101. Some of these programs memory 218 for the analysis engine 215 is determined by the may access the system bus 105 or the test bus 104. A program designer of the IC. can control which test wrapper 102 is accessed by using the The trigger logic has a start address counter 820 and a stop test bus interface 213 in order to set control signals on the test counter 821, which are shown in FIG. 9c. These counters are 10 bus 104. This allows the SPU 101 to read data from a test loaded by the microprocessor 211. The trigger circuit also has wrapper 102 via the test bus 104 into the buffer memory 218 an address counter 822 which is designed to overflow at the and then send said data out to the diagnostic console 103. highest memory address of the buffer memory 218. At that Typically, a separate program executed on the diagnostic point the start address is reloaded with the beginning address console 103 displays this information in a human readable of the high memory space which is reserved for the buffer 15 format as may be appropriate for the given application. 218. This converts a random access memory into a FIFO Programs executed by the SPU 101 can also read data from register. The stop counter 821 decrements when a latched the diagnostics console 103 via the SIO interface 210 or TAP trigger signal line 824 becomes set. Subsequently the analysis interface 217, as shown in FIG. 2b, and write data out to engine 215 collects data into the buffer memory 218 from the individual scan flip-flops on the test wrappers 102 via the test variable FIFOs 804 for as many cycles as defined by the value 20 bus 104. Significant processing, for example, expansion, loaded into the stop counter 821. The system IC designer uses compaction, or intermediate storage of data can be done by the buffer memory size and the value in the stop counter 821 the SPU 101 utilizing the buffer memory 218. In other as two parameters to control the amount of data collected embodiments, control functions may be supplied directly before and after an event has been detected. from the TAP interface 217 or SIO interface 210 to the analy- Also part of the trigger logic is a circuit which generates the 25 sis engine 215 or BIST engine 212, via the processor bus 219 triggering signals on the trigger signal line 824. As shown in without involving the microprocessor 211. The SPU 101 may FIG. 9d, the generating circuit is structured to form Boolean be coupled to either the system bus 205, or a separate test bus AND-OR logic 831 out of individually selectable terms 832. 104, or both. The coupling to the diagnostics console 103 may The terms 832 are fed from a polarity programming logic be via the TAP interface 217 or the SIO interface 210. The test circuit 833 that accepts individual trigger variables, Probe 1 30 bus 104 may be coupled to one or more test wrappers 102. through Probe N. In addition, the true or the complemented Another embodiment of the invention is defined in which value for the output function can be selected through a final the SPU 101 does not include an embedded microprocessor level circuit 830. In one embodiment (shown in FIG.9d), the 211. In this case, the analysis engine 215 and the BIST engine result is also shifted into three successive flip-flops 834. Each 212 can access the buffer memory 218 and system bus inter- of the flip-flops 834 drives one input of each of a plurality of 35 face 214 directly, following instructions received from the multiplexers 835. The other inputs of the multiplexers 835 are external diagnostics console 103. In this case, the loading of set to a logic one (1) level. Each multiplexer 835 is individu the configuration information and transfer of data to and from ally controlled through programmable bits and the multi the analysis engine 215 is controlled using hardwired control plexer outputs are logically ANDed together to form a signal, signals. In this embodiment, the analysis engine 215 is imple- T[i], which represents the presence of the trigger condition 40 mented in the form of an on-chip logic analyzer (OLA) which over four consecutive clock periods. The output from the captures sequential snapshots of sets of signals. The selected AND gate 836 is passed to an AND gate 837 with inputs from signals form the digital probes 202. The selections are the corresponding AND gates 836 of duplicate circuits that achieved by coupling the signals for digital probes 202 to the produce T[0], T[1], through T[n] signals. The output of AND channels of the analysis engine 215 and turning-on enabling gate 837 is stored in a latch 838 to form the latched trigger 45 circuits, if provided, to allow the signals on the digital probes signal on the line 824. Once the signal is set, the latched 202 value to be captured onto channels of the logic analyzer trigger signal maintains its value until it is reset through 215. As shown in FIG. 11, the channels of the logic analyzer reprogramming by the microprocessor 211. In other embodi 215 are formed from probe storage elements (PSE) 1000 to ments, there may be more or fewer latches, and additional form a distributed serial shift register which acts as a pipeline logic to make adjustments to the phases (i.e., the relative 50 to move data captured at a probe point towards the end of the clock cycle when signal is received) of the individual signals. logic analyzer channel where the data are Another embodiment of the trigger logic is shown in FIG. memory 218. Each channel of the analysis engine 215 con- 10. This embodiment provides for the capability of reversing tains zero or more number of PSEs 1000 which are clocked by the data capturing function of the analysis engine 215 from a common periodic clock signal labeled "C" on a clock continually capturing new data until the trigger is detected, to 55 signal line 1001. The clock signal is chosen (at design time) not capturing any data until a trigger is received. In the latter from among the fastest frequency of clock signals which are case, each time a trigger signal on the line 824 is received, the used in generating source signals to be captured by the analysis engine 215 captures new data for a preprogrammed probes. This way all signals captured on the analysis engine number of cycles and then stops until the next latched signal 215 channels arrive at the end of the channels after a fixed, able this mode of operation, 60 predetermined number of clock cycles so that their cycle the trigger circuit shown in FIG. 10 causes the previous trig relationship to one another is preserved, regardless of the ger condition to be cleared so that it, may be recognized again. length (i.e., number of bits) of the individual channels of This mode is very useful since it enables the capture of signals analysis engine 215. around (i.e., before and after) multiple occurrences of trigger Subsequently, after the captured data has been transported conditions. The buffer memory 218 is utilized more effi- 65 to the external diagnostics console 103, software processes ciently as the storage of unwanted cycles of data between the use the number of PSEs 1000 on each channel of the analysis trigger points is not required. It is also possible to program the engine 215 to align the data with respect to one another. The 9 14 US 8,239,716 B2 13 lengths (i.e. number of bits) of the serial shift registers on the the Q output terminal. The multiplexed-PSEs shown in FIGS. individual channels of the analysis engine 215 are determined 12 and 13 build cost efficient logic analyzer channels. at design time so that signal delays due to physical distances Once enabled, the analysis engine 215 captures new values among the PSEs 1000 are sufficiently short to allow data to be first into the flip-flops along the OLA channels and subse- shifted between consecutive bits of the shift registers in a 5 quently into the buffer memory 218 using trigger signals that single clock cycle. If necessary, the number of stages of the have been pre-programmed and implemented as shown in shift registers may be increased to satisfy this condition. Each FIGS. 9c, 9d and 10. channel of the analysis engine 215 is coupled to a different In one mode of operation of the IC 100 shown in FIG. 16, the human engineer may use the diagnostics console 103 to data input port of the buffer memory 218. The collective data 10 initialize both of the system logic and the SPU 101. In this applied to the ports of the buffer memory 218 is written to an manner, the SPU 101 may be programmed to perform logic address in memory which is identified by a common address analyzer functions and specific probe points may be enabled register 822 that advances under control of the periodic clock so that a history of data values appearing at the selected probe signal "C" on the line 1001. points can be captured by SPU 101. Additionally, the trigger FIG. 12 shows a preferred embodiment of a channel of the of the 15 logic shown in FIGS. 9 and 10 may be programmed to select OLA 215 which uses multiplexed PSEs 1000 to combine the a desired trigger event in order to stop the data capture opera- selection of probe points and pipelining captured data into a tions. Next, the diagnostics console 103 invoke the IC 100 to single, efficient design. This enables the coupling one PSE execute its normal system operations. If and when the 1000 to two probe points or another PSE 1000. Scan opera selected trigger event is detected and the analysis engine 215 tions shift a control signal into the PSE 1000 to program itself 20 has captured the required data, the diagnostics console 103 to select one or the other of its input ports. instructs the SPU 101 to transfer the captured data values out The details of a multiplexed PSE are shown in FIG. 13. The of the IC 100 and into the diagnostics console 103 where the PSE 1000, illustrated by a dotted line, is connected to a data may be formatted and presented for analysis and inter- multiplexer 1108 which has two input terminals connected to pretation. The diagnostics console 103 and the SPU 101 can two input probe paths, P1 and P2, for the logic analyzer 25 constrain some of the signals on one or more test wrappers channels. Besides the probe clock signal line 1001, which 102 in order to affect the behavior of the IC 100 and perform carries the Cf signal, the PSE 1000 is connected to a first scan logic analysis under these conditions. For example, this clock signal line 1101, which carries an A_clk signal, a sec approach may be useful to determine how the overall behav- ond scan clock signal line 1102, which carries a B_clk signal, ior of the IC 100 is affected when some of the functionality of and a scan control line 1103, which carries a Scan_mode 30 any one of the blocks 106 is disabled. signal. The PSE 1000 has three latches 1105, 1106 and 1107. In a different mode of operation automatic test equipment The output terminal of the latch 1105 is connected to one (ATE) may access the IC 100 through its TAP interface 217 in input terminal of the latch 1106 and to one input terminal of order to initialize the SPU 101 so that internal scan strings 403 the latch 1107. One input terminal of the latch 1105 is con and test wrappers 102 are loaded with predetermined test nected to the output terminal of the multiplexer 1108 and a 35 values. The response of the blocks 106 is observed using the second input terminal of the latch 1105 forms a scan data scan strings 403 and test wrappers 102. Furthermore, the ATE input terminal 1104, SI. The output terminal of the latch 1107 may be programmed to instruct the SPU 101 to execute BIST forms a scan data output terminal, SO, and is also connected or other buffer memory 218 test functions and to check the to the control terminal of the multiplexer 1108. The output results to determine pass or fail conditions. terminal of the latch 1106 forms an output probe path, Q, for 40 In yet another mode of operation, it is possible to use an the logic analyzer channels. in-circuit test (ICT) or similar board-level test equipment to The scan clock signals, A_clk and B_clk respectively, and access the IC 100 through its TAP interface 217 in order to the Scan_mode signal configure the PSE 1000. For serial shift instruct the SPU 101 to turn-on its external memory test operations, the serial input (SI) on the line 1104 is captured function. In this mode, patterns are generated by the SPU 101 into the latch 1105 when the A_clk signal is applied and the 45 and made to appear at specific I/O pins of the IC 100 which are output of the latch 1105 is captured into the latch 1106 when coupled to external memory. For example, the IC 100 may the B_clk signal is applied. If the Scan_mode signal on the generate the data and address values that are applied to the line 1103 is set to a logic 1, the B_clk signal on the line 1102 external memory. The data responses received are captured in is also passed through a multiplexer 1109 and an AND gate order to determine if the external memory is functioning 1112 to the latch 1107 by a clock signal line 1111. Thus, 50 correctly. non-overlapping A_clk and B_clk signals on the clock signal While the description above provides a full and complete lines 1101 and 1102 respectively clock serial shift operations disclosure of the preferred embodiments of the present inven- in the PSE 1000. Signals scanned into the latch 1105 through tion, various modifications, alternate constructions, and line 1104 are also scanned into the latch 1107 (and the latch equivalents will be obvious to those with skill in the art. Thus, the pro- 55 the scope of the present invention is limited solely by the gramming of the PSE 1000 such that value that has been metes and bounds of the appended claims. loaded into the latch 1107 controls input multiplexer 1108 What is claimed is: which selects between two input ports 1109 and 1110. Once 1. An integrated circuit comprising: the PSE 1000 has been programmed, the Scan_mode signal one or more logic blocks configured to generate one or on control line 1103 signal is set to and maintained at logic 0 60 more system operation signals at one or more system until the PSE 1000 is programmed with a new value. When operation clock rates; the Scan_mode signal is set to logic 0, the PSE 1000 performs a service processor unit configured to perform one or more its normal data capture function using the clock signal Cf on debug operations on one or more of said logic blocks, the the line 1001. The Cf clock signals are passed by the multi- service processor unit comprising: plexer 1109 to the latch 1106 by a clock signal 1110. The latch 65 a control unit, 1106 captures the signals from the latch 1105 and the multi- a buffer memory, plexer 1108 at the Cf clock rate and passes the signals out to an analysis engine, and 9 US 8,239,716 B2 15 a bus interface; and a multiplicity of probe lines configured to capture and propagate one or more of said one or more system opera- tion signals from said logic blocks to said service pro- cessor unit during normal system operation; wherein said analysis engine is configured to align signals received from said probe lines during normal system operation. 2. The integrated circuit as in claim 1, wherein said analysis engine includes a variable first-in, first-out (FIFO) element. 3. The integrated circuit as in claim 1, wherein said analysis engine is configured to store aligned signals in said buffer 5 memory. 9 UNITED STATES PATENT AND TRADEMARK OFFICE CERTIFICATE OF CORRECTION PATENT NO. APPLICATION NO. Page 1 of 1: 8,239,716 B2: 12/717391: August 7, 2012: Dervisoglu et al. DATED INVENTOR(S) It is certified that error appears in the above-identified patent and that said Letters Patent is hereby corrected as shown below: Title Page 2, in Field (56), under "OTHER PUBLICATIONS", in Column 2, Line 16, delete "t al.," and insert -- et al., --, therefor. Title Page 2, in Field (56), under "OTHER PUBLICATIONS", in Column 2, Line 67, delete "Anaylzer"," and insert -- Analyzer", --, therefor. In Column 3, Line 19, delete "processor, unit and insert -- processor, a unit --, therefor. In Column 4, Line 18, delete "Engine; and" and insert -- Engine; --, therefor. In Column 4, Line 29, delete "DESCRIPTION" and insert -- DETAILED DESCRIPTION --, therefor. In Column 9, Line 38, delete "aground" and insert -- a ground --, therefor. In Column 11, Line 62, delete "that it, may" and insert -- that it may --, therefor. Signed and Sealed this Eighth Day of January, 2013 David S. Kappos. David J. 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