American Patents LLC v. Mediatek, Inc. et al

Western District of Texas, txwd-6:2018-cv-00339

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2 EXHIBIT 5 Case 6:18-47-00339ADA Document 166-5 Filed 10/25/11,9mbbrale 29f_29 Please type a plus sign (+) inside this box PROVISIONAL APPLICATION FOR PATENT COVER SHEET (Small Ent. This is a request for filing a PROVISIONAL APPLICATION FOR PATENT under 37 CFR 1.53 (C). 03/25/98 INVENTOR(SYAPPLICANT(S) Given Name (first and middle (if any)) Family Name or Sumame Residence (City and either State or Foreign Country) Bulent Ismail | Dervisog Mountain View, California Laurence Hager Cooke Los Gatos, California Vacit Arat Los Altos Hills, California | Additional inventors are being named on page 2 attached hereto TITLE OF THE INVENTION (280 characters max) On-Chip Service Processor CORRESPONDENCE ADDRESS Direct all correspondence to: Customer Number - Place Customer Number Bar Code Label here OR [XI individual Name Bulent Ismail Dervisoglu 495 Sieeper Avenue Address Address City Country 50079316.032598 Mountain View State CA ZIP 94040 10.S, A. Telephone (050) 964.33981 Fax 16504428-0411 ENCLOSED APPLICATION PARTS (check all that apply) Number of Pages Small Entity Statement return receipt postcard Number of Sheets 9 L Xl Other (specify) to inventor' #1 Specification 18 X7 Drawing(s) METHOD OF PAYMENT OF FILING FEES FOR THIS PROVISIONAL APPLICATION FOR PATENT (check one) IXI A check or money order is enclosed to cover the filing fees FILING FEE AMOUNT The Commissioner is hereby authorized to charge filing fees or credit any overpayment to Deposit Account Number: $75.00 The invention was made by an agency of the United States Government or under a contract with an agency of the United States Government No. 1 Yes, the name of the U.S. Government agency and the Government contract number are: Respectfully submitted, SIGNATURE_Bluettes SIGNATURE Date 03/18/1998 TYPED or PRINTED NAME REGISTRATION NO. (if appropriate) TELEPHONE (650) 964-3398 USE ONLY FOR FILING A PROVISIONAL APPLICATION FOR PATENT SEND TO: Box Provisional Application, Assistant Commissioner for Patents, Washington, DC 20231 (Page 1 of 1 P19SMALL REVO4 2 DOCKET NUMBER BLV-98-01 function. When the selected trigger event is detected and the Analysis Engine stops capturing data, the engineer may use the Diagnostics Console to instruct the SPU to transfer the captured data values out of the SIC and into the Diagnostics Console where the data may be formatted and presented to the engineer for interpretation. The engineer may also use the Diagnostics Console and the SPU to constrain some of the signals on one or more test wrappers in order to affect the behavior of the SIC and perform logic analysis under these conditions. For example, this approach may be useful to determine how the overall behavior of the SIC is affected when some of the functionality of any one of the core blocks is disabled. In a different mode of operation Automatic Test Equipment (ATE) may be used to access the TAP port of an SIC and use that to initialize the SPU in order to enable the internal scan chains of the SIC and test the SIC using pre-determined test vectors Furthermore, the ATE may be programmed to instruct the SPU to execute BIST or embedded memory test functions and to check the results to determine pass or fail condition. Using yet another mode of operation it is possible to use an In-Circuit Test (ICT) or similar board-level test equipment to access the TAP port of the SIC in order to instruct the SPU to turn-on its external memory test function. In this mode, patterns may be generated by the SPU and made to appear at specific I/O pins of the SIC which are coupled to the external memory. For example, the SIC may generate the data and address values that are applied to the external memory and capture the data responses received in order to determine if external memory is functioning correctly. Summary The above invention is the inclusion of one or more of the following elements in a larger Integrated Circuit; a stored program microprocessor, a logic analyzer function, a built-in self test pattern generator, a circular test bus, scan and probe strings around sections of the chip, specifically to aid in the test, debug, diagnostics, initialization, and optimization of the operation of the rest of the Integrated Circuit. Abstract An integrated circuit which includes a stored program processor with an on-chip memory and external interface that includes one or more of a logic analyzer, a bus monitor, a scan string controller, a built-in self test generator, and a bus transaction analyzer. The external interface can couple to a separate computer for controlling the execution of the above functions and displaying the results The external interface may be via an existing test interface, or a separate serial or parallel port. Page 8 of 17 Case 6:18-C12-00339-ADA Document 166 5_Filed 10/25419_Page 20622 Page 1 of 2 VERIFIED STATEMENT (DECLARATION) CLAIMING SMALL ENTITY Docket No. STATUS (37 CFR 1.9(f) AND 1.27 (b)) - INDEPENDENT INVENTOR BLV-98-01 Serial No. Filing Date Patent No. Issue Date Applicant/ Bülent Ismail Dervisoplu Patentee: Laurence Hager Cooke - Vacit Arat Invention: On-Chip Service Processor As a below named inventor, I hereby declare that I qualify as an independent inventor as defined in 37 CFR 1.9(c) for purposes of paying reduced fees under section 41(a) and (b) of Title 35, United States Code, to the Patent and Trademark Office with regard to the invention entitled above and described in: w the specification to be filed herewith. o the application identified above. o the patent identified above. T have not assigned, granted, conveyed or licensed and am under no obligation under contract or law to assign, grant, convey or license, any rights in the invention to any person who could not be classified as an independent inventor under 37 CFR 1.9(c) if that person had made the invention, or to any concern which would not qualify as a small business concern under 37 CFR 1.9(d) or a nonprofit organization under 37 CFR 1.9(e). Each person, concern or organization to which I have assigned, granted, conveyed, or licensed or am under an obligation under contract or law to assign, grant, convey, or license any rights in the invention is listed below: No such person, concern or organization exists. Each such person, concern or organization is listed below. *NOTE: Separate verified statements are required from each named person, concern or organization having rights to the invention averring to their status as small entities (37 CFR 1.27) FULL NAME ADDRESS o individual Small Business Concern Nonprofit Organization FULL NAME ADDRESS Individual 0 Small Business Concern Nonprofit Organization FULL NAME ADDRESS Individual Small Business Concern O Nonprofit Organization FULL NAME ADDRESS 0 Individual Small Business Concern Nonprofit Organization Copyright 1994 Legalsoft PO3/REVO1 Patent and Trademark Office-U.S. DEPARTMENT OF COMMERCE Case 6:18-01-00330.ADA Document 166.5 Eiled 10125/19 Page 13 of 22 Page 2 of 2 I acknowledge the duty to file, in this application or patent, notification of any change in status resulting in loss of entitlement to small entity status prior to paying, or at the time of paying, the earliest of the issue fee or any maintenance fee due after the date on which status as a small entity is no longer appropriate. (37 CFR 1.28(b)) Thereby declare that all statements made herein of my own knowledge are true and that all statements made on information and belief are believed to be true; and further that these statements were made with the knowledge that willful false statements and the like so made are punishable by fine or imprisonment, or both, under Section 1001 of Title 18 of the United States Code, and that such willful false statements may jeopardize the validity of the application, any patent issuing thereon, or any patent to which this verified statement is directed. DATE: 3-18-1998 NAME OF INVENTOR Bulent Ismail Dervisoglu SIGNATURE OF INVENTOR B. At the NAME OF INVENTOR Laurence Hager Cooke SIGNATURE OF INVENTOR Jom the Last NAME OF INVENTOR Vacit Arat. SIGNATURE OF INVENTOR DATE: 3/18/98 DATE: 3/18/1998 DATE: NAME OF INVENTOR SIGNATURE OF INVENTOR w DATE: NAME OF INVENTOR SIGNATURE OF INVENTOR DATE: NAME OF INVENTOR SIGNATURE OF INVENTOR DATE: NAME OF INVENTOR SIGNATURE OF INVENTOR DATE: NAME OF INVENTOR SIGNATURE OF INVENTOR DATE: NAME OF INVENTOR SIGNATURE OF INVENTOR DATE: NAME OF INVENTOR SIGNATURE OF INVENTOR DATE: Patent and Trademark Office-U.S. DEPARTMENT OF COMMERCE 2 DOCKET NUMBER BLV-98-01 System IC 3rd-Party Core III|||||||| UUTII CAM011 Bus Interface Block 2 Host Processor System Bus. . Bridge User-Developed Core TTTTTTTTTTTTTTTT DILLUMIE ... Peripheral Bus Figure la (prior art) 865280" STE6ZOOS Test Wrapper Service Processor ...... 3rd Party Core HHHHH Dus laterace Block Diagnostics Console Host Processor Xxii Systen Bus _Test Bus Bridge I MINIT User-Developed Сcre Jewellery Y — System IC Periphera Bus Figure 1b Page 9 of 17 2 DOCKET NUMBER BLV-98-01 Service Processor Analog Probes Buffer Memory Interrupt Micro Analysis BIST Handler | Processor Engine Engine Scan Range Bus Port SIO Control Check & Monitor Interface Triggers Test Bus- On Chip Bus Figure 2a Analysis Engine micro- processor BIST engine parallel SIO ΤΑΡΙ muxed ΙΙΟ System Test Processor Bus Buffer Memory Bus Bus Interface Interface Figure 2b Page 10 of 17 2 DOCKET NUMBER BLV-98-01 probe out scan out probe put scan out test 1 ScanIN FF Data in- Scan FF - Data out Data in Data out probe in scan in Figure 3a probe in scan in Figure 3b 86S2EO" 99€6. 2009 Scan Cik B Scan Clk A Data out out Data in Scan FF - in in out Probe Scan out out Scan in - Master Scan Slave Scan out Data Scan in Scan FFL Data Lin in out Data Data Data in Data out Slave Probe Scan Dam out out Data Scan FF System Clk in Lin in out Probe Scan Figure 3c (prior art) Figure 3d Page 11 of 17 2 DOCKET NUMBER BLV-98-01 Test Bus Scan Port Test Bus Probe strings Scan Strings Figure 4a SPU Test bus Test Bus Wrapper Interface Test Test Wrapper – Test Bus Figure 4b From Wrapper To Test bus Figure 4c Page 12 of 17 2 DOCKET NUMBER BLV-98-01 +V +V Figure 5a Figure 5b Figure 5c Gnd Probe Reset Quiet Ground Local Ground Figure 6 Page 13 of 17 2 DOCKET NUMBER BLV-98-01 Mask Shift Register Pattern Shift Register HHHHHH Mixed BIST/ Functional Scan Vectors Polynomial Register Figure 7 Variable FIFO Scan Variable FIFO TO Buffer Memory Probe Inputs Variable FIFO Variable FIFO Digital PLL Figure da Page 14 of 17 2 DOCKET NUMBER BLV-98-01 Variable FIFO pt DI Decode | Count Register Figure 86 Buffer Memory Address Data input 86S2EO" 92867009 » Address Counter IL Load From Variable FIFO Latched Stop Counter Trigger Start Address Figure 8c Page 15 of 17 2 DOCKET NUMBER BLV-98-01 591 T[i] IIIIIIIII Probe-K- Probe-Ka D ro T[O] - Latched Trigger T(n-1) T[n] Figure 8d 8652E0"91€67009 Page 16 of 17 2 DOCKET NUMBER BLV-98-01 Buffer Memory Address Data input [-2 From Probes » Address Counter Load Stop Counter Start Address Clock triggers ext ITR-Q Stop Count o Figure 9 Page 17 of 17 2 PROVISIONAL APPLICATION FOR PATENT COVER SHEET (Small Entity) INVENTOR(SVAPPLICANT(S) Given Name (first and middle (if anyl) Family Name or Sumame Residence (city and either State or Foreign Country) Certificate of Mailing by Express Mail Il certify that this provisional patent application cover sheet, provisional patent application and fee is being deposited on with the U.S. Postal Service as "Express Mail Post Office to Addressee' service under 37 C.F.R. 1.10 and is addressed to the Assistant Commissioner for Patents, Washington, D.C.20231. c Signature of Person Mailing Correspondence t Ismail Dervisoglu Typed or Printed Name of Person Mailing Correspondence USE ONLY FOR FILING A PROVISIONAL APPLICATION FOR PATENT SEND TO: Box Provisional Application, Assistant Commissioner for Patents, Washington, DC 20231 [Page 2 of 2] P19SMALL/REV04 2 DOCKET NUMBER BLV-98-01 Provisional Patent Application of Bulent Dervisoglu, Laurence H. Cooke and Vacit Arat for On-Chip Service Processor Field of Invention Microprocessor incorporating special instructions, co-processors and test interfaces, to operate as an on-chip diagnostic and test processor for System ICs. Background of the invention The complexity of integrated circuits (IC's) demands that special features are included in their design in order to facilitate their testing. For example, a technique know as Scan is commonly utilized whereby, during the IC test mode, internal flip-flops of the IC are configured in the form of a serial shift register so that straightforward serial shift (i.e. scan) operations are utilized to load the flip-flops with desired values or observe their present values. ICs that comprise many flip-flops require special features to reset the flip- flops (i.e. bring the IC to a known starting state). Including such Reset and Scan logic in the design of IC's has become common place. The size of integrated circuits has grown in gate count to the point where it has become inefficient and expensive to test and debug ICs using traditional scan techniques. It has now become extremely beneficial to put more than the traditional reset or scan logic on the IC. Historically, large system designs have incorporated separate console or service processors on circuit boards. These separate processors have had a number of useful functions. For example, they may control the scan strings in the system; originate diagnostics that are run on the main system, etc. They have also provided diagnostic and scan debug features including providing field engineers and remote-service specialists access to the internal registers and memory within the system. Service processors have also been used to bring-up the main system during power up. All of these functions have helped system designers in designing and debugging their systems. As IC technology continues to advance, it has become cost effective and desirable to include a service processor embedded within the IC itself. An advantage that this solution provides is the ease of observability of the target system that an embedded service processor makes possible. Many integrated circuits operate at internal clock speeds that exceed the frequency of signals at the chip Input and Output (I/O) boundary. An internal service processor can execute diagnostic programs at the native system speeds and can access many more points in the system than is feasible from an external processor. In addition, an on chip service processor can reduce the amount of test logic required elsewhere within the chip. For all of these reasons a preferable way of designing large Page 1 of 17 Caše 6:18-CV-00339-ADA Document 166-5 Filed 10/25/19 Page 5 of 22 DOCKET NUMBER BLV-98-01 integrated circuits is to include such a dedicated processor embedded within the target integrated circuit. Summary of the Invention The invention provides a small, stored-program processor (SPP) integrated onto a system IC chip with dedicated peripheral hardware, special instructions and co-processor functions for implementing diagnostics, debug and test functions. In a preferred embodiment, the invention comprises a micro controller with special functions for built-in- self-test (BIST), control of internal test scan strings, an interrupt handler for special triggers, digital and analog probes, and a module for logic analyzer functions. This processor couples to and controls a test bus for fast access to multiple bits within the scan strings coupled to a test port on the test bus. The test bus may comprise scan data and control signals as well as other signals for configuring the circuitry of the IC. In a preferred embodiment each scan string provides means for observing its state from the service processor. The service processor may be coupled to the outside world via test pins of a device such as an IEEE 1149.1 Test Access Port (TAP), a standard serial 1/0 interface, etc. Brief description of drawings. Figure la shows a high-level diagram of a large and complex IC, referred to as a System IC (SIC). Figure 1b shows the SIC with the components of the present invention also added and also shows how the SIC may be coupled to an external Diagnostics Console. Figure 2a shows component modules of an embodiment of a Service Processor Unit (SPU) and Figure 2b shows one embodiment for the architecture for the SPU. Figure 3a shows one embodiment of the means for observing test points along a boundary- scan chain (for example, IEEE 1149.1 standard Test Access Port and Boundary Scan Architecture). Figure 3b shows one embodiment of the means for observing test points along an internal-scan chain. Figure 3c shows an example of prior art for a scan flip-flop Figure 3d shows a subset of a scan and probe string. Figure 4a shows the coupling between scan strings and the test bus. Figure 4b shows the structure of the test bus. Figure 4c shows the structure of a test port on the test bus. Figure 5a shows the digital construction of an out-of-range detection probe. Figures 5b and 5c are the transistor-level details of two components in figure 5a. Figure 6 is a diagram of a ground-bounce detection probe Figure 7 is a diagram of an embodiment of a Built In Self-Test (BIST) engine. Page 2 of 17 2 DOCKET NUMBER BLV-98-01 Figure 8a is a diagram of an embodiment of the Analysis Engine. Figure 8b is one element of the Analysis Engine. Figure 8c is a diagram of the Analysis Engine's Memory addressing structure. Figure 8d is a diagram of one embodiment of the trigger logic for the Analysis Engine. Description of preferred embodiments. In a preferred embodiment of the invention, as shown in figure lb, the following components are added to a system IC as shown in figure la, an SPU which is coupled to both the IC's system bus and a test bus. The coupling from the IC to the external diagnostics console, typically implemented using another computer, uses the Test Access Port, or an SIO interface. The test bus is further coupled to test wrappers comprising scan strings, which are individually wrapped around a number of cores on the IC. Each test wrapper is used for accessing the input and output signals of a core block, and optionally, the internal states of the core. Preferred embodiments of these elements can be seen in figures 3a and 3b, which will be discussed below). Program instructions and initial data values necessary for executing programs that implement the functions of the SPU are loaded from the diagnostics console into the SPU's buffer memory. Some of these programs may access the system bus or the test bus. A program can control which test wrapper is accessed by using the test bus interface, shown in figure 2b, to set control signals on the test bus. This allows the SPU to read data from a test wrapper via the test bus into the buffer memory and then send the read data out to the diagnostic console. Typically, a separate program executed on the diagnostic console displays this information in a human readable format that is appropriate for the application. Programs executed by the SPU can also read data from the System Console via the SIO or TAP interfaces, as shown in figure 2b, and write the data out to individual scan flip-flops on the test wrappers via the test bus. Significant processing, for example expansion, compaction, or intermediate storage of data can be done by the SPU utilizing the buffer memory. In other embodiments, control functions may be supplied directly from the TAP or SIO to the analysis or BIST engines without involving the SPU. Another embodiment is defined in which the SPU does not include an embedded stored program processor, SPP. In this case the analysis or BIST engines can access the buffer memory and bus interfaces directly, following instructions sent to the SIC from the diagnostics console. The SPU, shown in figure 1b, may be coupled to either the IC's system bus or a separate test bus or both. The coupling to the outside terminal may be via a Test Access Port (TAP), or an SIO interface. The test bus may be coupled to one or more test wrappers. Page 3 of 17 2 DOCKET NUMBER BLV-98-01 Figure 3a shows an embodiment of the circuitry for a test point in a test wrapper The test signal controls whether the device is in a test mode or normal operation. In a test mode, the value on the output of the circuit is defined by the flip-flop and the value on the input is captured by the flip-flop. This is a scan flip-flop, and thus the logic value on the input is isolated from the logic value on the output. Under normal operation, the flip-flop is bypassed and the state of the flip-flop controls a multiplexor. This multiplexor selects either the value of the input signal or the value of the previous bit of the probe string to be reflected at the output port of the multiplexor. The probe string is formed by the cascading of the multiplexors such that the desired input value is reflected at the probe string output port by setting the scan string with all logic zero values except a single logic one value that corresponds to the input position to be observed. Each of the scan strings may be coupled to the test bus via a test port. A high level diagram of a test port is shown in figure 4a. The test bus is a circular unidirectional bus with ports coupled to it for transferring data to the test wrappers as shown in figure 4b. One embodiment of a test port is shown in figure 4c. A first multiplexor selects either the data from the bus or the wrapper to forward on to. A second multiplexor selects between forwarding the data on the bus directly or forwarding the registered data. These selections are done via individual bit control signals from the SPU, to facilitate observation of signals during system operation. The test port can also couple special analog probes to the test bus, for observation by the SPU. Preferred embodiments of two such probes can be seen in figures 5a, 56, 5c and 6. A high level diagram of an embodiment of the SPU is shown in figure 2a. This unit consists of an SPP core plus a number of optional tightly coupled units including: a) buffer memory for instructions and data, b) bus interface and monitor, c) an SIO interface for coupling to a console monitor, d) a scan control unit that interfaces to the test bus described above, e) a range checker to verify proper usage of the on-chip bus, f) an interrupt handler for another way of accessing probe data from sensors as shown in figures 5a, 56, 5c and 6, g) a BIST engine, an example of which is shown in figure 7, and h) an analysis engine, one example of which is shown in figures 8a, and 8b. The coupling between these units can be seen in more detail in figure 2b A high-speed processor bus facilitates coupling a variety of components within the SPU without having to redesign each configuration. In addition to the SIO interface, the SPU may also include a parallel input and output (PIO) interface. This requires more pins than the SIO, but re-uses much of the control logic of the SIO interface. The TAP interface couples to external test pins via a device such as an IEEE 1149.1 Standard Test Access Port. This is used for testing and initializing the SPU, as well as for loading scan data into the scanable flip-flops of the IC. The various units couple to the processor bus in any desired combination and order. Figures 5a, 5b and 5c show the components of an embodiment of an analog probe which may be used for detecting extended intermediate voltage levels. Such voltage levels Page 4 of 17 2 DOCKET NUMBER BLV-98-01 are most likely to occur on an on-chip bus that is in contention. The analog probe has two inverters coupled to an exclusive nor in figure 5a. Figure 5b is a transistor diagram depicting a low threshold inverter, and figure 5c is a transistor diagram depicting a high threshold inverter. These inverters exhibit switching properties characteristic of a very low internal voltage, and a very high internal voltage device, respectively. Normally the circuit in figure 5a will output a logic one (1) level, but during transitions of the input signal the two inverter outputs may remain in opposite states for a period of time that is long enough to cause the output of the circuit to go to a logic zero (0) level before the input signal returns back to the logic one (1) level. This negative pulse can be captured by the SPU. Figure 6 shows a schematic of an embodiment of a ground bounce detector. In this circuit, a quiet (and true) ground is routed to the N channel transistor which is driven by the local ground connection. A periodic clock called -reset clears the pair of NAND gates configured as a SR latch, and charges up the capacitor on the -set input of the SR latch. The N channel transistor gated by the local ground discharges the -set line of the SR latch, which flips the state of the SR latch if the local ground falls below threshold, for example if a ground spike occurs on the local ground. The frequency and duty cycle of the -reset signal determines how large and long a ground spike on the local ground must be to trigger the probe. When the probe is triggered, the probe produces a negative (0) value until reset by the reset signal. Figure 7 is a preferred embodiment of a BIST engine. The polynomial register identifies the bits in the Linear Feedback Shift Register (LSFR) that are used to form the exclusive-or (EXOR) function that generates pseudo-random values. The polynomial register is set by the SPU. The initial contents of the LSFR are also set by the SPU. The mask shift register identifies the bit positions whose values are selected from predetermined patterns versus bit positions that receive the pseudo-random values generated by the LFSR. These features are useful because random vectors work well only when the controls allow the random vectors to exercise most of the section under test. If there are more than a few control lines, the probability of properly exercising the logic under test with random vectors is very low. These features also allow the SPU to generate regularly repeating patterns, For example periodic patterns that may be useful in a memory test may be generated by the SPU. Figure Sa shows how the analysis engine in the SPU may capture the logic value of a test wrapper test, or probe point. This is achieved by first setting the scan flip-flop circuit in figure 3a to enable the desired signal to be probed and setting the test signal to reflect the scan flip-flop value at the test wrapper output port. This creates a direct multiplexor path to the analysis engine input port where the signal is captured. In figure 8a, the digital phase locked loop (PLL) has selectable clock outputs to tune when the data from each probe point is captured, and figure 8b shows the details within each Variable FIFO. The Variable FIFO's shift depth is programmable by the SPU setting the count register for each bit in the engine. This logic essentially compensates for Page 5 of 17 2 DOCKET NUMBER BLV-98-01 the path delay differences from the different probe points being accessed. The output from the Variable FIFOs are realigned in time so the designer or user can detect timing and cycle errors easily Figures 8c and 8d show sections of the Trigger Logic that is a programmable circuit to detect one or more events which, when detected, causes the Analysis Engine to stop capturing new data and preserve the data that has been captured up to that point. Figure 8c shows a high level diagram of the memory addressing structure of the Analysis Engine. The Start Address and Stop counter are loaded from the SPU processor. The Address counter is designed to overflow at the highest memory address of the Buffer memory. At that point the start address is reloaded. This is a common practice to convert a random access memory into a FIFO. When the analysis-engine is collecting data it may write over the old data, keeping only as many cycles of data as the buffer can hold. The system IC designer can choose the size of the data retention buffer for the logic Analysis Engine. This buffer resides in high memory, so as not to interfere with the instructions and data in low memory. The stop counter begins decrementing when the trigger is set. As a result, when a trigger event occurs, the Analysis Engine will continue to collect information in the memory for as many cycles as are defined in the stop counter. In this way the system IC designer can control how much data is collected before and after an event has been detected. The trigger logic forms a Boolean AND-OR logic out of individual trigger signals (Probel, through Probe K in figure 8d) and also offers programmability to select the true or the complement value function. In one embodiment (shown in figure 8d), the result is shifted into three successive flip-flops. Each of the flip-flops drives one input of a multiplexor with the other input of each multiplexor set to a logic one level (1). Each of the multiplexors is individually controlled through programmable bits. The multiplexor outputs are AND'ed together to form a signal (T[i]) that represents the presence of the trigger condition over four clock periods. Output from the said AND gate is then AND'ed with outputs from the corresponding AND gates of duplicate circuits that produce T[0}, T[1], through T[n] signals and is then latched. In other embodiments there maybe more or fewer latches, and additional logic to make adjustments to the phases (i.e. relative clock cycle when signal is received) of the individual signals. Another embodiment of the Trigger Logic is shown in figure 9. This embodiment provides for the capability to reverse the data capturing function of the Analysis Engine from continually capturing new data until the trigger detected to not capturing any data until a trigger is received. In the latter case, each time a trigger is received the Analysis Engine captures new data for a pre-programmed number of cycles and then stops again until the next trigger is received. This mode is very useful since it enables more efficient use of the Analysis Engine memory by not storing unwanted cycles of data between the trigger points. Page 6 of 17 2 DOCKET NUMBER BLV-98-01 In an embodiment of the SPU, which does not include and SPP, the loading of the configuration information and the transfer of the data from the buffer memory may be done by hardwired controls. In another embodiment, the Analysis Engine or on-Chip Logic Analyzer (OLA) captures sequential snapshots of set of signals, which are selected to form the probe signals. Said selection is achieved by coupling the probe signals to the channels of the OLA and turning-on enabling circuits, if provided, to allow the probe signal value to be captured onto the logic analyzer channel. Logic Analyzer channels are formed from Probe Storage Elements (PSE) to form a serial shift register that acts as a pipeline to move data captured at the Probe point (i.e. the beginning of the Logic Analyzer channel) towards the end of the channel. Each OLA channel contains the same number of PSE's which are clocked by a common periodic clock signal, termed "Cf". The said clock signal (i.e. "CI) is chosen (at design time) from among the fastest frequency of clock signals which are used in generating source signals to be captured by the probes. This way all signals captured on the OLA channels arrive at the end of the channels after the same, fixed number of clock cycles so that their cycle relationship to one another is preserved, regardless of how long (i.e. number of bits) the OLA channels are. The length (i.e. number of bits) of the serial shift registers on the OLA channels is determined at design time so that signals can be shifted between consecutive bits of the shift registers on the OLA channels in a single clock cycle. If necessary, the number of stages of the shift registers may be increased to satisfy this condition. Each OLA channel is coupled to a different Data Input port of an embedded memory block. The collective data applied to the Data Input ports of the memory block is written to an address in memory which is identified by a common address register. The address register is incremented and the data is written into the memory block under control of the periodic clock signal "Cf". Once enabled, the OLA continues to capture new values onto the OLA channels and subsequently into the embedded memory until a trigger signal is received The memory address register is designed to access memory locations in consecutive fashion and return back to the beginning address when all memory locations have been written into. The trigger signal is generated using logic circuits that produce a trigger signal when a programmable condition has been detected. Capturing of signals into the memory block may be stopped after a programmable number of cycles of the "Cf' clock elapse following the trigger condition. This allows placing the trigger condition at any cycle within the capture window of the OLA, where the capture window is determined by the depth (i.e. number of independently addressable locations) of the memory block. In one mode of operation of the SIC shown in figure 1b, the human engineer may use the Diagnostics Console to initialize both of the system logic and the SPU logic on the SIC. This way the SPU may be programmed to perform the functions of the Analysis Engine and specific probe points may be enabled so that a history of data values appearing at the selected probe points can be captured by the Analysis Engine. In addition, the trigger logic may be programmed to select a desired trigger event in order to stop the data capture phase of Logic Analysis. Next, the SIC may be enabled to performing its desired Page 7 of 17