American Patents LLC v. Mediatek, Inc. et al

Western District of Texas, txwd-6:2018-cv-00339

Exhibit A - '001 Patent

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7 EXHIBIT A 7 USOO6964001B2 (12) United States Patent (10) Patent No.: US 6,964,001 B2 Dervisoglu et al. (45) Date of Patent: Nov. 8, 2005 (54) ON-CHIP SERVICE PROCESSOR 5,068,881 A 11/1991 Dervisoglu et al. 5,155.432 A 10/1992 Mahoney (75) Inventors: Bulent Dervisoglu, Mountain View, CA 5,202.624 A 4/1993 Gheewala et al. (US); Laurence H. Cooke, Los Gatos, 5,202.625 A 4/1993 Farwell 5,206.862 A 4/1993 Chandra et al. CA (US); Vacit Arat, La Canada 5,254,482 A 10/1993 Fisch Flintridge, CA (US) 5,369,648 A 11/1994 Nelson (73) Assignee: On-Chip Technologies, Inc., Los 5,418,470 A * 5/1995 Dagostino et al. .......... 324/763 5,428,629 A 6/1995 Gutman et al. Gatos, CA (US) 5,479,652 A * 12/1995 Dreyer et al. ................. 714/30 5,495.486 A 2/1996 Gheewala (*) Notice: Subject to any disclaimer, the term of this 5,590,354 A * 12/1996 Klapproth et al. ............ 714/30 patent is extended or adjusted under 35 5,642,478 A 6/1997 Chen et al. U.S.C. 154(b) by 76 days. 5,724.505 A * 3/1998 Argade et al. ................ 714/45 5,761,489 A 6/1998 Broseghini et al. (21) Appl. No.: 10/767,265 5,771,240 A 6/1998 Tobin et al. 5,838,163 A 11/1998 Rostoker et al. (22) Filed: Jan. 30, 2004 5,854.996 A 12/1998 Overhage et al. 5,905,738 A 5/1999 Whetse (65) Prior Publication Data 5,936,876 A 8/1999 Sugasawara 5.991,898 A 11/1999 Rajski et al. US 2004/O187054 A1 Sep. 23, 2004 (Continued) Related U.S. Application Data Primary Examiner-David Ton (63) Continuation of application No. 09/275,726, filed on (74) Attorney, Agent, or Firm-Venable LLP; Jeffrey W. Mar. 24, 1999, now Pat. No. 6,687,865. Gluck (60) Provisional application No. 60/079,316, filed on Mar. (57) ABSTRACT 25, 1998. An integrated circuit is described which include a stored (51) Int. Cl............................................... G01R 31/28 program processor for test and debug of user-definable logic (52) U.S. Cl. ....................... 714/726; 714/727; 714/729 plus external interface between the test/debug circuits and (58) Field of Search ............................ 714/728, 30, 45, the component pins. The external interface may be via an 714/726,727, 729; 324/763 existing test interface, or a separate Serial or parallel port. Test and debug circuits may contain Scan Strings that may be (56) References Cited used to observe States in user-definable logic or be used to U.S. PATENT DOCUMENTS provide pseudo-random bit Sequences to user-definable logic. Test and debug circuits may also contain on-chip logic 3,761,695 A 9/1973 Eichelberger analyzer for capturing Sequences of logic States in user 3,783.254. A 1/1974 Eichelberger definable circuits. Test and debug circuits may be designed 3,784,907 A 1/1974 Eichelberger to observe States in user-definable circuits during the normal 4,495,629 A 1/1985 Zasio et al. System operation of Said user-definable circuits. 4,667,339 A 5/1987 Tubbs et al. 4,817,093 A * 3/1989 Jacobs et al. ............... 714/728 5,065,090 A 11/1991 Gheewala 6 Claims, 16 Drawing Sheets Scan chain 403 Preferred Embodiment of Block Scan Connector 7 US 6,964,001 B2 Page 2 U.S. PATENT DOCUMENTS 6,131,171 A 10/2000 Whetse 6,182.247 B1 1/2001. Herrmann et al. 6,003,107 A 12/1999 Ranson et al. 6,460,148 B2 10/2002 Veenstra et al. 6,003,142 A 12/1999 Mori 6,564,347 B1 5/2003 Mates 6,107.821 A 8/2000 Kelem et al. 6,125,464 A 9/2000 Jin * cited by examiner 7 7 7 7 U.S. Patent US 6,964,001 B2 pg9.1m81, IZSOQn9qL · 7 U.S. Patent Nov. 8, 2005 Sheet 5 of 16 US 6,964,001 B2 s C s o r CD H FW ?sºLZOI19d eJA mãi.{ om qg L 1s2 IAA u9dde ZOI (f | 7 U.S. Patent US 6,964,001 B2 7 U.S. Patent Nov. 8, 2005 Sheet 7 of 16 US 6,964,001 B2 pJoqIXJunao1ðdg)3l?0Oojfauq.8ndI? 7 U.S. Patent US 6,964,001 B2 7 7 7 U.S. Patent Nov. 8, 2005 Sheet 11 of 16 US 6,964,001 B2 00/ punOJ!) 9ounq p19¡nò [u0n/OJ,O ÇOL -2—80/–Z[eT•*punoJO Z9.4m81, 7 U.S. Patent US 6,964,001 B2 ZIL No. IL I 90.1m8?I 7 7 U.S. Patent Nov. 8, 2005 Sheet 14 of 16 US 6,964,001 B2 tygt| <s|ºJup?yjuno H. omnõi p6 7 U.S. Patent Nov. 8, 2005 Sheet 15 of 16 US 6,964,001 B2 VTW.JKeu?ounga 7 7 US 6,964,001 B2 1 2 ON-CHP SERVICE PROCESSOR However, the Size of integrated circuits has grown to the point where it has become inefficient and expensive to test CROSS-REFERENCE TO RELATED and debug ICS using Solely conventional Scan techniques. APPLICATIONS Furthermore, variations of the Serial Scan technique include the use of so-called "shadow registers." IC internal This application is a continuation of U.S. patent applica Signal States are captured in a duplicate copy, i.e., the tion Ser. No. 09/275,726 now U.S. Pat. No. 6,687,865, Shadow register, of certain internal registers. The shadow entitled, "On-Chip Service Processor," filed on Mar. 24, registers are interconnected by a dedicated internal Scan 1999, commonly-assigned, and incorporated by reference chain. A predetermined event can trigger a Snapshot of the herein in its entirety. That application, in turn, is entitled to internal State values in the Shadow registers and the dedi the priority of U.S. Provisional Patent Application No. cated Scan chain shifts the captured Signal State without 60/079,316, filed on Mar. 25, 1998. affecting the system operation of the IC. However, this approach has Several deficiencies. First, only a single Snap BACKGROUND OF THE INVENTION shot can be captured and shifted out with each trigger event. 15 This greatly hamperS debugging the IC Since there is not The present invention is related to the testing and debug much visibility of the system activity around a point of ging of electronic Systems, and, in particular, to on-chip interest identified by the trigger event. Secondly, the Snap circuits for the test and diagnosis of problems in an inte shots can be taken only of those signals in registers which grated circuit. have a shadow register counterpart. Since a shadow register Heretofore, logic analyzer probes have often been used in effectively doubles the circuitry for the register, this the testing and debugging of electronic Systems. The logic approach is very costly to implement on a large Scale in the analyzer probes were coupled to the external pins of com IC. ponents of a digital System in order to capture the Sequence Another test and debug design for ICS is found in a of Signals after a predefined event (or time Stamp) occurs. standard, the IEEE 1149.1 Test Access Port and Boundary The captured signals can then be examined to Verify correct 25 Scan Architecture, which prescribes a test controller which System behavior or, alternatively, to identify the time and the responds to a set of predetermined instructions and an nature of erroneous behavior in the System. instruction register which holds the present instruction Furthermore, in the designs of large electronic Systems, which the controller executes. Each instruction is first Separate consoles, or Service processors, have often been loaded into the instruction register from a Source outside the incorporated into the circuit boards of the System. These IC and then that instruction is executed by the controller. Separate processors have a number of useful functions, While having Some advantages of Versatility and Speed, the including the control of scan Strings in the system; the standard still binds test and debug procedures to the world origination of diagnostic Signal probes to run on the System, external to the IC and thus, limits its performance. and So forth. The Service processors also have diagnostic and The present invention recognizes that while the advances Scan debug features, including access to the internal registers 35 in IC technology have helped to create the problems of and memory within the System. The Service processors have testing and debugging an IC, the advances also point the way also been used to bring-up the main System during its power toward Solving these problems. In accordance with the up phase. All of these functions have been useful to System present invention, Special on-chip circuits are used to designers for the design, test and debugging of electronic observe the internal workings of an IC. These circuits Systems. 40 operate at internal IC clock rates So that the limitations of the On the other hand, more and more digital Systems, or parts frequency of Signals at the IC input and output (I/O) bound of digital Systems, are being integrated in a Single compo ary are avoided. Many more points in the IC System are nent. The resulting complexity and lack of observability of accessed than is feasible with conventional external test and an integrated circuit poses Serious problems for the test, debug processors. Thus the present invention offers advan debug and bring-up stages of the integrated circuit (IC). For 45 tages which exceed the Straight-forward Savings in chip example, observation at the IC component pins of the Space due to miniaturization. Additionally, the present behavior of an IC system is increasingly difficult. The IC invention reduces the amount of test logic which might have component pins may be very far (in terms of logic hierarchy) been required elsewhere on the chip. from the actual points of interest. The extremely high The present invention also permits the coupling of probes frequency of digital IC operations and the frequency filtering 50 to internal IC points. The points may be selected from a effects of the large capacitance of the external logic analyzer larger number of internal points that may be observed with probes, often prevents a logic analyzer from capturing an external logic analyzer. Besides the greater observability Signals reliably and precisely. There is always an uncertainty of the internal operations of the IC, the present invention regarding the accuracy of Signals captured by an external also improves the accuracy of the observations, as compared logic analyzer compared to the actual signals values within 55 to an external logic analyzer. the IC. To address the problems of the testing of integrated SUMMARY OF THE INVENTION circuits, special features are being included in many IC designs. For example, one Standard technique is "Scan' To achieve these ends, the present invention provides for whereby, certain internal flip-flops, which are connected to 60 integrated circuit logic blocks, a control unit, a memory various Selected points of the IC, are also connected to form asSociated with the control unit and a plurality of Scan lines. a Serial shift register when the IC is configured in a test The memory holds instructions for the control unit to mode. Straightforward Serial shift (i.e., Scan) operations are perform test and debug operations of the logic blockS. The utilized to load the flip-flops with desired values, or to read Scan lines are responsive to the control unit for loading test out their present values reflective of the logic States of the 65 Signals for the logic blocks and retrieving test Signal results Selective IC points. Such ICS require Special features to reset from the logic blockS. The test Signals and the test Signal the flip-flops (i.e., bring the IC to a known starting State). results are Stored in the memory So that the loading and 7 US 6,964,001 B2 3 4 retrieving operations are performed at one or more clock FIG. 7 is a circuit which generates ground-bounce detec Signal rates internal to the integrated circuit. The integrated tion probe Signals for range probes, circuit also has a plurality of probe lines which are respon FIG. 8 is a block diagram of a Built In Self-Test (BIST) Sive to the control unit for carrying System operation signals engine of the FIG. 2 SPU; at predetermined probe points of the logic blocks. The FIG. 9a is a block diagram of an input aligner portion of System operation Signals are also Stored in the memory So Analysis Engine of the FIG. 2 SPU; FIG.9b is a detail of the that the System operation signals are retrieved at one or more FIG. 9a Analysis Engine's input aligner; FIG. 9c is a block clock signal rates internal to the integrated circuit. diagram of the Analysis Engine's memory addressing Struc The present invention also provides for an integrated ture, FIG. 9d is a block diagram of the trigger logic portion circuit which has an interface for coupling to an external of the Analysis Engine; and diagnostic processor, a unit responsive to instructions from FIG. 10 is a block diagram of another embodiment of the the external diagnostics processor, a plurality of probe lines Analysis Engine's memory addressing Structure, coupled to the unit, and a memory coupled to the unit and FIG. 11 shows a probe string connection of probe points to the interface. In response to the unit, the probe lines carry to the buffer memory using logic analyzer channels that are Sequential of Sets of System operation Signals at predeter 15 implemented with probe storage elements (PSE); mined probe points of the integrated circuit and the System FIG. 12 shows an alternative probe string connection with operation Signals are Stored in the memory at one or more improved multiplexed PSEs which combine probe selection clock Signal rates internal to the integrated circuit. The and data capture functions, and System operation Signals are retrieved from the memory FIG. 13 is a block diagram of the improved PSE of FIG. through the interface to the external diagnostic processor at 12. one or more clock signal rates external to the integrated circuit. This allows the external diagnostics processor to DESCRIPTION OF THE SPECIFIC process the captured System operation signals. EMBODIMENTS The present invention further provides for a method of operating an integrated circuit which has logic blocks, a 25 General Organization of the Present Invention control unit, a memory and a plurality of Scan lines of the logic blocks. The memory is loaded with test Signals and In accordance with the present invention, a Service Pro instructions for the control unit and the Scanlines responsive cessor Unit (SPU) is incorporated within an integrated to the control unit are loaded with the test Signals for the circuit. Besides addressing the problems of testing and logic blocks at one or more clock signal rates internal to the debugging the IC, the availability of a programmable unit, integrated circuit. The logic blocks are then operated at one such as the SPU, which may load or unload the state or more clock signal rates internal to the integrated circuit variables into and from the user-definable logic in an IC, and the resulting test signal results are retrieved from the greatly simplifies the problem of resetting the IC and observ logic blocks along the Scan lines at one or more clock signal ing its current state. The SPU is implemented in the form of rates internal to the integrated circuit. The test Signal results 35 a basic Stored-program control unit, Such as a microproces are Stored in the memory at one or more clock signal rates Sor, with a predefined instruction Set, a number of extended internal to the integrated circuit; and the Stored test results function units (EFUs), program, data, and Scratch pad Signals are processed in the control unit responsive to the memories, plus an input/output circuit for loading and Stored instructions in the memory to perform test and debug unloading the SPU memories with data/programs from the operations of the logic blockS. 40 outside world. This allows the SPU to be programmed to execute a control program which interacts with the various BRIEF DESCRIPTION OF THE DRAWINGS extended functional units to control various test and debug related activities on the IC. FIG. 1a shows a high-level diagram of an exemplary large Each EFU is designed to control a specific test or debug and complex integrated circuit; FIG. 1b shows the FIG. 1 a 45 feature and the EFU provides the control unit a general, integrated circuit with a Service Processor Unit (SPU), programmable access to that feature. For example, one EFU according to one embodiment of the present invention; may be designed to control the execution of Serial shift FIG. 2 illustrates one embodiment for the architecture for operations along Some or all of the internal Scan chains of the SPU of FIG. 1b, the IC. The other EFUs may be enabled to interact with the 50 Scan chains, Such as a predetermined algorithm to provide a FIG. 3a illustrates the coupling between test wrappers, Built-In Self-Test (BIST) for an embedded Random Access Scan Strings, probe Strings and range probes to a test bus, Memory (RAM) block. The existing scan chains load and FIG. 3b is a circuit diagram of a test bus connector of FIG. unload the BIST patterns and results to/from the RAM 3a; FIG. 3c is an exemplary connection of multiple test bus block. The EFUs provide the control unit with a straight connectors, 55 forward, programmable means for controlling the functions FIG. 4a is a circuit diagram of a block input/output of the EFU such that knowledge of low level details of the connector for test wrapperS for observing test points outside Scan or BIST functions become unnecessary. a block along a boundary-Scan chain (for example, IEEE With its program and data memories, the SPU acts 1149.1 standard Test Access Port and Boundary Scan Archi autonomously once its program memory has been loaded tecture); FIG. 4b is a circuit diagram of a block Scan 60 with the desired instruction sequence. The SPU's program connector for Scan Strings for observing test points inside a memory may be loaded with the desired program instruc block along a Scan chain; tions through the SPUs interface to the external environ FIG. 5 is a circuit diagram of a scan flip-flop in the FIG. ment. Alternatively, the instructions may be Stored in an 4b circuit diagram; on-chip Read Only Memory (ROM) that has been provided FIG. 6a is a circuit which generates an out-of-range 65 to work as the SPU's program memory. detection probe signals for range probes; FIGS. 6b and 6c In one embodiment of the present invention, an EFU are the transistor-level circuits of inverters in FIG. 6a, carries out certain functions of a logic analyzer. A logic 7 US 6,964,001 B2 S 6 analyzer captures and Stores signal State values in a digital nals to be loaded into these probe circuits. The Scan chain System following the occurrence of a pre-defined event. The also carries other control Signals to be loaded into a trigger logic analyzer then analyzes the captured data and displayS circuit which starts and stops the data capture operations. the results for perusal. With the present invention, the Once the desired data has been captured into an on-chip capture and Storage functions are incorporated into the IC. RAM, the data is transported outside the IC for Subsequent The EFU which implements these functions captures and analysis and display. Stores not a single Snapshot but a sequence (i.e., history) of Implementations of the Present Invention Signal values using logic probes which are Selectively AS a starting point, FIG. 1a is a diagram of an exemplary coupled to desired points in the IC logic circuits. The logic integrated circuit. The IC 100 is complex having a host analyzer EFU is configurable to Select the location, number processor connected by a System bus to various circuit and Sequential depth of Signal channels from a predeter mined Set of choices. Thus, each logic analyzer channel may blocks, including a third party core and other blockS adapted be selectively coupled to more than one predetermined to the application of the IC. The IC also has a peripheral bus capture point by programming the control unit and hence, which is connected to the system bus by a bridge. The the EFU. A solution is provided for capturing the history of 15 peripheral bus is connected to other functional blocks, Such Signal values at the internal points of the IC without having as a user-developed core and So on. to provide each one of these points with their shadow A preferred embodiment of the present invention to test register counterpart. The captured data are Stored in an and debug the complex IC of FIG. 1a is shown in FIG. 1b. on-chip Random Access Memory (RAM). Transportation of Added to the IC 100 is a Service Processor Unit (SPU) 101 the captured data out of the IC is performed later for analysis which is coupled to the IC system bus 105 and an added test by an external computer which can reformat and display as bus 104. Connected to the test bus 104 are test wrappers 102 required for diagnostics. The present invention has the which provide test communication channels into Selected benefit of enhanced data accuracy with minimal cost over blocks 106. More details of the test bus 104 and test head by Separating the Signal capture/storage function of a wrappers 102 are provided below. The SPU 101 provides a logic analyzer into the IC. 25 connection for an external diagnostics console 103 to view Two different types of logic probes may be used with the and test the internal workings of the IC 100. logic analyzer EFU. One type of logic probe, termed the As shown in FIG. 2, the SPU 101 has several extended digital probe, captures Sequences of digital signals from function units (EFUs), including a control unit, Such as a internal points of the IC. Digital signal values flow from the microprocessor 211, a buffer memory unit 218, an analysis internal capture point to a logic analyzer channel through the engine 215, a Scan control unit 222, an interrupt handler 221, digital probe. In its Simplest form each digital probe has at which is further connected to a range check unit 220, a least two input ports, a selection means and an output port System bus interface 214, a test bus interface 213 and a that is directly coupled to a logic analyzer channel. Digital built-in self test (BIST) engine 212, which are all intercon probes may also be constructed from a Series of internal nected by a processor bus 219. The various EPUs are Storage elements (i.e., flip-flops or latches) to form a pipeline 35 coupled to the processor bus 219 in any desired combination to move the data from the capture points towards the logic and order. To provide communication between the external analyzer channels. In this case, the movement of the data world and the SPU 101, the bus 219 is also connected to a along the digital probe flip-flops is Synchronized with an serial input/output (SIO) interface 210, a parallel input/ on-chip clock signal. Since the clock frequency also defines output interface (PIO) 216, and a test access port (TAP) 217. the maximum capture rate, the particular clock signal is 40 For example, the coupling between the IC 100 and the Selected based on the maximum desired capture rate. The external diagnostics console 103, typically implemented digital probes used for the logic analyzer EFU operate with using another computer, uses the TAP217, the SIO interface the same electrical and timing characteristics of the native 210 or the PIO interface 216. Signals of the IC. The digital probes are implemented in the Analog probe lines 201 are connected to the range check Same technology, with the same functional logic circuitry, 45 unit 220 which processes their values to detect out-of-range and under the Same clock timing, as the rest of the IC. conditions which are then Signaled to the interrupt handler Signals are therefor captured and propagated along the 221. The interrupt handler 221 also receives signals from digital probes in exactly the same way as they are operated trigger event lines 204 directly or from test bus 104 by way upon by the functional circuitry of the IC. This assures much of test bus connections 203 to the interrupt handler 221. The greater accuracy of Signal States captured by the digital 50 signals on the trigger event lines 204 or test connections 203 probes. In contrast, logic probes used with an external logic are used to capture Signal State values when predetermined analyzer must use trigger events and Signal values that are (i.e., triggering) events occur. The interrupt handler 221 Visible external to the IC. The captured signal values may passes the captured values to the analysis engine 215. The differ significantly from the original (internal) values. test bus 104 is further coupled to test wrappers 102, which The logic analyzer EFU may use a Second type of logic 55 are individually wrapped around a number of predetermined probe, termed an analog probe, which captures Signal events blocks 106 on the IC 100. Each test wrapper 102 accesses representing the detection of Signal integrity conditions, the input and output signals of a block 106. The test bus 104 Such as ground bounce. Desired signal observation points is also connected to Scan String lines 403, which are con are coupled to analog detection circuits which produce nected to internal elements of a block 106. digital signals when particular Signal conditions are 60 As shown in FIG. 3a, the test bus 104 forms a unidirec detected. The analog probe records these digital Signal States tional loop with test bus connectors 401 selectively trans in the logic analyzer EFU. ferring data between the test bus 104 and a test wrapper 102. The benefits of the logic analyzer EFU are such that for The test bus 104 is made up of multiple bit lines, where the certain ICs, only the EFU portion of the SPU is implemented number of the bits is determined by the requirements of the on the IC. In this alternate embodiment of the present 65 test system. Through test bus connector 401, the test bus 104 invention, the digital and analog probes are Selectively is Selectively connected to test wrapperS 102, Scan String enabled by a Scan-chain which allows Specific control Sig lines 403, probe string lines 402 and trigger lines 204. 7 US 6,964,001 B2 7 8 A test bus connector 401 which handles a one bit con selects whether the functional signal at data-in terminal 302 nection between the test bus 104 and a test wrapper 102 is or the signal held in the scan flip-flop 301 is passed onto the illustrated in FIG. 3b. A first multiplexer 421 has one of its data-out terminal 307. When the control signal of the line input terminals connected to one of the lines of the test bus 300 Signal is not-asserted, i.e., normal mode, there is normal 104. The other input terminal is connected to a signal line of 5 operational signal flow between the data-in terminal 302 and the test wrapper 102. The output terminal of the multiplexer the data-out terminal 307. On the other hand, when the 421 is connected to an input terminal of a flip-flop 426 and control signal on the line 300 is in asserted State, i.e., test to an input terminal of a Second multiplexer 422, which has mode, the current state of the scan flip-flop 301 is passed a Second input terminal connected to the output terminal of onto the data-out terminal 307; the data-in terminal 302 and the flip-flop 426. The output terminal of the flip-flop 426 is the data-out terminal 307 are isolated from one another. The also connected to the line of the test wrapper 102, which is state stored in the scan flip-flop 301 is also controls whether also in the form of a unidirectional loop. The multiplexer the signal at the data-in terminal 302 or the probe-in terminal 421 selects either the data from the test bus 104 or the test 303 is passed onto the probe-out terminal 305. In this wrapper 102; the second multiplexer 422 selects between the manner, data from another probe point which is connected to data selected by the first multiplexer 431 or the data captured 15 the probe-in terminal 303 are selectively passed onto the in the flip-flop 426 to place back onto the test bus 104. These probe-out terminal 305. The signal state in the scan flip-flop Selections are done under the control of SPU 101. The test 301 value is controlled and observed using regular Scan bus connector 401 is also be used for coupling a trigger line operations of the test wrapper 102 through the Scan-in and 204, probe string line 402 or scan string line 403 to a test bus Scan-out terminals 304 and 306. Of course, if observation of 104 by connecting the desired signal line in place of the line an input or output signal of the block 106 by a probe string of the test wrapper 102 port as shown in FIG. 3b. 402 is not required, the multiplexer 309 can be eliminated FIG. 3C shows an embodiment of coupling a trigger line from the circuit 310. 204, probe string 402, test wrapper 102 and scan string line A scan string 403 is formed by serially connecting block 403 to three lines of the test bus 104. Other possible Scan connector circuits 320. One Such circuit 320, which configurations for the couplings include coupling the test 25 couples an internal element of a block 106 to the Scan String wrapper 102 and scan string 403 onto separate lines of the 403, is illustrated in FIG. 4b. The connector circuit 320 has test bus 104. a scan-in terminal 314 and a scan-out terminal 316. The A test wrapper 102 is formed by serially connecting block Scan-in terminal 314 of one connector circuit is connected to I/O connector circuits 310. One Such circuit 310, which the Scan-out terminal 316 of another connector circuit 320 to couples an input or output Signal of a block 106 to the test form a serial scan string 403. The block scan connector wrapper 102, is illustrated in FIG. 4a. The connector circuit circuit 320 also has a data-in terminal 312 and a data-out 310 has a scan-in terminal 304 and a scan-out terminal 306. terminal 317 which provide an interstitial connection The scan-in terminal 304 of one circuit 301 is connected to between internal elements of the block 106. In the normal the scan-out terminal 306 of another circuit 301 to form the operation of the IC 100, the connector circuit 320 is a simple serial chain of a test wrapper 102. The connector circuit 310 35 path between the internal elements in the block 106. The also has a data-in terminal 302 and a data-out terminal 307 connector circuit 320 also has a probe-in terminal 313 and which provide an interstitial connection between a block 106 a probe-out terminal 315 which provide a path for probe and the rest of the IC 100. In the normal operation of the IC, signals from selected portions of the block 106 through the the connector circuit 310 provides a simple path between the connector circuit 320 to observe operations in the block 106. block 106 and the rest of the IC 100. If the connector circuit 40 The block scan connector circuit 320 has a scan flip-flop 310 is to provide an input signal to the block 106 during test 311 and a multiplexer 319. The data-in terminal 312 and the operations, the data out terminal 307 is connected to the scan-in terminal 314 form the inputs to the scan flip-flop block 106 and the data in terminal is connected to the rest of 311. The output from the flip-flip 311 include the scan out the IC 100. If the block I/O connector circuit 310 is to terminal 316 and the data-out terminal 317. The data-in receive an output signal from the block 106 during test 45 terminal 302 is also connected to one input to the multi operations, the data-out terminal 307 is connected to the rest plexer 319. The probe-in terminal 313 forms a second input of the IC 100 and the data-in terminal is connected to the to the multiplexer 319 whose output forms the probe-out block 106. The connector circuit 310 also has a probe-in terminal 315. A special circuit is used for the scan flip-flop terminal 303 and a probe-out terminal 305 which provide a 311 (and the flip-flop 301 of FIG. 4a). The circuit, which is path for probe Signals from Selected portions of the block 50 shown in FIG. 5 and is found in previous IC scan designs, 106 through the connector circuit 310 to observe operations has separate Scan-Slave and data-Slave Sections. The Sepa in the block 106. ration allows a State signal which has been Scanned into the The elements of the connector circuit 310 include a scan scan flip-flop 311 to remain unaffected by functional clock flip-flop 301 and two multiplexers 308 and 309. The data-in pulses that cause the flip-flop 311 to capture signals on the terminal 302 and the scan-in terminal 304 form the inputs to 55 data in terminal 312 So that they appear in the data-Slave the flip-flop 301. The output from the flip-flip 301 include Section and on the data out terminal 317. The connector the scan out terminal 306 and one input to the multiplexer circuit 320 acts as a simple conduit for Signals within the 308 having an output which forms the data-out terminal 307. block 106. At the same time, the previously scanned-in The second input to the multiplexer 308 is connected to the Signal, which appears in the Scan-Slave Section, Selects data-in terminal 302, which is also connected to one input to 60 whether signals at the data in terminal 312 or the output from the multiplexer 309. The probe-in terminal 303 forms a another probe point which has been connected to the probe second input to the multiplexer 309 whose output forms the in terminal 313 is to be passed onto the probe-out terminal probe-out terminal 305. The control input of the multiplexer 315. A probe string 402 is created. Of course, if an internal 309 is the output of the scan flip-flop 301 (and is connected scan string 403 need not be connected to a probe string 402, to one input of the multiplexer 308). The control input of the 65 the multiplexer 319 can be eliminated from the circuit 320. multiplexer 308 is a test control line 300 from the control A probe string 402 is formed by serially connecting the unit 311 of the SPU 101. The control signal on the line 300 probe-in terminal of a connector circuit 310 and 320 to the 7 US 6,964,001 B2 10 probe-out terminal of another connector circuit 310 and 320. of the multiplexer 715 is an input to the LSFR 714. The The probe string 402 typically has a set of selectively mask shift register 712 identifies the bit positions whose connected probe points. However, only one probe point values are Selected from predetermined bit patterns in mask along each probe String 402 may be actively probed at any shift register 713 versus the bit positions which receive the given time. Thus the IC designer Selects the probe points pseudo-random values generated by the LFSR 714. The which are to be connected along the same probe String 402 output of the multiplexer 715 is a combination of built-in and determines the total number of probe strings 402 that are Self-test and functional Scan vectors. These features are to be connected to the individual bits of the test bus 104. useful because random vectors work well only when the This structure allows the IC designer great flexibility to controls allow the random vectors to exercise most of the IC optimize the number of test bus 104 lines with respect to the Section under test. If there are more than a few control lines, number of simultaneously observable probe points in the IC. the probability of properly exercising the logic under test The probes described above are digital probes. Two with random vectors is very low. These features also allow analog probes are illustrated in FIGS. 6a, 6b, 6c and 7. The the SPU 101 to generate regularly repeating patterns; for range check unit 220 receives inputs from the analog probes example, periodic patterns that may be useful in a memory that comprise signals on a threshold check line 600 and a 15 test may be generated by the SPU 101 that may output the ground bounce line 700. The unit transmits these signals to data to the Section of logic under test via the test buS or the the SPU 101. FIGS. 6a, 6b and 6c show the circuit which System bus, whichever has been provided with a connection generate the signal for the threshold check line 600. The to the SPU 101. circuit is used for detecting extended intermediate Voltage Another EFU of the SPU 101 is the analysis engine 215. levels. Such Voltage levels are most likely to occur on an FIG. 9a shows an embodiment of the analysis engine 215 on-chip bus which is in contention among multiple circuit which, under the control of the microprocessor 211, captures drivers. The analog probe has two inverters 601 and 602, logic signals from the test bus 104. This is achieved by first which are both coupled to an Exclusive-NOR logic gate setting either the scan flip-flops 301 of the block I/O circuit. FIG. 6b is a transistor diagram depicting the low connector circuits 310 (FIG. 4a) or the scan flip-flops 311 of threshold inverter 601, and FIG. 6c is a transistor diagram 25 the block scan connector circuit 320 (FIG. 4b) so that a depicting the high threshold inverter 602. These inverters boundary connection or an internal point connection of the 601 and 602 exhibit switching properties characteristic of a target block 106 is selected for probing, respectively. Next, very low internal Voltage, and a very high internal Voltage all flip-flops along the same probe String 402 are pro device, respectively. Normally, the circuit in FIG. 6a has a grammed (by the SPU 101) so that only signals from the logic one (1) output level, but during transitions of the input Selected probe point are allowed to flow through the probe signal, the outputs of inverters 601 and 602 may remain in string 402 and arrive at the test bus connector 401. The opposite states for a period sufficient to cause the circuit to multiplexer 421 and the multiplexer 422 in the test bus go to a logic Zero (0) output level before returning to the connector 401 (FIG. 3a) are controlled by the SPU 101 so logic one (1) output level. This negative pulse can be that the Signals on the probe String 402 are passed along to captured by the SPU 101. 35 the test bus 104. Finally, all remaining test bus connector FIG. 7 shows a Schematic diagram of a ground bounce circuits 401 along the same bit line of the test bus 104 are detector circuit which generates the Signals for a ground controlled by the SPU 101 so that they pass the probesignals bounce line 700. In this circuit, a quiet (and true) ground along test bus 104. This allows the selected probe signal to terminal 701 is connected to an N-channel transistor 702, arrive at the analysis engine 215 where it is captured for which gate is driven by a local ground connection terminal 40 Subsequent off-line analysis. The input terminals of a plu 703. A periodic clock on a Reset terminal 706, which is rality of flip-flops 805, one for each bit line of the test bus controlled from the range check 220, clears a pair of NAND 104, form the input port 802 of the analysis engine 215. A gates configured as a SR latch 704, and charges a capacitor digital phase locked loop (PLL) 802 has selectable clock 705 having one terminal connected to the Set input of the SR outputs 803 to each flip-flop 805 to tune when the data from latch. The second terminal of the capacitor 705 is connected 45 each probe point is to be captured. The output terminal of to the quiet ground terminal 701. The N-channel transistor each flip-flop 905 is connected to the input terminal of a 702 which is gated by the local ground discharges the Set variable First-In-First-Out shift register (FIFO) 804. line of the SR latch 704, which flips the state of the SR latch FIG. 9b shows the circuit details of each variable First 704 if the local ground falls above threshold. For example, In-First-Out shift register (FIFO)804, each having a number a ground Spike on the local ground may drive the local 50 of Serially-connected register Stages 812. Each register Stage ground below threshold. The frequency and duty cycle of the 812 has a multiplexer which, under control of a decoder 811, Reset Signal determines the magnitude and duration of a Selects between the Signal held in a flip-flop of that Stage or ground Spike on the local ground to trigger the probe. A the incoming Signal to the Stage to place on the Stage's variety of frequencies and duty cycles are created by the output terminal. The shift depth of each variable FIFO 804 range check 220 to determine the Severity of ground Spikes. 55 is programmable by the SPU 101 by setting a count register When the probe is triggered, the probe produces a negative 810 for each bit feeding the analysis engine 215. The value (0) value until reset by the Reset signal on the terminal 706. in the count register 810 is decoded by the decoder 811. The Returning to the components of the SPU 101, FIG. 8 is a result controls the number of register Stages 812 which are preferred embodiment of the BIST engine 212. A polyno bypassed. This compensates for the path delay differences mial register 711 identifies the bits in a linear feedback shift 60 among the different probe points by realigning capture times register (LSFR) 714 which are used to form an Exclusive of Signals captured in the analysis engine 215. OR (XOR) function which generates pseudo-random values. The analysis engine 215 also has trigger logic which The polynomial register 711 is set by the microprocessor controls the capture of data. FIGS. 9c and 9d show sections 211, which also initializes contents of the LSFR 714. The of the trigger logic, a programmable circuit which detects output of the LSFR 717 is connected to the inputs of a 65 one or more events to Stop the analysis engine 215 from multiplexer 715 which also receives the outputs of a mask capturing new data. The data that has been captured up to shift register 712 and a pattern shift register 713. The output that point is preserved in the buffer memory 218 of the SPU 7 US 6,964,001 B2 11 12 101. The buffer memory 218 resides in the same address multiple occurrences of trigger conditions. The buffer space as the RAM used by the SPU 101 but may be mapped memory 218 is utilized more efficiently as the storage of to use high memory Space in order to prevent interference unwanted cycles of data between the trigger points is not with the instructions and data Stored in low memory Space. required. It is also possible to program the trigger logic So When the analysis-engine 215 collects data, it may be it uses an externally generated trigger condition 902 in place allowed to write over old data, keeping only as many of an internally programmed event. most-recent cycles of data as the buffer memory 218 can Program instructions and initial data values for executing hold. The size of the buffer memory 218 for the analysis programs to implement the functions of the SPU 101 are engine 215 is determined by the designer of the IC. loaded from the diagnostics console 103 (see FIG. 1b) into The trigger logic has a start address counter 820 and a stop the buffer memory 218 of the SPU 101. Some of these counter 821, which are shown in FIG.9c. These counters are programs may access the system bus 105 or the test bus 104. loaded by the microprocessor 211. The trigger circuit also A program can control which test wrapper 102 is accessed has an address counter 822 which is designed to overflow at by using the test bus interface 213 in order to set control the highest memory address of the buffer memory 218. At signals on the test bus 104. This allows the SPU 101 to read that point the Start address is reloaded with the beginning 15 data from a test wrapper 102 via the test bus 104 into the address of the high memory Space which is reserved for the buffer memory 218 and then send said data out to the buffer 218. This converts a random access memory into a diagnostic console 103. Typically, a separate program FIFO register. The stop counter 821 decrements when a executed on the diagnostic console 103 displays this infor latched trigger Signal line 824 becomes Set. Subsequently mation in a human readable format as may be appropriate for the analysis engine 215 collects data into the buffer memory the given application. 218 from the variable FIFOs 804 for as many cycles as Programs executed by the SPU 101 can also read data defined by the value loaded into the stop counter 821. The from the diagnostics console 103 via the SIO interface 210 System IC designer uses the buffer memory size and the or TAP interface 217, as shown in FIG.2b, and write data out value in the Stop counter 821 as two parameters to control to individual scan flip-flops on the test wrappers 102 via the the amount of data collected before and after an event has 25 test buS 104. Significant processing, for example, expansion, been detected. compaction, or intermediate Storage of data can be done by Also part of the trigger logic is a circuit which generates the SPU 101 utilizing the buffer memory 218. In other the triggering Signals on the trigger Signal line 824. AS embodiments, control functions may be Supplied directly shown in FIG. 9d, the generating circuit is structured to form from the TAP interface 217 or SIO interface 210 to the Boolean AND-OR logic 831 out of individually selectable analysis engine 215 or BIST engine 212, via the processor terms 832. The terms 832 are fed from a polarity program bus 219 without involving the microprocessor 211. The SPU ming logic circuit 833 that accepts individual trigger vari 101 may be coupled to either the system bus 205, or a ables, Probe 1 through Probe N. In addition, the true or the Separate test buS 104, or both. The coupling to the diagnos complemented value for the output function can be Selected tics console 103 may be via the TAP interface 217 or the SIO through a final level circuit 830. In one embodiment (shown 35 interface 210. The test bus 104 may be coupled to one or in FIG. 9d), the result is also shifted into three successive more test wrappers 102. flip-flops 834. Each of the flip-flops 834 drives one input of Another embodiment of the invention is defined in which each of a plurality of multiplexers 835. The other inputs of the SPU 101 does not include an embedded microprocessor the multiplexers 835 are set to a logic one (1) level. Each 211. In this case, the analysis engine 215 and the BIST multiplexer 835 is individually controlled through program 40 engine 212 can access the buffer memory 218 and System mable bits and the multiplexer outputs are logically ANDed bus interface 214 directly, following instructions received together to form a signal, Ti, which represents the presence from the external diagnostics console 103. In this case, the of the trigger condition over four consecutive clock periods. loading of the configuration information and transfer of data The output from the AND gate 836 is passed to an AND gate to and from the analysis engine 215 is controlled using 837 with inputs from the corresponding AND gates 836 of 45 hardwired control Signals. In this embodiment, the analysis duplicate circuits that produce T0, T1, through TIn engine 215 is implemented in the form of an on-chip logic signals. The output of AND gate 837 is stored in a latch 838 analyzer (OLA) which captures sequential Snapshots of Sets to form the latched trigger signal on the line 824. Once the of Signals. The Selected Signals form the digital probes 202. Signal is Set, the latched trigger Signal maintains its value The Selections are achieved by coupling the Signals for until it is reset through reprogramming by the microproces 50 digital probes 202 to the channels of the analysis engine 215 Sor 211. In other embodiments, there may be more or fewer and turning-on enabling circuits, if provided, to allow the latches, and additional logic to make adjustments to the Signals on the digital probes 202 value to be captured onto phases (i.e., the relative clock cycle when signal is received) channels of the logic analyzer 215. As shown in FIG. 11, the of the individual signals. channels of the logic analyzer 215 are formed from probe Another embodiment of the trigger logic is shown in FIG. 55 storage elements (PSE) 1000 to form a distributed serial 10. This embodiment provides for the capability of reversing shift register which acts as a pipeline to move data captured the data capturing function of the analysis engine 215 from at a probe point towards the end of the logic analyzer continually capturing new data until the trigger is detected, channel where the data are stored in buffer memory 218. to not capturing any data until a trigger is received. In the Each channel of the analysis engine 215 contains Zero or latter case, each time a trigger Signal on the line 824 is 60 more number of PSEs 1000 which are clocked by a common received, the analysis engine 215 captures new data for a periodic clock Signal labeled "Cf. on a clock signal line preprogrammed number of cycles and then Stops until the 1001. The clock signal is chosen (at design time) from next latched signal on the line 824 is received. To enable this among the fastest frequency of clock Signals which are used mode of operation, the trigger circuit shown in FIG. 10 in generating Source Signals to be captured by the probes. causes the previous trigger condition to be cleared So that it 65 This way all signals captured on the analysis engine 215 may be recognized again. This mode is very useful Since it channels arrive at the end of the channels after a fixed, enables the capture of Signals around (i.e., before and after) predetermined number of clock cycles So that their cycle 7 US 6,964,001 B2 13 14 relationship to one another is preserved, regardless of the programmed, the Scan mode signal on control line 1103 length (i.e., number of bits) of the individual channels of signal is set to and maintained at logic 0 until the PSE 1000 analysis engine 215. is programmed with a new value. When the Scan mode Subsequently, after the captured data has been transported signal is set to logic 0, the PSE 1000 performs its normal to the external diagnostics console 103, Software processes data capture function using the clock signal Cf on the line use the number of PSEs 1000 on each channel of the analysis 1001. The Cf clock signals are passed by the multiplexer engine 215 to align the data with respect to one another. The 1109 to the latch 1106 by a clock signal 1110. The latch 1106 lengths (i.e. number of bits) of the Serial shift registers on the captures the signals from the latch 1105 and the multiplexer individual channels of the analysis engine 215 are deter 1108 at the Cf clock rate and passes the signals out to the Q mined at design time So that Signal delays due to physical output terminal. The multiplexed-PSEs shown in FIGS. 12 distances among the PSEs 1000 are sufficiently short to and 13 build cost efficient logic analyzer channels. allow data to be shifted between consecutive bits of the shift Once enabled, the analysis engine 215 captures new registers in a single clock cycle. If necessary, the number of values first into the flip-flops along the OLA channels and Stages of the shift registers may be increased to Satisfy this Subsequently into the buffer memory 218 using trigger condition. Each channel of the analysis engine 215 is 15 Signals that have been pre-programmed and implemented as coupled to a different data input port of the buffer memory shown in FIGS. 9c, 9d and 10. 218. The collective data applied to the ports of the buffer In one mode of operation of the IC 100 shown in FIG.1b, memory 218 is written to an address in memory which is the human engineer may use the diagnostics console 103 to identified by a common address register 822 that advances initialize both of the system logic and the SPU 101. In this under control of the periodic clock signal "Cf. on the line manner, the SPU 101 may be programmed to perform logic 1001. analyzer functions and Specific probe points may be enabled FIG. 12 shows a preferred embodiment of a channel of the So that a history of data values appearing at the Selected OLA215 which uses multiplexed PSEs 1000 to combine the probe points can be captured by SPU 101. Additionally, the Selection of probe points and pipelining captured data into a trigger logic shown in FIGS. 9 and 10 may be programmed Single, efficient design. This enables the coupling one PSE 25 to Select a desired trigger event in order to Stop the data 1000 to two probe points or another PSE 1000. Scan capture operations. Next, the diagnostics console 103 invoke operations shift a control signal into the PSE 1000 to the IC 100 to execute its normal system operations. If and program itself to Select one or the other of its input ports. when the Selected trigger event is detected and the analysis The details of a multiplexed PSE are shown in FIG. 13. engine 215 has captured the required data, the diagnostics The PSE 1000, illustrated by a dotted line, is connected to console 103 instructs the SPU 101 to transfer the captured a multiplexer 1108 which has two input terminals connected data values out of the IC 100 and into the diagnostics to two input probe paths, P1 and P2, for the logic analyzer console 103 where the data may be formatted and presented channels. Besides the probe clock signal line 1001, which for analysis and interpretation. The diagnostics console 103 carries the Cf signal, the PSE 1000 is connected to a first and the SPU 101 can constrain some of the signals on one Scan clock Signal line 1101, which carries an A clk signal, 35 or more test wrappers 102 in order to affect the behavior of a Second Scan clock signal line 1102, which carries a B clk the IC 100 and perform logic analysis under these condi Signal, and a Scan control line 1103, which carries a tions. For example, this approach may be useful to deter Scan mode signal. The PSE 1000 has three latches 1105, mine how the overall behavior of the IC 100 is affected when 1106 and 1107. The output terminal of the latch 1105 is Some of the functionality of any one of the blocks 106 is connected to one input terminal of the latch 1106 and to one 40 disabled. input terminal of the latch 1107. One input terminal of the In a different mode of operation automatic test equipment latch 1105 is connected to the output terminal of the mul (ATE) may access the IC 100 through its TAP interface 217 tiplexer 1108 and a second input terminal of the latch 1105 forms a scan data input terminal 1104, SI. The output in order to initialize the SPU 101 so that internal scan strings terminal of the latch 1107 forms a scan data output terminal, 45 403 and test wrappers 102 are loaded with predetermined SO, and is also connected to the control terminal of the test values. The response of the blocks 106 is observed using multiplexer 1108. The output terminal of the latch 1106 the scan strings 403 and test wrappers 102. Furthermore, the forms an output probe path, Q, for the logic analyzer ATE may be programmed to instruct the SPU 101 to execute channels. BIST or other buffer memory 218 test functions and to check The Scan clock Signals, A clk and B clk respectively, 50 the results to determine pass or fail conditions. and the Scan mode signal configure the PSE 1000. For In yet another mode of operation, it is possible to use an serial shift operations, the serial input (SI) on the line 1104 in-circuit test (ICT) or similar board-level test equipment to is captured into the latch 1105 when the A clk signal is access the IC 100 through its TAP interface 217 in order to applied and the output of the latch 1105 is captured into the instruct the SPU 101 to turn-on its external memory test latch 1106 when the B clk signal is applied. If the 55 function. In this mode, patterns are generated by the SPU Scan mode Signal on the line 1103 is set to a logic 1, the 101 and made to appear at specific I/O pins of the IC 100 B clk signal on the line 1102 is also passed through a which are coupled to external memory. For example, the IC multiplexer 1109 and an AND gate 1112 to the latch 1107 by 100 may generate the data and address values that are a clock signal line 1111. Thus, non-overlapping. A clk and applied to the external memory. The data responseS received B clk signals on the clock signal lines 1101 and 1102 60 are captured in order to determine if the external memory is respectively clock serial shift operations in the PSE 1000. functioning correctly. Signals scanned into the latch 1105 through line 1104 are While the description above provides a full and complete also scanned into the latch 1107 (and the latch 1106) and the disclosure of the preferred embodiments of the present SO output terminal. This completes the programming of the invention, various modifications, alternate constructions, PSE 1000 Such that value that has been loaded into the latch 65 and equivalents will be obvious to those with skill in the art. 1107 controls input multiplexer 1108 which selects between Thus, the scope of the present invention is limited solely by two input ports 1109 and 1110. Once the PSE 1000 has been the metes and bounds of the appended claims. 7 US 6,964,001 B2 15 16 What is claimed is: Strings of input/output port connectors is connected to 1. An input/output port connector, comprising: one of Said bus connectors. a storage element; 4. An input/output port connector as in claim 1, wherein: a probe in port; in a Second mode of operation, data is propagated from a probe out port; Said Scan in port through said Storage element to Said a data in port; Scan Out port, a data out port; in a third mode of operation, data propagates from Said a Scan in port, and Storage element to Said data out port, a Scan Out port, wherein, in a first mode of operation, contents of Said in a fourth mode of operation, data from Said data in port Storage element are used to Select between data on Said is captured in Said Storage element, and data in port and Said probe in port to propagate directly in a fifth mode of operation, data propagates directly from to Said probe out port. Said data in port to Said data out port. 2. A logic block, comprising: 5. An integrated circuit comprising: a multiplicity of input/output (I/O) ports, and 15 a multiplicity of logic blockS: a multiplicity of Said input/output port connectors as in an on-chip logic analyzer with a multiplicity of input claim 1, ports: and wherein each of Said I/O ports is connected to one of Said multiplicity of block input/output port connectors, and a multiplicity of probe lines: wherein each said input/output port connector is con wherein each of Said probe lines is adapted to capture nected to an adjacent one of Said input/output port Signals from Said logic blocks and to propagate Said connectors by connecting Said probe in ports of one Signals to one of Said multiplicity of input ports of Said input/output port connector to Said probe out ports of an on-chip logic analyzer, Said input ports of Said on-chip adjacent one of Said input/output port connectors and logic analyzer comprising: Said Scan in ports of Said one input/output port con 25 means to capture Said Signals from Said probe lines: nector to Said Scan out ports of Said adjacent one of Said means to align said Signals propagated through Said input/output port connectors, thus forming a String of probe lines to create aligned signals: and input/output port connectors. means to capture Said aligned signals. 3. An integrated circuit comprising: a multiplicity of logic blocks as in claim 2: 6. The integrated circuit as in claim 5, wherein Said a multiplicity of bus connectors: and on-chip logic analyzer further comprises means to transfer a test bus: Said aligned Signals Out of Said integrated circuit. wherein each of Said multiplicity of bus connectorS is connected to Said test bus, and wherein each of Said