Bicameral LLC v. NXP USA, Inc. et al

Western District of Texas, txwd-6:2018-cv-00294

BRIEF by Bicameral LLC.

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6 IN THE UNITED STATES DISTRICT COURT FOR THE WESTERN DISTRICT OF TEXAS WACO DIVISION BICAMERAL, LLC, Plaintiff, Case No. 6:18-cv-00294-ADA v. JURY TRIAL DEMANDED NXP USA, INC., NXP SEMICONDUCTORS N.V. AND NXP B.V., Defendants. PLAINTIFF BICAMERAL LLC'S OPENING BRIEF ON CLAM CONSTRUCTION 6 TABLE OF CONTENTS I. INTRODUCTION............................................................................................................. 1 A. The '331 Patent ....................................................................................................... 1 B. The '538 Patent ....................................................................................................... 1 II. DISPUTED CLAIM TERMS .......................................................................................... 2 A. "program counter means … for indexing said instructions" ('331 Patent, claims 1 and 21) ................................................................................ 2 B. "cause register means for indicating information regarding interrupts and exceptions" ('331 Patent, claim 1) .............................................................................................. 5 C. "cause register means for indicating cause information regarding interrupts and exceptions" ('331 Patent, claim 21) ............................................................................................ 8 D. "interrupt[s]" and "exception[s]" ('331 Patent, claims 1 and 21) ................................................................................ 9 E. "first output" ('331 Patent, claims 1 and 21) .............................................................................. 15 F. "first decoder means for indicating information about an instruction executed by said processor during a clock cycle" ('331 Patent, claims 1 and 21) .............................................................................. 17 G. "cause information" ('331 Patent, claim 21) .......................................................................................... 19 H. "dynamically computing" ('538 Patent, claims 1 and 21) .............................................................................. 20 i 6 TABLE OF AUTHORITIES Cases Applied Med. Res. Corp. v. United States Surgical Corp., 448 F.3d 1324 (Fed. Cir. 2006) 3, 7, 20 Avid Technology, Inc. v. Harmonic, Inc., 812 F.3d 1040 (Fed. Cir. 2016) .................................... 8 Cisco Sys., Inc. v. Innovative Wireless Solutions, LLC, 2015 WL 128138 (W.D. Tex. Jan. 8, 2015) ......................................................................................................................................... 22 Creo Prods. v. Presstek, Inc., 305 F.3d 1337 (Fed. Cir. 2002)....................................................... 4 Epos Tech. Ltd. v. Pegasus Tech. Ltd., 766 F.3d 1338 (Fed. Cir. 2014) .......................... 17, 21, 22 Festo Corp. v. Shoketsu Kinzoku Kogyo Kabushiki Co., 535 U.S. 732 (2002) ............................ 11 Kara Tech. Inc. v. Stamps.com Inc., 582 F.3d 1341 (Fed. Cir. 2009) .................................... 16, 21 Kothmann Enters. v. Trinity Indus., 394 F. Supp. 2d 923 (S.D. Tex. 2005) .................................. 4 LG Elecs., Inc. v. Bizcom Elecs., Inc., 453 F.3d 1364 (Fed. Cir. 2006) ......................................... 4 Liebel-Flarsheim v. Medrad, Inc., 358 F.3d 898 (Fed. Cir. 2004) ............................................... 17 Liqwd, Inc. v. L'Oréal USA, Inc., 720 Fed. Appx. 623 (Fed. Cir. Jan. 16, 2018) ........................ 16 Nautilus, Inc. v. Biosig Instruments, Inc. ...................................................................................... 10 Playtex Products, Inc. v. Procter & Gamble Co., 400 F.3d 901 (Fed. Cir. 2005).......................... 4 Presidio Components, Inc. v. American Technical Ceramics Corp., 875 F.3d 1369 (Fed. Cir. 2017) ......................................................................................................................................... 14 ScriptPro LLC v. Innovation Assocs., 833 F.3d 1336 (Fed. Cir. 2016) ........................................ 17 Sonix Technology Co., Ltd., 844 F.3d 1380 (Fed. Cir. 2017) ....................................................... 15 Wenger Mfg. v. Coating Mach. Sys., 239 F.3d 1225 (Fed. Cir. 2001).................................. 5, 7, 20 Statutes 35 U.S.C. § 112 ¶ 6 ................................................................................................................ passim ii 6 I. INTRODUCTION Plaintiff Bicameral LLC ("Bicameral") presents this opening claim construction brief relating to the disputed terms. There are currently four patents-in-suit: 6,321,331 (the "'331 Patent"); 6,639,538 (the "'538 Patent"); 6,754,223 (the "'223 Patent"); and RE42,092 (the "'092 Patent"). The parties have resolved claim construction disputes as to the '223 and '092 Patents, and therefore this brief only addresses the '331 and '538 Patents. This Court is familiar with pertinent claim construction principles and Bicameral cites to relevant authority in the body of the brief. A. The '331 Patent The '331 Patent is entitled "Real Time Debugger Interface For Embedded Systems." The application for the '331 Patent was filed by Transwitch Corporation, a Connecticut based semiconductor design company that has since been acquired by Cadence. The patent "relates to systems and methods for debugging software in real time" such as with "firmware in embedded systems, e.g. ASIC chips having one or more processors on a single chip." '331 Patent, col. 1:6- 10 (Kheyfits Decl., Ex. 1). A stated purpose of the '331 Patent was "to provide a debugging interface for tracing instructions without loss of real time context and event interaction." Tracing instructions with real-time context and event interaction is helpful to computer engineers because it allows them to understand the state of the processor while fixing bugs that appear in their code. The '331 Patent was briefly involved in several declaratory judgment actions brought by Xilinx, Inc. but, to Bicameral's knowledge, the '331 Patent was not involved in substantive district court litigation. The '331 Patent survived a reexamination process that was commenced on March 4, 2011, culminating in a reexam certificate issued on July 10, 2012. B. The '538 Patent The '538 Patent is entitled "Real-Time Transient Pulse Monitoring System and Method." 1 6 The application for the '538 Patent was filed by SRI International, a U.S. non-profit scientific research institute, originally known as the "Stanford Research Institute." The '538 Patent relates to measurements of parameters associated with transient, or short-term, phenomena such as electrical pulses or mechanical motion. Examples of transient phenomena provided by the patent include "electrical transients, such as those encountered on utility power lines or with lightning" and "mechanical shock or motion." '538 Patent, col. 4:47-60 (Kheyfits Decl., Ex. 2). The '538 Patent provides a solution that generally includes circuitry for converting an analog signal into digital data which is then continuously received by a digital circuit to characterize parameters of the stimulus. II. DISPUTED CLAIM TERMS A. "program counter means … for indexing said instructions" ('331 Patent, claims 1 and 21) Bicameral's Construction Defendants' Construction Function: indexing said instructions. 35 U.S.C. § 112 ¶ 6 function: indexing contents of memory Structure: program counter (such as 24a, 24b, means 24c) as described in Fig. 1, Abstract, col. 3:33- structure: program counter 24 which contains 42, col. 4:7-7:10, and claims; and equivalents. (i) an index of the instructions in an associated IRAM and (ii) pointer to the index as they instruction are executed. (and equivalents thereto) The parties agree that this is a means-plus-function term, but disagree on its function and structure. The asserted independent claims of the '331 Patent first recite instructions to be executed by the processor, and then recite a program counter means for indexing said instructions. For example, claim 1 recites: 2 6 '331 Patent, Col. 8:14-18 (underline added). As recited in the claim, the "program counter means" performs the function of "indexing said instructions." Bicameral's function for the program counter is taken verbatim from independent claims 1 and 21 in which this term appears. NXP, however, morphs the function from "indexing said instructions" into "indexing contents of memory means." In so doing, NXP confuses asserted and disputed claims that require the program counter to index "said instructions," such as claims 1 and 21, with not-currently- asserted claims that require "program counter means. . .for indexing contents of said instruction memory means," such as claims 11 and 22. NXP's proposed function also incorporates extraneous functional language into the claim. As the Federal Circuit explained: A court errs when it improperly imports unclaimed functions into a means-plus-function claim limitation. First, this can occur during claim construction by defining a claimed function to require more than is actually claimed. See JVW Enters., 424 F.3d at 1331. Second, the error can occur during infringement analysis if the court improperly determines the way in which the disclosed structure performs the previously-defined function. In this step, the inquiry should be restricted to the way in which the structure performs the properly-defined function and should not be influenced by the manner in which the structure performs other, extraneous functions. Applied Med. Res. Corp. v. United States Surgical Corp., 448 F.3d 1324, 1334 (Fed. Cir. 2006). In the present case, disputed independent claims 1 and 21 recite the function of "indexing said instructions" and NXP's extraneous language should not be incorporated into the claim. "The function of a means-plus-function limitation. . . must come from the claim language itself." Creo Prods. v. Presstek, Inc., 305 F.3d 1337, 1344 (Fed. Cir. 2002). Indeed, "[b]ecause the recited function is clear on its face, it [i]s improper to incorporate the additional functional limitation" into the claims. LG Elecs., Inc. v. Bizcom Elecs., Inc., 453 F.3d 1364, 1379 (Fed. Cir. 2006) (rev'd on other grounds). Thus, the correct function for this term is simply "indexing said instructions"—instructions that may be stored in the instruction memory means to be executed 3 6 by the processor. In contrast, NXP's function for this term refers to "contents of memory means," ignoring the actual language of the claim. Turning to the underlying structure, Bicameral identifies "a program counter (such as 24a, 24b, 24c)" as described in the specification, figures, and claims, including equivalents thereof. NXP's construction also refers to program counter 24 but further requires the structure to include "(i) an index of the instructions in an associated IRAM and (ii) pointer to the index as they instruction are executed." In support, NXP points to a sentence in the description of a preferred embodiment where the '331 Patent states that "[e]ach program counter contains an index of the instructions in an associated IRAM and a pointer to the index as the instructions are executed by the processor." However, NXP's proposed structure is unduly limiting. First, "[t]he corresponding structure for a means-plus-function patent claim can be found in drawings, the abstract, or the written description. Claims are not necessarily limited to drawings or descriptive phrases viewed in isolation." Kothmann Enters. v. Trinity Indus., 394 F. Supp. 2d 923, 972 (S.D. Tex. 2005) (citing Playtex Products, Inc. v. Procter & Gamble Co., 400 F.3d 901, 909 (Fed. Cir. 2005)). Viewing the "[e]ach program counter contains. . ." language in isolation ignores the fact that the inventors were describing a preferred embodiment that had three program counters, and the "each" was referring to those three specific program counters, and not to all program counters possible in the '331 Patent. Second, "[u]nder § 112, P 6, a court may not import functional limitations that are not recited in the claim, or structural limitations from the written description that are unnecessary to perform the claimed function." Wenger Mfg. v. Coating Mach. Sys., 239 F.3d 1225, 1233 (Fed. Cir. 2001). Here, NXP incorporates both functional and structural limitations into the structure that are not necessary to perform the claimed function. Even assuming that the function of the 4 6 program counter is to index the contents of a memory means (even though the recited function is "indexing said instructions"), the structure identified by NXP is beyond that required to perform the function. For example, to index the contents of a memory means, a program counter may use "an index of the instructions in an associated IRAM" and a "pointer to the index as the instructions are executed." But the program counter may also index the instructions by pointing to the instructions themselves, as opposed to only the index itself. See, e.g., '331 Patent at col. 4:29-31 ("the decoder 28 is arranged to indicate whether the program counter has moved its pointer to a new instruction.") (emphasis added). See also id. at col. 4:52-54 ("the processor has not processed a new instruction and the program counter pointer has not changed."). Id. at col. 4:56-57 ("the program counter pointer has incremented to the next instruction in the index."). Id. at col. 4:64-67 ("the program counter pointer has incremented to the next instruction in the index."). Thus, the structure proposed by NXP which requires both an index and a pointer is beyond that required to perform either of the identified functions. In view of the above, NXP's construction unduly limits both the function and structure of this element. B. "cause register means for indicating information regarding interrupts and exceptions" ('331 Patent, claim 1) Bicameral's Construction Defendants' Construction Function: indicating information regarding 35 U.S.C. § 112 ¶ 6 interrupts and exceptions function: indicating information regarding interrupts and exceptions Structure: cause register (such as 26a, 26b, and structure: Cause Register 26 that may store 26c) as described in Fig. 1, Abstract, col. 3:13- information about both (a) exception 42, col. 4:7-7:10, and claims; and equivalents. conditions; and (b) the pending interrupts simultaneously (and equivalents thereto) The parties agree as to the function of this claim term but dispute the structure of the cause register means. Specifically, Bicameral contends that the structure of this term is simply a 5 6 cause register as described in the specification and claims, for indicating "information regarding interrupts and exceptions." NXP's proposed structure, however, has several flaws. First, NXP's structure requires the cause register to store information about both exceptions and interrupts simultaneously—a requirement not found in the specification or prosecution history. Second, NXP's structure improperly incorporates language already found in the agreed function for this term. As to NXP's improper requirement that the cause register must store both exceptions and interrupts simultaneously, the specification explicitly states that "the contents of the cause register contain code which indicates an interrupt or exception." '331 Patent, col. 5:2-3 (emphasis added). An embodiment of the invention provides for a "second decoder" that "decodes the contents of the cause register and enables the history buffer whenever the contents of the cause register indicates an exception, a jump register instruction, or a change in the status of an interrupt line." '331 Patent, col. 3:19-22 (emphasis added). And, an embodiment of the history buffer, which captures information from the cause register, stores interrupt and exception codes in separate locations. Specifically, "[b]it locations 39 through 35 are used to store processor related exception conditions" and "[b]it locations 34 through 18 are used to store an indication of all pending interrupts (external, software, co-processor)." However, nowhere does the '331 Patent require the cause register to simultaneously store interrupt and exception conditions. In fact, the word "simultaneously" does not appear in the '331 Patent. Turning to the rest of NXP's construction, NXP improperly limits the structure of the term, both by importing features not required by the claim, and also by including structure beyond that required to perform the function. Specifically, the structure of a "register that may store information about both (a) exception conditions; and (b) pending interrupts 6 6 simultaneously" is beyond than required for the agreed function of "indicating information regarding interrupts and exceptions." As noted in Section II.A of this brief, "[u]nder § 112, P 6, a court may not import functional limitations that are not recited in the claim, or structural limitations from the written description that are unnecessary to perform the claimed function." Wenger Mfg. v. Coating Mach. Sys., 239 F.3d 1225, 1233 (Fed. Cir. 2001). See also Applied Med. Res. Corp. v. United States Surgical Corp., 448 F.3d at 1334. Finally, the prosecution history does not mandate NXP's proposed construction. For example, a reference cited in the reexam, the IBM PowerPC 403GA User's Manual ("IBM Manual") described an embedded controller having a Machine State Register ("MSR") and an External Interrupt Status Register ("EXISR"). As the Patent Owner explained, the EXISR only stored information about interrupts and the MSR consisted of "control bits" that "provide no information about interrupts and exceptions." Kheyfits Decl., Ex. 3, Excerpts From The File History Of The Re-Examination Of The '331 Patent, Patent Owner's September 27, 2011 Response to Office Action dated July 29, 2011, p. 27 (BC_GEN_0002234). Turning to the disputed claim term, the Patent Owner stated that the prior art combination, including the IBM Manual, "fails to disclose or suggest the claimed 'cause register means for indicating information regarding interrupts and exceptions.'" Id. at pp. 27-28 (BC_GEN_0002234-35). But, the Patent Owner never stated that the "cause register" must store both interrupt and exception information simultaneously. Accordingly, there was no prosecution history estoppel. Avid Technology, Inc. v. Harmonic, Inc., 812 F.3d 1040, 1045 (Fed. Cir. 2016) ("Where the alleged disavowal is ambiguous, or even amenable to multiple reasonable interpretations, we have declined to find prosecution disclaimer.") (internal citations and quote marks omitted). 7 6 C. "cause register means for indicating cause information regarding interrupts and exceptions" ('331 Patent, claim 21) Bicameral's Construction Defendants' Construction Function: indicating cause information 35 U.S.C. § 112 ¶ 6 regarding interrupts and exceptions function: indicating cause information regarding interrupts and exceptions Structure: cause register (such as 26a, 26b, and 26c) as described in Fig. 1, Abstract, col. 3:13- structure: same as above 42, col. 4:7-7:10, and claims; and equivalents. The "cause register means" of this term differs from the preceding "cause register means" term by "indicating cause information regarding interrupts and exceptions" whereas the previous term simply requires "indicating information regarding interrupts and exceptions." The parties agree as to the function of this claim term but dispute the structure of the cause register means. Bicameral contends that the structure of this claim term is simply a cause register as described in the specification, for indicating "cause information regarding interrupts and exceptions." NXP, however, argues that the structure of this term is the same as that of the "cause register" in Section II.B, effectively arguing that "information" means the same thing as "cause information." Yet, the Patent Owner explained during reexamination that "in the patented claims, the word 'cause' is used as an adjective." Kheyfits Decl., Ex. 3, Excerpts From The File History Of The Re-Examination Of The '331 Patent, Patent Owner's September 27, 2011 Response to Office Action dated July 29, 2011, p. 28 (BC_GEN_0002235). Indeed, the Patent Owner distinguished this claim element from registers that provide no cause information. Specifically, a reference cited in reexam, the IBM PowerPC 403GA User's Manual ("IBM Manual") described an embedded controller having a Machine State Register ("MSR"), which "acts as a switch to allow a user to enable or disable certain interrupts and exceptions by setting the value of certain bits." Kheyfits Decl., Ex. 3, Excerpts From The File History Of The Re-Examination Of The 8 6 '331 Patent, Patent Owner's September 27, 2011 Response to Office Action dated July 29, 2011, p. 18 (BC_GEN_0002225). As the Patent Owner explained, "the MSR provides no cause information regarding interrupts or exceptions, but rather simply functionality enabling user settings of exceptions and interrupts." Id. NXP's structure for this claim term requires indicating "information about both (a) exception conditions; and (b) the pending interrupts simultaneously (and equivalents thereto)." Bicameral does not dispute that information about "exception conditions" and "pending interrupts" is an example of "cause information." However, NXP's structure for this term again requires "simultaneous" storage of exceptions and interrupts, when neither the specification nor the prosecution history so require. As noted in Section II.B of this brief, the specification explicitly states that "the contents of the cause register contain code which indicates an interrupt or exception." '331 Patent, col. 5:2-3 (emphasis added). And, the specification also explains that the history buffer can be enabled "whenever the contents of the cause register indicates an exception, a jump register instruction, or a change in the status of an interrupt line." Id. at 3:20- 22 (emphasis added). Thus, while the "cause register" must be capable of storing information about interrupts and exceptions, it does not need to store both simultaneously. Accordingly, NXP's proposed structure for this claim term is too limiting and should be rejected. D. "interrupt[s]" and "exception[s]" ('331 Patent, claims 1 and 21) "interrupt[s]" Bicameral's Construction Defendants' Construction no construction required/plain and ordinary Indefinite meaning "exception[s]" Bicameral's Construction Defendants' Construction no construction required/plain and ordinary Indefinite meaning 9 6 In Nautilus, Inc. v. Biosig Instruments, Inc. the Supreme Court held that 35 U.S.C. § 112 ¶ 2 requires "a patent's claims, viewed in light of the specification and prosecution history, [to] inform those skilled in the art about the scope of the invention with reasonable certainty." 572 U.S. 898, 910 (2014). The Nautilus court explained that "[t]he definiteness requirement, so understood, mandates clarity, while recognizing that absolute precision is unattainable." Id. Indeed, in discussing its prior precedent, the Court recognized that some uncertainty would not run afoul of the definiteness requirement. Id. at 909. ("Some modicum of uncertainty. . . is the price of ensuring the appropriate incentives for innovation.") (citing Festo Corp. v. Shoketsu Kinzoku Kogyo Kabushiki Co., 535 U.S. 732 (2002)). In the '331 Patent, the terms "interrupt" and "exception" have plain and ordinary meanings that require no further construction. In his declaration, Bicameral's expert witness, David Hansquine, M.S., states that "[i]n my opinion these terms did not require any explanation in the specification of the '331 Patent because of their widely accepted meaning at the time of the '331 Patent's invention. Hansquine Decl. ¶ 24. Mr. Hansquine explained that "[i]n the field of the '331 Patent, "interrupt" refers to a break in the normal program flow of a computer system or a process. The source of the interrupt may be external or internal." Id. ¶ 25. "When the normal flow of a processor is suspended by an interrupt from an internal or external source, typically, the processor begins to execute a corresponding interrupt handler, which is a sequence of instructions intended to appropriately handle the interrupt. Following the execution of the interrupt handler, the processor resumes from the point where the break occurred." Id. ¶ 25. This is consistent with dictionaries available at the time the '331 Patent application was filed. See, e.g., Interrupt – 1. In a computer, a break in the normal flow of a system or routine such that the flow can be resumed from that point at a 10 6 later time. The source of the interrupt may be internal or external. 2. A method of stopping a process and identifying that a certain condition exists. In graphic systems, interrupts can originate from data entry devices, the display list, the host computer, the refresh clock, and display error conditions. When an interrupt occurs, the host computer and display refresh cease until the interrupt is answered and processed. At that time, the host computer will restart the refresh usually from where it was halted. If a new display list is to be presented, the display starts at the beginning of the list. 3. To disrupt temporarily the normal execution of a program by a special signal from the computer. 4. To stop a process so that it cannot be automatically resumed. Hansquine Decl. ¶ 27, Ex. 3, Modern Dictionary of Electronics. Sixth Edition (1997), p. 515. According to Mr. Hansquine, definitions (1) and (2) in the above dictionary excerpt are consistent with the understanding of "interrupt" by a person of ordinary skill in the art at the time of the invention, as used in the '331 Patent. Id. ¶ 27. Turning to "exceptions," in his declaration Mr. Hansquine also stated that "[i]n the context of microprocessors, an 'exception' refers to an abnormal condition detected by the micro-processor in relation to the instructions it is executing." Hansquine Decl. ¶ 28. "When such a condition occurs, the processor itself, the operating system, or a programming language typically provide facilities to define, raise, recognize, ignore, and/or handle the abnormal situation." Id. "When such an event occurs, control is typically transferred to an exception handler, which is a sequence of instructions intended to appropriately handle the exception." Id. Mr. Hansquine discussed two examples of exceptions, such as division by zero and a page fault. Id. Mr. Hansquine further stated that a contemporaneous dictionary definition confirms the understanding of a person of ordinary skill in the art at the time of the '331 Patent's invention and provided the following definition Exception – In a computer, a condition which is out of the ordinary in normal task execution; e.g., arithmetic overflow. 11 6 Hansquine Decl. ¶. 31, Ex. 3, Modern Dictionary of Electronics. Sixth Edition (1997), p. 353 Finally, Mr. Hansquine explained the differences between "interrupt" and "exception" as would be appreciated by a person of ordinary skill in the art at the time of the '331 Patent's invention: Both interrupts and exceptions result in a deviation from normal process execution, but a key distinction to underscore the differences is that interrupts often signal events independent of instruction execution – in other words, they signal asynchronous events that occur in the computer system that may require attention. Exceptions, on the other hand, typically occur in relation to instruction execution. . . . Another key distinction between interrupts and exceptions is that for interrupts, the code or program that was interrupted is generally resumed after the interrupt handler completes. In the case of an exception, while this may occur for certain classes of exceptions, there are other classes of exceptions for which the program that generated the exception may be aborted. Hansquine Decl. ¶ 33. Mr. Hansquine concluded that "[a] person of ordinary skill in the art at the time of the '331 Patent invention would understand the terms 'interrupts' and 'exceptions' with reasonable certainty, consistent with the above dictionary definitions, and would not require further clarification from the specification as to the meaning of these terms." Hansquine Decl. ¶ 34. Indeed, Mr. Hansquine's declaration establishes that a person of ordinary skill in the art would understand with reasonable certainty what interrupts and exceptions mean because their widely accepted meanings are consistent with how the inventors used those terms in the specification. For example, the inventors discussed the change "in the status of an interrupt line" (external interrupt) as distinct from an exception: The second decoder decodes the contents of the cause register and enables the history buffer whenever the contents of the cause register indicates an exception, a jump register instruction, or a change in the status of an interrupt line. Ex. 1 '331 Patent at col. 3:19-23. The inventors also explained that, generally, exception 12 6 conditions are "processor related" but interrupts can be "external, software, [or] co-processor": Bit locations 39 through 35 are used to store processor related exception conditions. Bit locations 34 through 18 are used to store an indication of all pending interrupts (external, software, co- processor. Ex. 1, '331 Patent at col. 6:66-7:3. In both instances, the usage of the terms "interrupts" and "exceptions" is consistent with the plain and ordinary meaning as would be understood by a person skilled in the art consistent with Mr. Hansquine's opinions. Hansquine Decl. ¶ 34. NXP, however, contends that "interrupt" and "exception" are indefinite. Although in its claim construction disclosures, NXP did not provide details for its indefiniteness position, the following discussion in its invalidity contentions is informative: However, the '331 specification does not provide any basis to distinguish interrupts from exceptions and many processor architectures intermingle the terminology and/or use the same type of "handlers" to perform processing regardless of whether the event is denominated an "interrupt" or an "exception." The '331 specification did not explain the difference between these two events sufficiently to convey that alleged difference meaning to one of ordinary skill in the art. Kheyfits Decl., Ex. 4, NXP Invalidity Contentions p. 35. NXP's indefiniteness argument fails for three reasons. First, as discussed above, Mr. Hansquine's expert declaration supports Bicameral's position that these terms have plain and ordinary meanings, accepted by persons of ordinary skill in the art, and that require no further construction. Second, the fact that the '331 Patent specification does not spell out the distinction between "interrupt" and "exception" to NXP's liking does not render the claims invalid because "[a] patent need not explicitly include information that is already well known in the art." Presidio Components, Inc. v. American Technical Ceramics Corp., 875 F.3d 1369 (Fed. Cir. 2017). Third, the use of these terms by experts in the field such as patent examiners and NXP 13 6 itself weighs against the finding of indefiniteness. For example, during the prosecution of the '331 Patent, the examiner stated the following: As for claims 7, 17 and 25, Folwell et al. disclosed the second decoder means enables the event history buffer means when the cause register means indicate an event of a change in status of an interrupt line, internal processor exception, or a, jump based on the contents of a register. . . Kheyfits Decl., Ex. 5, Excerpt From The File History Of The '331 Patent, Office Action dated June 10, 1999, pp. 6-7 (BC_GEN_0000246 – 247). The above passage demonstrates that the examiner not only understood the meaning of the terms, but understood and appreciated the distinction between them. Moreover, during reexamination, similarly evidencing the understanding of, and distinction between, "interrupt" and "exception," the examiner stated: The IBM Manual for the PPC403GA teaches, e.g., a machine state register (MSR) and/or an external interrupt status register (EXISR) for indicating information regarding interrupts and exceptions. Kheyfits Decl. Ex. 3, Excerpts From The File History Of The Re-Examination Of The '331 Patent, Office Action dated April 8, 2011, p. 4 (BC_GEN_0002146). The examiner's understanding and usage of these terms provides evidence of definiteness. Sonix Technology Co. v. Publ'ns Int'l, Ltd., 844 F.3d at 1370 (Fed. Cir. 2017) ("Although Appellees are correct that application by the examiner and an expert do not, on their own, establish an objective standard, they nevertheless provide evidence that a skilled artisan did understand the scope of this invention with reasonable certainty.") Moreover, NXP itself uses the terms "interrupt" and "exception" in its own patents indicating that it understands the meaning of these terms. For example, NXP states in U.S. Patent No. 9,626,280 entitled "Debug Method And Device For Handling Exceptions and Interrupts: FIGS. 5 and 6 are flow diagrams indicating a manner in which 14 6 exceptions and interrupts are handled by a data processor in accordance with a specific embodiment. As used herein, the term "exception/interrupt" is intended to refer to one of either an exception or an interrupt. The use of either the term "exception" or the term "interrupt" by itself is intended to refer specifically to an exception or an interrupt, respectively. Kheyfits Decl. Ex. 6, U.S. Pat. No. 9,626,280, col. 11:44-51. Significantly, "evidence of a challenger's own ability to apply a term without unreasonable uncertainty counts against an indefiniteness contention." Liqwd, Inc. v. L'Oréal USA, Inc., 720 Fed. Appx. 623 (Fed. Cir. Jan. 16, 2018). In view of the above, the terms "interrupt" and "exception" are well understood by those skilled in the art with reasonable certainty, including NXP itself, and NXP has not established otherwise by clear and convincing evidence. E. "first output" ('331 Patent, claims 1 and 21) Bicameral's Construction Defendants' Construction no construction required/plain and ordinary "3-bit output interpreted as shown in Table meaning 1" This term requires no further construction. The parties appear to agree that the word "output" requires no construction as NXP uses this very word in its proposed construction. The '331 Patent uses the word "first" as a label, to distinguish this output, from another, "second output" recited in claim 6. No construction is required beyond this plain and ordinary meaning. NXP's proposed construction impermissibly limits the claims to an embodiment disclosed in the specification. The claims already recite a "a first output" without specifying a number of output bits (see claims 1 and 21). "The claims, not specification embodiments, define the scope of patent protection. The patentee is entitled to the full scope of his claims, and we will not limit him to his preferred embodiment or import a limitation from the specification into the claims." Kara Tech. Inc. v. Stamps.com Inc., 582 F.3d 1341 (Fed. Cir. 2009). "[I]t is improper to 15 6 read limitations from a preferred embodiment described in the specification—even if it is the only embodiment—into the claims absent a clear indication in the intrinsic record that the patentee intended the claims to be so limited." Epos Tech. Ltd. v. Pegasus Tech. Ltd., 766 F.3d 1338, 1341 (Fed. Cir. 2014) (quoting Liebel-Flarsheim v. Medrad, Inc., 358 F.3d 898, 914 (Fed. Cir. 2004)). In addition, the 3-bit output is only required by dependent claim 5. As importantly, claim 10, which depends on claims 9, 6, and 1, recites "wherein: said first output is an n-bit parallel output." (emphasis added). For the avoidance of doubt, the inventors included claim 10 with the application at the time of filing: Kheyfits Decl., Ex. 7, U.S. Patent Application No. 09/064,474 as filed on April 22, 1998, p. 26, claim 10 (BC_GEN_0000175). It is black letter law that "[o]riginal claims are part of the specification." ScriptPro LLC v. Innovation Assocs., 833 F.3d 1336, 1341 (Fed. Cir. 2016). And while the preferred embodiment of the '331 Patent may be directed to a 3-bit first output, "a specification's focus on one particular embodiment or purpose cannot limit the described invention where that specification expressly contemplates other embodiments or purposes." Id. at 1341. Because the '331 Patent, the original prosecution history, and re-exam prosecution history contain no clear indication that the claims should be limited to a 3-bit output, and, in fact, provide the opposite, NXP's proposed construction should be rejected. 16 6 F. "first decoder means for indicating information about an instruction executed by said processor during a clock cycle" ('331 Patent, claims 1 and 21) Bicameral's Construction Defendants' Construction Function: indicating information about an 35 U.S.C. § 112 ¶ 6 instruction executed by said processor during a function: indicating information about an clock cycle instruction executed by said processor during a clock cycle Structure: first decoder (such as 28a, 28b, 28c) structure: Decoder 28 with three bit output as described in Fig. 1, Abstract, col. 2:62-3:32, (elements 30a, 30b, 30c) on a cycle by cycle col. 3:43-58, col. 4:20-6:39, col. 7:21-8:10, basis which is indicative of the processor and claims; and equivalents. activity during the last clock cycle indicating the outputs as interpreted in Table 1 by decoding the instruction in IRAM and the contents of the cause register (and equivalents thereto) The parties agree as to the function of this claim term but dispute the structure of the "first decoder means." Specifically, Bicameral contends that the "first decoder means" is simply the first decoder as described in the specification. NXP, however, incorporates structure far beyond that required to perform the agreed-upon function. First, NXP argues that the decoder must have a "three bit output." As discussed in Section II.E above, limiting the claims to a three-bit output embodiment is improper. Second, NXP's reference to "outputs as interpreted in Table 1" is as flawed as its "three bit output" position because the '331 Patent discloses decoders with outputs of greater than or less than three bits (n-bits), as described above. As the patent itself explains, "while particular configurations have been disclosed in reference to the indications provided by the first decoders, it will be appreciated that other configurations could be used as well, provided that they achieve substantially the same results as described herein." '331 Patent, col. 8:2-5. Thus, for example, a 4-bit output, would be able to provide 16 conditions and not be limited to the eight rows of Table 1. 17 6 In addition, Table 1 does not include an exclusive list of conditions that could be output by the first decoder. For example, Table 1 describes output "100" as "Exception Encountered" while the specification explains that "output 100 indicates that since the last clock cycle the processor has encountered an interrupt or an exception…." '331 Patent, col. 4:67-5:2 (emphasis added). Thus, the specification contemplates indications of interrupts or exceptions within Table 1, not just indications of exceptions. In another example, Table 1 describes output "111" as "Exception Encountered, No History Buffer Entry Written." But the specification notes that in one embodiment, 111 may also "indicate[] that since the last clock cycle the processor has encountered an interrupt or an exception…." Id. at 5:9-10. This, again, illustrates that the '331 Patent contemplates multiple versions of Table 1. Thus, Table 1 and surrounding language listed in NXP's claim construction should not be incorporated into the structure of this term. Third, the remaining portions of NXP's construction, such as "by decoding the instruction in IRAM and the contents of the cause register," are actions of the first decoder in the preferred embodiment, and not "structure" as NXP contends. For example, the specification provides that: The decoder also decodes the instruction in the IRAM to provide information about the instruction, an decodes the contents of the cause register to provide an indication of an exception encountered during the execution of an instruction. '331 Patent, col. 4:31-35. But this excerpt describes steps that the decoder may perform, and not the structure of the decoder. Even if the above excerpt were to disclose the structure of the first decoder, it would be optional structure that goes beyond that required to perform the function. The agreed-upon function for this claim term is "indicating information about an instruction executed by said processor during a clock cycle," and decoding the instruction in IRAM and the contents of the cause register are not required to perform the function. As noted 18 6 in Section II.A of this brief, "[u]nder § 112, P 6, a court may not import functional limitations that are not recited in the claim, or structural limitations from the written description that are unnecessary to perform the claimed function." Wenger Mfg. v. Coating Mach. Sys., 239 F.3d 1225, 1233 (Fed. Cir. 2001). See also Applied Med. Res. Corp. v. United States Surgical Corp., 448 F.3d at 1334. G. "cause information" ('331 Patent, claim 21) Bicameral's Construction Defendants' Construction Plain and ordinary meaning; requires no "cycle by cycle information regarding the construction current instruction being executed by the processor; capable of indicating at least one In the alternative: "information regarding a instance of each of the following: whether it cause" is an exception, a jump / branch instruction based on the contents of a register or a change in the status of the interrupt line" Bicameral submits that this term has a plain and ordinary meaning and requires no further construction. The parties appear to agree that the term "information" requires no construction because NXP uses it as part of its own proposed construction. Bicameral submits that "cause" sufficiently qualifies "information" to convey that the subject information is regarding the cause of the program leaving the normal path of software execution. As the Patent Owner explained, "in the patented claims, the word 'cause' is used as an adjective." Kheyfits Decl., Ex. 3, Excerpts From The File History Of The Re-Examination Of The '331 Patent, Patent Owner's September 27, 2011 Response to Office Action dated July 29, 2011, p. 28 (BC_GEN_0002235). No further construction is necessary. In the alternative, Bicameral proposes to construe this term to mean "information regarding a cause." NXP, again, invites the Court to overload the construction with limitations pertinent to one specific embodiment disclosed in the '331 Patent. Because there is no clear indication in the patent or prosecution history that the patentee intended the invention to be so limited, the Court 19 6 should decline NXP's invitation. See Kara Technology Inc., 582 F.3d 1341 (Fed. Cir. 2009); Epos Tech. Ltd. v. Pegasus Tech. Ltd., 766 F.3d 1338 (Fed. Cir. 2014). H. "dynamically computing" ('538 Patent, claims 1 and 21) Bicameral's Construction Defendants' Construction "computing in real-time or near-real-time" "computing in real-time" The '538 Patent discloses and claims a system for characterizing a stimulus represented by an analog signal. The stimuli characterized in the exemplary embodiment are electrical transients, such as the ones caused by lightnings. The patent disclosed other stimuli such as "kinetic (dynamic) energy, potential (static) energy, radiation (electromagnetic) energy, heat, light, chemical, and electrical." An important feature of the invention is to continuously convert the analog signal representing the stimulus into digital data and analyze the digital data without dead time. Although the patent focuses on real-time processing, the inventors realized that that the benefits and the goals of the invention may be achieved in near-real-time, i.e., with a slight delay due to transmission and processing of signals and data, but still without dead times when no analog signal is sensed, digitized, and processed. In other words, if the system ensures no dead time, but delays the output by some negligible amount of time, the objectives of the system would still be fulfilled. The difference between the dead time that is not within the claim scope and the delay of real time determination (resulting in near-real-time determination) that is within the scope of the claims is illustrative. To this end, the '538 Patent discloses the following: Accordingly, a user can determine in near-real-time if transient phenomena have occurred (i.e., delayed from real-time by the time taken for the conversion circuitry 20 to receive and convert the analog signal into digital data and for the digital circuitry 22 to compute and transmit the parameter values to the storage system 28). The '538 Patent, col. 5:67-6:6. The above passage expressly contemplates near-real-time 20 6 computation, i.e., delayed from real-time by the time required to carry out the computation. The claims of the '538 Patent do not recite "real time." And while Bicameral's proposed construction of "dynamically computing" properly captures the scope of the invention by permitting for real-time and near-real-time computations, NXP's proposed construction improperly limits the claims to only real-time computations, despite the above disclosure in the patent and controlling precedent. "Although the specification may indicate that certain embodiments are preferred, particular embodiments appearing in the specification will not be read into the claims when the claim language is broader than the embodiment." Cisco Sys., Inc. v. Innovative Wireless Solutions, LLC, 2015 WL 128138, *2 (W.D. Tex. Jan. 8, 2015). See also Epos Tech. Ltd. v. Pegasus Tech. Ltd., 766 F.3d 1338, 1341 (Fed. Cir. 2014) ("it is improper to read limitations from a preferred embodiment described in the specification—even if it is the only embodiment—into the claims absent a clear indication in the intrinsic record that the patentee intended the claims to be so limited."). For the above reasons, Bicameral construction for this term should be adopted. 21 6 Dated: August 12, 2019 Respectfully submitted, /s/ Dmitry Kheyfits Dmitry Kheyfits (Admitted Pro Hac Vice) California State Bar No. 321326 dkheyfits@kblit.com KHEYFITS BELENKY LLP 4 Embarcadero Center, Suite 1400 San Francisco, CA 94111 Tel: 415-429-1739 Fax: 415-429-6347 Andrey Belenky (Admitted Pro Hac Vice) New York State Bar No. 4524898 abelenky@kblit.com Hanna G. Cohen (Admitted Pro Hac Vice) hgcohen@kblit.com New York State Bar No. 4471421 KHEYFITS BELENKY LLP 1140 Avenue of the Americas 9th Floor New York, New York 10036 Tel. (212) 203-5399 Fax. (212) 203-6445 Raymond W. Mort, III Texas State Bar No. 00791308 raymort@austinlaw.com THE MOST LAW FIRM, PLLC 106 E. Sixth Street, Suite 900 Austin, Texas 78701 Tel/Fax: (512) 865-7950 Attorneys for Plaintiff Bicameral, LLC 22 6 CERTIFICATE OF SERVICE I hereby certify that all counsel of record who are deemed to have consented to electronic service are being served with a copy of this document and all accompanying documents via the Court's CM/ECF system on August 12, 2019. /s/ Dmitry Kheyfits Dmitry Kheyfits 23