Bicameral LLC v. NXP USA, Inc. et al

Western District of Texas, txwd-6:2018-cv-00294

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8 Kheyfits Declaration Exhibit 8 8 IN THE UNITED STATES DISTRICT COURT FOR THE WESTERN DISTRICT OF TEXAS WACO DIVISION § Bicameral LLC, § § Plaintiff § § v. § Civil Action No. 6:18-cv-00294 § NXP USA, Inc., NXP Semiconductors N.V., § Jury Trial Demanded and NXP B.V., § § Defendants. § § § § DEFENDANTS' DISCLOSURE OF PROPOSED CLAIM CONSTRUCTIONS Pursuant to the Court's Amended Scheduling Order (Dkt. #41), Defendants NXP USA, Inc., NXP Semiconductors N.V., and NXP B.V. (collectively, "NXP" or "Defendants") hereby disclose their proposed constructions for the claim terms and/or phrases ("terms") from the Asserted Claims of the Patents-in-Suit identified by the parties as potentially requiring construction. Defendants do not waive their right to argue, including in the alternative to construction, that one or more of these terms are indefinite under 35 U.S.C. § 112. See Defendants' Preliminary Invalidity Contentions served on July 3, 2019. This disclosure of proposed constructions is preliminary in nature and is based on Defendants' present understanding of the terms that may be relevant to Plaintiff's infringement contentions on the presently asserted patent claims and/or Defendants' invalidity contentions as to such claims, and Defendants reserve the right to update this disclosure as the case develops. For example, Defendants may update their disclosure (including by adding terms or modifying proposed constructions) based on Plaintiff's disclosure of its proposed constructions, the meet- 8 and-confer process with Plaintiff, amendments to Plaintiff's infringement contentions or Defendants' invalidity contentions, information obtained during discovery, and/or other developments bearing on this disclosure. This disclosure includes terms and phrases that Defendants assert should be given their plain meaning. However, in Plaintiff's infringement contentions, Plaintiff appears to construe several terms in a manner that is contradictory to or broader than their plain meaning. Accordingly, Defendants have identified all terms for which it presently appears a claim construction dispute may exist so that those disputes may be resolved, if possible, during the meet-and-confer process, or as required by the Court at the Markman hearing. O2 Micro Int'l Ltd. v. Beyond Innovation Tech. Co., 521 F.3d 1351, 1362 (Fed. Cir. 2008). NXP reserves all of its rights and does not waive any proposed construction, defense, or position by the submission of this disclosure. Further, NXP reserves the right to refine the tables below by combining or dividing identified claim terms in an effort to resolve any dispute that may arise as to the proper disposition of the tabulated claim terms. Additionally, NXP reserves the right to propose constructions for claim terms heretofore not construed by the parties. 1. U.S. Patent No. 6,008,727 (Asserted Claims 1 and 2) Claim Term Asserted Proposed Construction Claims processor 1 plain meaning identification number 1 plain meaning interconnect switch 1 "a device having electrical contacts that can be opened or closed to complete or break an electric circuit" user defined 1 "opening or closing electrical contacts in a switch interconnection based on the actions of a user or rules selected by a user" 2 8 the interconnect switch is 2 "the interconnect switch is configured such that biased to remain normally its electrical contacts are in the open position open except during specific periods in which the electrical contacts are temporarily closed according to certain rules or user actions" 2. U.S. Patent No. 6,321,331 (Asserted Claims 1, 2, 3, 4, 21, 23, and 24) Claim Term Asserted Proposed Construction Claims instruction memory 1, 21 35 U.S.C. § 112 ¶ 6 means for storing function: storing instructions to be executed by instructions to be said processor executed by said processor structure: instruction RAM (IRAM) 18 and equivalents storing instructions 1, 21 "the act of maintaining in memory the instructions to be executed by the processor" program counter means 1, 21 35 U.S.C. § 112 ¶ 6 … for indexing said function: indexing contents of memory means instructions structure: program counter 24 which contains (i) an index of the instructions in an associated IRAM and (ii) pointer to the index as they instruction are executed. (and equivalents thereto) directly coupled 1 "coupled with no intermediate elements (including specifically no intermediate bus) between those so coupled" cause register means for 1 35 U.S.C. § 112 ¶ 6 indicating information function: indicating information regarding regarding interrupts and interrupts and exceptions exceptions structure: Cause Register 26 that may store information about both (a) exception conditions; and (b) the pending interrupts simultaneously (and equivalents thereto) cause register means for 21 35 U.S.C. § 112 ¶ 6 indicating cause function: indicating cause information regarding information regarding interrupts and exceptions interrupts and exceptions 3 8 structure: same as above interrupts 1, 21, 24 indefinite exceptions 1, 21 indefinite first output 1, 21 "3-bit output interpreted as shown in Table 1" first decoder means for 1, 21 35 U.S.C. § 112 ¶ 6 indicating information function: indicating information about an about an instruction instruction executed by said processor during a executed by said clock cycle processor during a clock cycle structure: Decoder 28 with three bit output (elements 30a, 30b, 30c) on a cycle by cycle basis which is indicative of the processor activity during the last clock cycle indicating the outputs as interpreted in Table 1 by decoding the instruction in IRAM and the contents of the cause register (and equivalents thereto) cause information 21, 23 "cycle by cycle information regarding the current instruction being executed by the processor; capable of indicating at least one instance of each of the following: whether it is an exception, a jump / branch instruction based on the contents of a register or a change in the status of the interrupt line" 3. U.S. Patent No. 6,639,538 (Asserted Claims 1, 2, 3, 4, 7, 8, 9, 10, 12, 13, 14, 15, 17, 19, 20, 21, 22, and 23) Claim Term Asserted Proposed Construction Claims conversion circuitry 1 plain meaning continuously receiving the analog signal and converting the analog signal into digital data continuously receiving 1 plain meaning the analog signal and converting the analog signal into digital data 4 8 continuously receiving 1 plain meaning the analog signal continuously … 1 plain meaning converting the analog signal into digital data digital circuitry in 1 dynamically computing: "computing in real- communication with the time" conversion circuitry to receive continuously the digital data from the Rest is plain meaning conversion circuitry, the digital circuitry dynamically computing from the digital data a value that characterizes a parameter of the stimulus while the digital circuitry continuously receives new digital data from the conversion circuitry digital circuitry in 1 plain meaning communication with the conversion circuitry to receive continuously the digital data from the conversion circuitry receive continuously the 1 plain meaning digital data from the conversion circuitry dynamically computing 1 dynamically computing: "computing in real- from the digital data a time" value that characterizes a parameter of the stimulus while the digital circuitry Rest is plain meaning continuously receives new digital data from the conversion circuitry while the digital circuitry 1 plain meaning continuously receives 5 8 new digital data from the conversion circuitry a processing unit 14 dynamically computing: "computing in real- dynamically computing time" from the digital data a value that characterizes a parameter of the stimulus Rest is plain meaning processing unit 14 plain meaning dynamically computing 14 dynamically computing: "computing in real- from the digital data a time" value that characterizes a parameter of the stimulus Rest is plain meaning memory buffer 14 plain meaning continuously receiving 14 plain meaning new digital data from the analog-to-digital converter while the processing unit processes digital data received from the memory buffer to compute the value that characterizes the parameter of the stimulus continuously receiving 14 plain meaning new digital data from the analog-to-digital converter continuously receiving 21 plain meaning digital data digitized from the analog signal representing the stimulus dynamically computing 21 dynamically computing: "computing in real- from the continuously time" received digital data a value that characterizes a parameter of the stimulus Rest is plain meaning while receiving new digital data digitized 6 8 from the analog signal representing the stimulus dynamically computing 21 dynamically computing: "computing in real- from the continuously time" received digital data a value that characterizes a parameter of the stimulus Rest is plain meaning while receiving new 21 plain meaning digital data digitized from the analog signal representing the stimulus dynamically computing 1, 14, 21 "computing in real-time" 4. U.S. Patent No. 6,754,223 (Asserted Claims 1 and 5) Claim Term Asserted Proposed Construction Claims co-processor circuitry 1 plain meaning configured to receive and store communication packets in data buffers and determine a prioritized processing order, wherein the co- processor circuitry is configured to determine priorities for the communication packets, place entries in priority queues based on the priorities, and arbitrate the entries to establish the prioritized processing order, and wherein the co-processor circuitry is configured to determine the priorities based on a number of outstanding request for processing from individual ones of the priority queues 7 8 wherein the co-processor 1 plain meaning circuitry is configured to determine priorities for the communication packets place entries in priority 1 plain meaning queues based on the priorities arbitrate the entries to 1 plain meaning establish the prioritized processing order wherein the co-processor 1 plain meaning circuitry is configured to determine the priorities based on a number of outstanding request for processing from individual ones of the priority queues a core processor 1 plain meaning configured to execute a packet processing software application that directs the core processor to process the communication packets in the data buffers based on the prioritized processing order packet processing 1, 5 plain meaning software application based on the prioritized 1, 5 plain meaning processing order directs the core processor 1 plain meaning to process the communication packets in the data buffers based on the prioritized processing order 8 8 co-processor circuitry 1, 5 plain meaning operates in parallel with the core processor in co-processor circuitry 5 plain meaning receiving and storing the 5 plain meaning communication packets in data buffers and determine a prioritized processing order, wherein determining the prioritized processing order comprises determining priorities for the communication packets placing entries in priority 5 plain meaning queues based on the priorities arbitrating the entries to 5 plain meaning establish the prioritized processing order wherein determining the 5 plain meaning prioritized processing order comprises determining the priorities based on a number of outstanding request for processing from individual ones of the priority queues in a core processor 5 plain meaning executing a packet 5 plain meaning processing software application that directs the core processor to process the communication packets in the data buffers based 9 8 on the prioritized processing order packet processing 5, 1 plain meaning software application based on the prioritized 5, 1 plain meaning processing order co-processor circuitry 5, 1 plain meaning operates in parallel with the core processor 5. U.S. Patent No. RE42,092 (Asserted Claims 1, 2, 5, 17, 18, 21, 33, 34, 35, 38, 51, 52, and 55) Claim Term Asserted Proposed Construction Claims a core processor 1 plain meaning configured to create a plurality of external buffers that are external to the integrated circuit and configured to store the communication packets where each external buffers is associated with a pointer that corresponds to the external buffer control logic configured 1 allocate: "reserve the buffer, so other entities do to allocate the external not improperly write to it while it is allocated" buffers as the corresponding pointers are read from the pointer de-allocate: "release the buffer, so other entities cache and de-allocate the may reserve it" external buffers as the corresponding pointers are written back to the Rest is plain meaning pointer cache wherein the control logic is configured to transfer an exhaustion signal if a number of the pointers to the de-allocated buffers 10 8 reaches a minimum threshold allocate the external 1 allocate: "reserve the buffer, so other entities do buffers as the not improperly write to it while it is allocated" corresponding pointers are read from the pointer cache Rest is plain meaning allocate the external 1, 33 allocate: "reserve the buffer, so other entities do buffers not improperly write to it while it is allocated" Rest is plain meaning de-allocate the external 1 de-allocate: "release the buffer, so other entities buffers as the may reserve it" corresponding pointers are written back to the pointer cache Rest is plain meaning de-allocate the external 1, 33 de-allocate: "release the buffer, so other entities buffers may reserve it" Rest is plain meaning control logic is 1 de-allocate: "release the buffer, so other entities configured to transfer an may reserve it" exhaustion signal if a number of the pointers to the de-allocated buffers Rest is plain meaning reaches a minimum threshold the core processor 1 allocate: "reserve the buffer, so other entities do configured to create not improperly write to it while it is allocated" additional external buffers and their corresponding pointers in Rest is plain meaning response to the exhaustion signal allocating the external 17 allocate: "reserve the buffer, so other entities do buffers as the not improperly write to it while it is allocated" corresponding pointers 11 8 are read from the pointer Rest is plain meaning cache allocating the external 17, 51 allocate: "reserve the buffer, so other entities do buffers not improperly write to it while it is allocated" Rest is plain meaning de-allocating the external 17 de-allocate: "release the buffer, so other entities buffers as the may reserve it" corresponding pointers are written back to the pointer cache; Rest is plain meaning de-allocating the external 17, 51 de-allocate: "release the buffer, so other entities buffers may reserve it" Rest is plain meaning transferring an 17 de-allocate: "release the buffer, so other entities exhaustion signal if a may reserve it" number of the pointers to the de-allocated buffers reaches a minimum Rest is plain meaning threshold in response to the 17 plain meaning exhaustion signal, creating additional external buffers and their corresponding pointers where the additional external buffers are external to the integrated circuit and are configured to store the communication packets processing facilities 33 plain meaning configured to create a plurality of external buffers that are external to the integrated circuit and configured to store the communication 12 8 packets where each external buffer is associated with a pointer that corresponds to the external buffer the processing facilities 33 allocate: "reserve the buffer, so other entities do are further configured to not improperly write to it while it is allocated" … allocate the external buffers as the corresponding pointers Rest is plain meaning are read from the pointer cache allocate the external 33, 1, 34 allocate: "reserve the buffer, so other entities do buffers not improperly write to it while it is allocated" Rest is plain meaning the processing facilities 33 de-allocate: "release the buffer, so other entities are further configured to may reserve it" … de-allocate the external buffers as the corresponding pointers Rest is plain meaning are written back to the pointer cache de-allocate the external 33, 1, 34 de-allocate: "release the buffer, so other entities buffers may reserve it" Rest is plain meaning transfer an exhaustion 33 de-allocate: "release the buffer, so other entities signal if a number of the may reserve it" pointers to the de- allocated buffers reaches a minimum threshold Rest is plain meaning create additional external 33 plain meaning buffers and their corresponding pointers in response to the exhaustion signal 13 8 the processing facilities 34 allocate: "reserve the buffer, so other entities do are further configured to not improperly write to it while it is allocated" … allocate the external buffers by modifying the pointer cache to indicate Rest is plain meaning that pointers in the pointer cache corresponding to the external buffers are in use allocate the external 34, 1, 33 allocate: "reserve the buffer, so other entities do buffers not improperly write to it while it is allocated" Rest is plain meaning the processing facilities 34 de-allocate: "release the buffer, so other entities are further configured to may reserve it" … de-allocate the external buffers by modifying the pointer Rest is plain meaning cache to indicate that pointers in the pointer cache corresponding to the external buffers are unused de-allocate the external 34, 1, 33 de-allocate: "release the buffer, so other entities buffers may reserve it" Rest is plain meaning transfer an exhaustion 34 plain meaning signal if a number of the pointers in the pointer cache corresponding to the external buffers indicated to be unused reaches a minimum threshold create additional external 34 plain meaning buffers and their corresponding pointers in 14 8 response to the exhaustion signal allocating the external 51 allocate: "reserve the buffer, so other entities do buffers by modifying the not improperly write to it while it is allocated" pointer cache to indicate that pointers in the pointer cache Rest is plain meaning corresponding to the external buffers are in use allocating the external 51, 17 allocate: "reserve the buffer, so other entities do buffers not improperly write to it while it is allocated" Rest is plain meaning de-allocating the external 51 de-allocate: "release the buffer, so other entities buffers by modifying the may reserve it" pointer cache to indicate that pointers in the pointer cache Rest is plain meaning corresponding to the external buffers are unused de-allocating the external 51, 17 de-allocate: "release the buffer, so other entities buffers may reserve it" Rest is plain meaning transferring an 51 plain meaning exhaustion signal if a number of the pointers indicated to be unused reaches a minimum threshold in response to the 51 plain meaning exhaustion signal, creating additional external buffers and their corresponding pointers where the additional external buffers are 15 8 external to the integrated circuit and are configured to store the communication packets Dated: July 23, 2019 /s/ Gilbert A. Greene Gilbert A. Greene State Bar No. 24045976 Pierre J. Hubert State Bar No. 24002317 DUANE MORRIS LLP Las Cimas IV 900 S. Capital of Texas Highway, Suite 300 Austin, Texas 78746 Tel: (512) 277-2300 Fax: (512) 277-2301 BGreene@duanemorris.com PJHubert@duanemorris.com Kevin P. Anderson (Pro Hac Vice) DUANE MORRIS LLP 505 9th Street, N.W., Suite 1000 Washington, DC 20004-2166 Tel: (202) 776-7800 Fax: (202) 776-7801 KPAnderson@duanemorris.com Attorneys for NXP USA, Inc., NXP Semiconductors N.V., and NXP B.V. 16 8 CERTIFICATE OF SERVICE I hereby certify that on July 23, 2019, a true and correct copy of the forgoing was served on Plaintiff's counsel of record via electronic email at the following addresses: Andrey Belenky abelenky@kblit.com Dmitry Kheyfits dkheyfits@kblit.com Hanna G. Cohen hgcohen@kblit.comm Raymond W Mort, III raymort@austinlaw.com /s/ Gilbert A. Greene 17