Bicameral LLC v. NXP USA, Inc. et al

Western District of Texas, txwd-6:2018-cv-00294

Exhibit Ex. 331EX3

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5 Exhibit 331EX3 5 IN THE UNITED STATES PATENT AND TRADEMARK OFFICE In re U.S. Patent No. 6,321,331 to ROY et al. Confirmation No.: 3636 Art Unit: 3992 Reexam Control No.: 90/011,532 VAKA JELAJARJA KERRRAKEJKPFPJULEPJJLAJAR PJEKE Examiner: Woo H. Choi Filed: March 4, 2011 Atty. Dkt. No.: 3059.014REXO For: Real Time Debugger Interface for Embedded Systems Patent Owner's Response to Office Action of July 29, 2011 Mail Stop Ex Parte Reexam Commissioner for Patents P.O. Box 1450 Alexandria, VA 22313-1450 Sir: In reply to the Order Granting Ex Parte Reexamination dated April 8, 2011 and the Office Action dated July 29, 2011, the patent owner TR Technologies Foundation LLC ("Patent Owner") submits the following: Amendments to the Claims, which begin on page 2 of this paper; and Remarks, which begin on page 15 of this paper. It is believed that no extensions of time or other fees are required. However, if any fees are necessary to prevent abandonment of this reexamination, then such fees are hereby petitioned and hereby authorized to be charged to our Deposit Account No. 19-0036. BC_GEN_0002208 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 30. (New) A processor according to claim 29. wherein said particular event is at e ve least one of a change in status of an interrupt line, an internal processor exception, or a jump instruction based on the contents of a register. 31. (New) A processor according to claim 1. wherein said cause register means comprises a plurality of registers. 32. (New) A processor according to claim 1. wherein said debugging interface is configured to facilitate the correlation of said output of said first decoder means and the information indicated by said cause register means with actual program code being executed by said processor. 33. (New) An embedded system according to claim 11. wherein said information comprises cause information. 34. (New) An embedded system according to claim 11. wherein said information comprises processor related exception conditions and an indication of pending interrupts. 35. (New) An embedded system according to claim 34, wherein said indication of pending interrupts includes at least one of an indication of external, software, of co-processor interrupts. 36. (New) An embedded system according to claim 11. further comprising: 1418015 1 - 10 - Attorney Docket No. 3059.014REXO BC_GEN_0002217 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 e) an event history buffer means for storing information regarding processor events. said history buffer means having a data input, a data output, and an enable input. said data input being directly coupled to each of said plurality of cause register means. 37. (New) An embedded system according to claim 36, wherein said event history buffer means comprises a olurality of buffers. 38. (New) An embedded system according to claim 36. wherein said event history buffer means is configured to capture contents of said plurality of cause register means when enabled by said enable input. 39. (New) An embedded system according to claim 38. wherein said event history buffer is configured to be enabled when the contents of said plurality of cause register means indicates a particular event. 40. (New) An embedded system according to claim 29. wherein said particular event is at least one of a change in status of an interrupt line, an internal processor exception. or a jump instruction based on the contents of a register. 41. (New) An embedded system according to claim ll. wherein said cause register means comprises a plurality of registers. 42. (New) An embedded system according to claim 11. wherein said debugging interface is configured to facilitate the correlation of said output of said first decoder means 1418015 1 - 11. Attorney Docket No. 3059.014REXO BC_GEN_0002218 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 and the information indicated by said cause register means with actual program code being executed by said processor. 43. (New) A processor according to claim 21. wherein said cause information comprises processor related exception conditions and an indication of pending interrupts. 44. (New) A processor according to claim 43. wherein said indication of pending interrupts includes at least one of an indication of external software, or co-processor interrupt. 45. (New) A processor according to claim 21. further comprising: e) event history buffer means for storing information regarding processor events. said event history buffer means having a data input, a data output, and an enable input, said data input being directly coupled to said cause register means. 46. (New) A processor according to claim 45. wherein said event history buffer means is configured to capture contents of said cause register means when enabled by said enable input. 47. (New) A processor according to claim 46, wherein said event history buffer is configured to be enabled when the contents of said cause register means indicates a particular event. 1418015 1 - 12 .. Attorney Docket No. 3059.014REXO BC_GEN_0002219 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 48. (New) A processor according to claim 47, wherein said particular event is at least one of a change in status of an interrupt line, an internal processor exception, or a jump instruction based on the contents of a register. 49. (New) A processor according to claim 21. wherein said cause register means comprises a plurality of registers. 50. (New) An embedded system according to claim 22. wherein said cause information comprises processor related exception conditions and an indication of pending interrupts. 51. (New) An embedded system according to claim 50. wherein said indication of pending interrupts includes at least one of an indication of external, software, or co-processor interrupt. 52. (New) An embedded system according to claim 22. further comprising: e) an event history buffer means for storing information regarding processor events. said history buffer means having a data input, a data output, and an enable input, said data input being directly coupled to each of said plurality of cause register means. 53. (New) An embedded system according to claim 52. wherein said event history buffer means is configured to capture contents of said plurality of cause register means when enabled by said enable input. 1418015 1 - 13 - Attorney Docket No. 3059.014REXO BC_GEN_0002220 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 54. (New) An embedded system according to claim 53. wherein said event history buffer is configured to be enabled when the contents of said plurality of cause register means indicates a particular event. 55. (New) An embedded system according to claim 54. wherein said particular event is at least one of a change in status of an interrupt line, an internal processor exception. or a jump instruction based on the contents of a register. 56. (New) An embedded system according to claim 22. wherein said cause register means comprises a plurality of registers. 1418015_1 - 14- Attorney Docket No. 3059.014REXO BC_GEN_0002221 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 Remarks Issued patent claims 1-5, 11-15, and 19-22 of U.S. Patent No. 6,321,331 to Roy et al. ("Roy" or "the '331 patent") are currently subject to the present ex parte reexamination proceeding. Claims 1, 11, 21, and 22 are independent claims. In accordance with 35 U.S.C. $ 305, Patent Owner is presenting new claims 23-56. Pursuant to 37 C.F.R. 1.530(e), the status of all claims and an explanation of the support in the disclosure of the '331 patent for newly presented claims 23-56 is provided in Section I. Newly presented claims 23-56 do not enlarge the scope of the claims of the '331 patent. Based on the following remarks, and the Declaration of Michael Barr under 37 C.F.R. $ 1.132 submitted herewith ("Barr Decl."), Patent Owner respectfully requests that the Examiner reconsider and withdraw all outstanding rejections and enter, examine, and allow newly presented claims 23-56. Section 1 provides the status of all claims. Section I also presents the added claims and provides an explanation of the support in the disclosure of the '331 patent for newly presented claims 23-56. Section II provides a summary of arguments that support the allowance of all claims subject to this reexamination. Section II discusses the legal standards relevant to the issues in this reexamination. Section IV describes the differences between the applied references and the original patent claims. Section V addresses patentability of newly presented claims 23-56 over the applied references. I. STATUS OF CLAIMS Original issued patent claims 1-5, 11-15, and 19-22 stand rejected. Claims 6-10 and 16-18 are not subject to reexamination. Claims 21 and 22 have been amended to clarify their meaning. Claim 19 has been amended to change its dependency to clam 16. No other amendments have been made to original patent claims 1-22. 1418015 1 - 15 - Attorney Docket No. 3059.014REXO BC_GEN_0002222 5 Patent Owner's Response to KOY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 In accordance with 35 U.S.C. $ 305, Patent Owner seeks to add new claims 23-56. Newly presented claims 23-56 have not previously been entered by the Examiner. New claims 23-29 depend from independent claim 1, new claims 30-36 depend from independent claim 11, new claims 37-42 depend from independent claim 21, and new claims 43-48 depend from claim 22. Support for the new claims can be found, inter alia, in the original claims and in the Specification of the '331 patent at 6:16-38; 6:62 – 7:28; FIGS. 1A and 1B. The following table indicates examples of specific support for each of the new claims in the specification of the patent: Claim 23 24 25 26 WANAWAKE 27 145 Example Support Specification at 6:62 - 7:15; FIGS. 1A and 1B Specification at 7:1-3 Specification at 7:1-3 Specification at 6:16-26 Specification at 6:16-26 Specification at 6:39-42 Specification at 7:11-13 Specification at 6:31-38 Specification at 6:16-38 Specification at 7:21-28 Specification at 6:62 – 7:15; FIGS. 1A and 28 29 30 31 Yarananntanneranan ***SLLLLLLLLLLLLLLLLLLLLLLL 32 33 | 1B 34 35 36 37 38 Specification at 7:1-3 Specification at 7:1-3 Specification at 6:16-26 Specification at 6:16-26 Specification at 6:39-42 Specification at 7:11-13 Specification at 6:31-38 Specification at 6:16-38 Specification at 7:21-28 39 40 www 41 42 1418015 1 - 16. Attorney Docket No. 3059.014REXO BC_GEN_0002223 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 43 ཁན་ཁག་མཁན མ ཏགགཧཧཧརཱསཱཝནཏ༣ སཱརཱབཱདྷ ནསཱཧསཱན ཝཱརཱན ར ར ཏ སྙན་ 44 45 46 47 48 49 Specification at 7:1-3 Specification at 7:1-3 Specification at 6:16-26 Specification at 6:39-42 Specification at 7:11-13 Specification at 6:31-38 Specification at 6:16-38 Specification at 7:1-3 Specification at 7:1-3 Specification at 6:16-26 Specification at 6:39-42 | Specification at 7:11-13 Specification at 6:31-38 Specification at 6:16-38 50 51 52 53 54 BLOGOGORO 55 56 cocco No new matter has been added by any of the claim amendments or new claims. Accordingly, the Patent Owner respectfully requests the entry of the claim amendments and the new claims. II. SUMMARY OF ARGUMENTS The Office Action rejected claims 1-5, 11-15, 19, and 20 under 35 U.S.C. § 103(a) as unpatentable under the combination of U.S. Patent No. 5,996,092 to Augsburg et al. ("Augsburg") in view of IBM PowerPC 403GA User's Manual, Second Edition, March 1995, [online], [retrieved on 2011-2-9) Retrieved using internet http://i.want.to.surf.free.fr/NCD/HTML/403gaum.pdf ("the IBM Manual"), and U.S. Patent No. 5,361,348 to Nakamoto ("Nakamoto"). Additionally, the Office Action rejected claims 21 and 22 under 35 U.S.C. § 103(a) as unpatentable over the combination of Augsburg and the IBM Manual. The Patent Owner respectfully disagrees. 1418015 1. 17 - Attorney Docket No. 3059.014REXO BC_GEN_0002224 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 Claims 21 and 22 With respect to claims 21 and 22, the combination of Augsburg and the IBM Manual fails to disclose or suggest each and every feature of the claimed invention. As amended herein, both claims 21 and 22 recite, among other features, a "cause register means for indicating cause information regarding interrupts and exceptions." The Office Action acknowledges that Augsburg does not teach or disclose the cause register means feature, but alleges that the IBM Manual remedies this deficiency. Specifically, the Office Action relies on the Machine State Register (MSR) and the External Interrupt Status Register (EXISR) to allegedly show the claimed cause register means. However, neither the MSR nor the EXISR teach or disclose a "cause register means for indicating cause information regarding interrupts and exceptions," as recited in claim 21 and similarly in claim 22. The EXISR fails to teach, disclose or suggest this element, because the EXISR only indicates information about external interrupts, and not about exceptions. The MSR fails to teach, disclose or suggest this element, because it does not indicate cause information regarding interrupts or exceptions. Rather, the MSR acts as a switch to allow a user to enable or disable certain interrupts and exceptions by setting the value of certain bits. Thus, the MSR provides no cause information regarding interrupts or exceptions, but rather simply functionality enabling user settings of exceptions and interrupts. Accordingly, neither the MSR nor the EXISR functions as the claimed cause register means. Thus, the combination of Augsburg and the IBM Manual fails to disclose or suggest each and every claimed feature. The rejection of claims 21 and 22 is, therefore, improper and should be withdrawn. Claims 1-5. 11-15, 19, and 20 With respect to claims 1-5, 11-15, 19, and 20, the combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest each and every claimed feature. For 1418015 1 - 18 - Attorney Docket No. 3059.014REXO BC_GEN_0002225 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 instance, independent claims 1 and 11 recite (a) "a cause register means for indicating information regarding interrupts and exceptions," (b) "first decoder means being directly coupled to said instruction memory means, said program counter means, and said cause register means," and (c) "program counter means directly coupled to said instruction memory means for indexing instructions." First, the combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest a cause register means for indicating information regarding interrupts and exceptions. As was the case for claims 21 and 22, the Office Action relies on the MSR and EXISR discussed in the IBM Manual to show this claimed feature. However, for reasons similar to those discussed above, the IBM Manual's MSR and EXISR actually fail to perform the function of a cause register means and are, therefore, not analogous. As discussed above. both the MSR and EXISR do not provide information regarding interrupts and exceptions. As discussed above, the MSR acts as a switch to allow a user to enable or disable certain interrupts and exceptions by setting the value of certain bits. Thus, it only provides functionality enabling user settings for interrupts and exceptions. Accordingly, a person of ordinary skill in the art would not understand the IBM Manual to disclose the claimed cause register means. Like Augsburg and the IBM Manual, Nakamoto also fails to disclose or suggest the claimed cause register means. Accordingly, the combination of Augsburg, the IBM Manual, and Nakamoto, lacks this claimed feature. Second, the combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest the claimed decoder means directly coupled to the instruction memory means, program counter means, and cause register means. The Office Action relies on Nakamoto's FIG. 2 to show this claimed feature. Specifically, the Office Action alleges that the claimed feature is taught because Nakamoto shows an instruction decoder and timing controller 3 that is directly coupled to the program memory 2, the PC1, and the latch register 1418015 1 i 19. Attorney Docket No. 3059.014REXO BC_GEN_0002226 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 6. As initial matter, even if Nakamoto did show a direct connection between these components, Nakamoto would still fail to show this claimed feature because it does not disclose a first decoder, so it cannot show any features directly coupled to it. The Office Action alleges that the instruction decoder and timing controller 3 is analogous to the claimed first decoder. However, the instruction decoder and timing controller 3 is entirely different from the claimed first decoder. Specifically, the "instruction decoder and timing controller 3" is used during the execution of the current instruction rather than for providing information regarding activity of the processor in real time, as recited by the claims. In addition to failing to show a first decoder, as noted above, Nakamoto fails to show a cause register. Accordingly, even if Nakamoto were to show a first decoder, it would still fail to disclose or suggest directly coupling the first decoder to the cause register means, as recited by the claims. The combination of Augsburg, the IBM Manual, and Nakamoto, therefore, lacks this claimed feature. Third, with regard to the program counter directly coupled to the instruction memory, the Office Action again relies on Nakamoto's FIG. 2 to show this feature. Within the context of Roy, directly coupled means two elements are directly coupled if they are connected to each other with no components in between them. Nakamoto's FIG. 2 does not teach direct coupling. Instead. Nakamoto explains that the program counter and the program memory shown in FIG. 2 are indirectly coupled through an internal bus. Accordingly, a person of ordinary skill in the art would not understand Nakamoto to disclose or suggest a program counter directly coupled to an instruction memory. Thus, since the combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest each and every claimed feature, the rejection of claims 1-5, 11-15, 19, and 20 is improper and should be withdrawn. 1418015 1 - 20 - Attorney Docket No. 3059.014REXO BC_GEN_0002227 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 III. REVIEW OF LEGAL STANDARDS GOVERNING THE REJECTIONS Standard of Review The standard of review for determining patentability is "preponderance of the evidence." (MPEP 706.I.) The examiner must weigh the evidence presented for and against patentability and if it is more likely than not that the claims are patentable, they must be allowed. (Id.) Patentability is determined through the lens of one having ordinary skill in the art at the time the application was filed. Phillips v. AWH Corp., 415 F.3d 1303, 1316 (Fed. Cir. 2005) (en banc). Further, the scope of the claims in patent applications is to be determined "not solely on the basis of the claim language, but upon giving claims their broadest reasonable construction 'in light of the specification as it would be interpreted by one of ordinary skill in the art." (Id.) (quoting In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004)). Claim Construction Despite the fact that patent owners in reexamination do not have the same freedom to amend claims as applicants do during regular prosecution, the Office nonetheless uses the "broadest reasonable interpretation" standard during reexamination. (MPEP $ 2258(1)(G); see also In re Trans Texas Holdings, Corp., 498 F.3d 1290, 1292 (Fed. Cir. 2007). But use of the broadest reasonable construction standard is not an unfettered license to ignore the specification and the perspective of the skilled artisan. Even under that rubric, the Office must interpret "the scope of claims ... not solely on the basis of the claim language, but upon giving claims their broadest reasonable interpretation 'in light of the specification as it would be interpreted by one of ordinary skill in the art.' (MPEP $ 2111; citing Phillips v. AWH 1418015 1 - 21- Attorney Docket No. 3059.014REXO BC_GEN_0002228 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 Corp., 415 F.3d 1303, 75 USPQ2d 1321 (Fed. Cir. 2005)) (emphasis added); see also, In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). Indeed, the Federal Circuit has stated that the "PTO applies to verbiage of the proposed claims the broadest reasonable meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art, taking into account whatever enlightenment by way of definitions or otherwise that may be afforded by the written description contained in applicant's specification." In re Morris, 127 F.3d 1048, 1054-55 (Fed. Cir. 1997). For instance, in In re Buszard, the Federal Circuit found the PTO's alleged "broadest reasonable interpretation" to be unreasonable where the claims and the specification specifically supported the applicant's construction and were contrary to the Office's construction. In re Buszard, 504 F.3d 1364, 1367 (Fed. Cir. 2007). Similarly, in In re Cortright, the Federal Circuit found the PTO's broad interpretation of the term "restoring hair growth" to be unreasonable because it was inconsistent with the disclosure. See In re Cortright. 165 F.3d 1353. 1359 (Fed. Cir. 1999). It is thus well settled that under the "broadest reasonable interpretation" standard, the Office is still required to interpret the claims in a reasonable manner and in light of the specification. The premise for the broadest reasonable interpretation standard is that claims can be readily amended during prosecution of an application. This claim construction standard has been extended to prosecution during reexaminations because patent owners are ostensibly free to amend claims. However, the freedom of patent owners to amend claims is not practical where the claims under reexamination are involved in simultaneous district court and/or ITC litigation. The reasons are many. First, the doctrine of intervening rights may cut 'MPEP 8 706.I. ("The standard to be applied in all cases is the 'preponderance of the evidence' test. In other words, an examiner should reject a claim if, in view of the prior art and evidence of record, it is more likely than not that the claim is unpatentable."). 1418015 1 - 22 - Attorney Docket No. 3059.014REXO BC_GEN_0002229 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 off past damages where claims are substantively amended. 35 U.S.C. $$ 307(b) and 316(b). Second, the parties may have expended considerable resources in Markman hearings- resources that could be effectively wasted if the claims are substantively amended. Third, because different claim construction standards are applied by the two bodies charged with determining patent validity, the patent owner is often faced with a Hobson's choice of taking inconsistent claim positions during one or the other proceedings.Put simply, patent owners are often not free to amend claims in the same way as patent applicants during original prosecution. For all of these reasons, the CRU should interpret "broadest reasonable interpretation" in view of these very real issues faced by Patent Owner in this case and rigidly adhere to the guidelines set forth by the Federal Circuit that the claims must be interpreted in light of the specification as understood by a person of ordinary skill in the art and not in a vacuum. Obviousness "A patent may not be obtained ... if the differences between the subject matter sought to be patented and the subject matter as a whole would have been obvious at the time the invention was made to a person of ordinary skill in the art to which the subject matter pertain." 35 U.S.C. $103(a). In KSR Int'l v. Teleflex 550 U.S. 398 (2006), the Supreme Court reaffirmed its decision in Graham v. John Deere that held that "the scope and content of the prior art (must] be determined; differences between the prior art and the claims at issue 2 However, when a patent owner loses their ability to amend the claims (e.g., when a patent term expires during the reexamination proceeding), the standard for claim construction moves from the broadest reasonable interpretation standard to a standard "pursuant to the principle set forth by the court in Phillips v. AWH Corp., 415 F.3d 1303, 1316, 75 USPQ2d 1321, 1329 (Fed. Cir. 2005)(words of a claim 'are generally given their ordinary and customary meaning' as understood by a person of ordinary skill in the art in question at the time of the invention)." MPEP 82258.I.G. 1418015 1 - 23 Attorney Docket No. 3059.014REXO BC_GEN_0002230 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 [must] be ascertained; and the level of ordinary skill in the pertinent art (must be] resolved" in order to support a finding of obviousness. Graham v. John Deere Co., 383 U.S. 1, 17 (1966). Graham also set forth "secondary considerations" relevant to nonobviousness such as "commercial success, long felt but unsolved needs, [and] failure of others." Id. at 17-18. To guard against impermissible hindsight, the Office must fully articulate its obviousness rejections. See In re Kahn, 441 F.3d 977, 986 (Fed. Cir. 2006). For instance, the Examiner may not use the challenged claims as a roadmap on how or why to combine references. Instead, the Examiner must rely solely on the prior art teachings and knowledge of a person of ordinary skill at the time the invention was made to determine whether an invention is obvious. See id.; see also MPEP 2145.X.A. For this reason, obviousness analysis is not an armchair exercise. If a person of skill in the art would not have identified the proposed combination, or if the proposed modification would have been inoperable, a conclusion of obviousness is improper. Further, "[i]f [a) proposed modification would render the prior art invention being modified unsatisfactory for its intended purpose, then there is no suggestion or motivation to make the proposed modification." MPEP 2143.01.V. Using these legal standards, each of the substantive rejections in the Office Action is addressed below in the order they were presented in the Office Action. IV. RESPONSE TO SUBSTANTIVE REJECTIONS A. Substance of the Interview The Patent Owners would like to thank Examiners Choi, Ferris, and Escalante for taking the time to conduct an interview on September 7, 2011. In attendance for the Patent Owners were: Michael Barr Donald Coulman (Reg. No. 50,406) Tim Seeley (Reg. No. 53,575) Technical Expert Patent Owner's Representative Patent Owner's Representative 1418015 1 - 24 - Attorney Docket No. 3059.014REXO BC_GEN_0002231 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 John Curry (Reg. No. 65,067) Lori Gordon (Reg. No. 50,633) Ameet Modi Michael Specht (Reg. No. 54,463) Michael Stadnick Robert Sterne (Reg. No. 28,912) Sterne, Kessler, Goldstein & Fox PLLC Sterne, Kessler, Goldstein & Fox PLLC Desmarais LLP Sterne, Kessler, Goldstein & Fox PLLC Desmarais LLP Sterne, Kessler, Goldstein & Fox PLLC During the interview, the Patent Owners presented the information contained in the slides that are attached as Exhibit 1 to this paper. The information contained in the slides discussed during the interview is reflected in the following remarks. B. Independent Claims 21 and 22 are Patentable Over the Combination of Augsburg and the IBM Manual. . The Office Action rejected claims 21 and 22 under 35 U.S.C. § 103(a) as allegedly obvious over U.S. Patent No. 5,996,092 to Augsburg et al. ("Augsburg") in view of IBM PowerPC 403GA User's Manual, Second Edition, March 1995, [online], [retrieved on 2011- 2-9] Retrieved using internet http://i.want.to.surf.free.fr/NCD/HTML/403gaum.pdf ("the IBM Manual"). The Patent Owner traverses the rejection because claims 21 and 22 recite subject matter neither taught, disclosed, nor suggested by the combination of Augsburg and the IBM Manual. For instance, neither Augsburg nor the IBM Manual teaches, discloses, or suggests the claimed feature of a "cause register means for indicating cause information regarding interrupts and exceptions." As explained by Roy, "[t]he cause registers store current information about interrupts, exceptions, and other processor functions." (Roy, 4:18-20). The specific kind of information stored in the cause register is explained in the context of storing the cause register information in bits 40-18 of the history buffer 14. (Roy, 6:39 - 7:10). As Roy explains, "bit locations 39 through 35 are used to store processor related exception conditions" and "[b]it locates 34 through 18 are used to store an indication of all pending interrupts (external, 1418015 1 - 25 - Attorney Docket No. 3059.014REXO BC_GEN_0002232 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 software, co-processor)." (Id.). Accordingly, the causc register performs at least two important functions, namely, it stores cause information about (a) exception conditions; and (b) the pending interrupts. (Barr Decl. at 1 42). This cause information can be used by the debugger to determine the reasons why the software left the normal path of software execution. (Barr Decl. at 4 42). Because Augsburg lacks any disclosure of a cause register, the Office Action relies on the IBM Manual to show this claimed feature. (Barr Decl. at 1148 and 56). Specifically, the Office Action alleges that the IBM Manual teaches the cause register feature because it teaches "a machine state register (MSR) and/or an external interrupt status register (EXISR) for indicating information regarding interrupts and exceptions." (Office Action at p. 4). However, neither the MSR nor the EXISR is a cause register. (Barr Decl. at 911 56-59) The EXISR differs from the claimed cause register because, among other things, the EXISR does not store cause information regarding interrupts and exceptions. (Barr Decl. at 58). The EXISR only contains information relating to the status of external interrupts. (IBM Manual at p. 6-9). Specifically, the IBM Manual explains that the EXISR contains the status of five external hardware interrupts. (Id.) The EXISR, however, contains no information concerning internal interrupts, co-processor interrupts, software interrupts, or exceptions. (Barr Decl. at 9 59). Thus, a person of ordinary skill in the art would not view the EXISR to be the equivalent of a "cause register means for indicating cause information regarding interrupts and exceptions," as recited by claim 21. (Barr Decl. at 958). The MSR differs from the claimed cause register because it does not indicate cause information regarding interrupts and exceptions. (Barr Decl. at 7 59). The IBM Manual discloses that the MSR consists of control bits that enable groups of interrupts and exceptions, among other things. (Id.). These control bits provide no information about the interrupts and exceptions - they are more correctly viewed as switches for turning the 1418015 1 - 26 - Attorney Docket No. 3059.014REXO BC_GEN_0002233 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 interrupts and exceptons on and off. (Id.). Thus, while the MSR allows the user to control which interrupts and exceptions are enabled, it does not contain any information concerning the cause of a program's deviation from the normal path of software execution. (Id.). Accordingly, the MSR does not teach, disclose or suggest the claimed cause register means. (Id.). Since neither Augsburg nor the IBM Manual discloses or suggests a cause register means for indicating cause information regarding interrupts and exceptions, the rejection of claim 21 is improper and should be withdrawn. The rejection of claim 22, which recites. similar features, is improper and should be withdrawn for at least the same reason. The Patent Owner, therefore, respectfully requests the withdrawal of the rejection of claims 21 and 22. C. Claims 1-5, 11-15, and 19-20 are Patentable Over the Combination of Augsburg, the IBM Manual, and Nakamoto. The Office Action rejected claims 1-5, 11-15, and 19-20 under 35 U.S.C. § 103(a) as allegedly unpatentable over the combination of Augsburg, the IBM Manual, and U.S. Patent No. 5,361,348 to Nakamoto ("Nakamoto). Patent Owners traverse the rejection because claims 1-5, 11-15, and 19-20 recite subject matter neither disclosed nor suggested by the combination of Augsburg, the IBM Manual, and Nakamoto. Augsburg, the IBM Manual, and Nakamoto Fail to Disclose or Suggest a Cause Register Means for Indicating Information Regarding Interrupts and Exceptions. The combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest the claimed "cause register means for indicating information regarding interrupts and 1418015 1 - 27 - Attorney Docket No. 3059.014REXO BC_GEN_0002234 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 exceptions." Based on the arguments above, neither Augsburg nor the IBM Manual discloses or suggests this claimed feature. Nakamoto, which the Office Action cites for its purported disclosure of other features, fails to remedy the deficiencies that Augsburg and the IBM Manual share with respect to the claimed invention. Namely Nakamoto at least fails to disclose or suggest the claimed cause register means. (Barr Decl. at 9 62). The Office Action, however, appears to suggest an equivalence between Nakamoto's latch register 6 and the claimed cause register at one point. (Office Action at 12). The Patent Owner respectfully disagrees. This false equivalence appears to stem from a misreading of Nakamoto – specifically the box labeled 302 that appears in FIG. 3, in which the word "cause" happens to appear adjacent to the word "register." (Office Action at 12). Box 302 of FIG 3, however, has nothing to do with anything even remotely similar to the claimed "cause register." As previously noted, a cause register indicates information regarding interrupts and exceptions. (Barr Decl. at 1 62). The latch register 6 does none of this. (Id.). Nakamoto does not contain anything called a "cause register." (Id.). Instead, box 302, read properly, simply explains that the instruction decoder and timing controller 3 generates a data latch control signal (DLCS) 4, which causes the latch register 6 to latch the accessed data. (Nakamoto, 3:31-34). That is, in Nakamoto, the word "cause" is used as a verb whereas in the patented claims, the word "cause" is used as an adjective. (Id.). Thus, like Augsburg and the IBM Manual, Nakamoto fails to disclose or suggest the claimed "cause register means for indicating information regarding interrupts and exceptions." 1418015 1 - 28 - Attorney Docket No. 3059.014REXO BC_GEN_0002235 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 Augsburg, the IBM Manual, and Nakamoto Fail to Disclose or Suggest a First Decoder Means Being Directly Coupled to Said Instruction Memory Means, Said Program Counter Means, and Said Cause Register Means. The combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest a "first decoder means being directly coupled to said instruction memory means, said program counter means, and said cause register means," as recited by independent claim 1. To show this feature, the Office Action mistakenly relies on Nakamoto, which purportedly teaches "an instruction decoder and timing controller that is directly coupled to the program memory 2, the PC1, and, e.g., the latch register 6." (Office Action at p. 12). First, Nakamoto fails to disclose or suggest a first decoder means at all, so it cannot disclose a first decoder means directly coupled to anything. Apart from the use of the word "decoder" in describing them, the instruction decoder and timing controller 3 and the claimed first decoder share very little in common. (Barr Decl. at 1 61). As explained by Roy, "the decoder 28 is arranged to indicate whether the program counter has moved its point to a new instruction." (Roy, 4:29-31). That indication, which corresponds to processor activity in the previous cycle, is provided by the three bit output of the first decoder 28. (Roy, 4:26-29). To that end, the claims recite a first decoder with a first output that "provides information regarding activity of said processor in real time." (Roy, 8:22-24). Nakamoto's "instruction decoder and timing controller" does something entirely different than the claimed first decoder means. (Barr Decl. at 1 61). Instead of providing an indication of processor activity during a previous clock cycle, Nakamoto's "instruction decoder and timing controller 3" is integral to performing the current instruction because it produces the DLCS and PCCS control signals, which control the latch register 6 and the program counter, respectively. (Id.) As explained by Nakamoto, the "instruction decoder and timing controller 3 decodes... instructions to provide a control signal 31 necessary to 1418015 1 - 29- Attorney Docket No. 3059.014REXO BC_GEN_0002236 5 Amendments to the Claims A listing of each claim under reexamination is provided below. The Patent Owner provides this listing of original patent claims 1-22 from the U.S. Patent No. 6,321,331 and a listing of newly presented claims 23-48. 1. (Original Patent Claim) A processor having a real time debugging interface, said processor comprising: a) instruction memory means for storing instructions to be executed by said processor; b) program counter means directly coupled to said instruction memory means for indexing said instructions; c) cause register means for indicating information regarding interrupts and exceptions; and d) first decoder means for indicating information about an instruction executed by said processor during a clock cycle, said first decoder means being directly coupled to said instruction memory means, said program counter means, and said cause register means, said first decoder means having a first output, wherein said first output provides information regarding activity of said processor in real time. 2. (Original Patent Claim) A processor according to claim 1, said information regarding processor activity includes information as to at least one of a jump instruction has been executed, a jump instruction based on the contents of a register has been executed, a branch has been taken, and an exception has been encountered. BC_GEN_0002209 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 3. (Original Patent Claim) A processor according to claim 1, wherein: said clock cycle is a processor clock cycle, and said first decoder means updates said information about each instruction executed by said processor for each said processor clock cycle. 4. (Original Patent Claim) A processor according to claim 3, wherein: said information about each instruction executed by said processor includes an indication whether or not an instruction has been executed since the previous processor cycle. 5. (Original Patent Claim) A processor according to claim 1, wherein: said first output consists of a three bit parallel output. 6. (Original Patent Claim) A processor according to claim 1, further comprising: e) second decoder means directly coupled to said cause register means for indicating information about contents of said cause register means, said second decoder means having a second output; and f) event history buffer means for storing information regarding processor events, said event history buffer means having a data input, a data output, and an enable input, said data input being directly coupled to said cause register means and said enable input being directly coupled to said second output, wherein said second decoder means decodes contents of said cause register means and enables said event history buffer means to capture contents of said cause register means when contents of said cause register means indicate a particular event. 7. (Original Patent Claim) A processor according to claim 6, wherein: said second decoder means enables said event history buffer means when contents of said cause 1418015 1 - 3. Attorney Docket No. 3059.014REXO BC_GEN_0002210 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 execute the instructions." (Nakamoto, 3:18-20). The "instruction decoder and timing controller 3" is, therefore, very different from the claimed first decoder. (Barr Decl. at 61). Accordingly, even if Nakamoto were to disclose direct coupling between its instruction decoder and timing controller 3 and various other components, it would still not disclose the claimed "first decoder means being directly coupled to said instruction memory means, said program counter means, and said cause register means" because Nakamoto's instruction decoder and timing controller 3 is totally different from the claimed first decoder means. (Id.). Additionally, even if Nakamoto were to disclose the claimed first decoder, it would still fail to disclose or suggest a "first decoder means being directly coupled... to said cause register means." (Barr Decl. at 1 63). This is because, as noted above, Nakamoto, like Augsburg and the IBM Manual, fails to disclose or suggest a cause register means as claimed. (Id.). Thus, it could not disclose or suggest first decoder means coupled to said cause register means, as recited by the claims. iii. Augsburg, the IBM Manual, and Nakamoto Fail to Disclose or Suggest a Program Counter Means Directly Coupled to said Instruction Memory Means. The combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest a "program counter means directly coupled to said instruction memory means for indexing said instructions," as recited by claim 1. The Office Action relies on Nakamoto to show this claimed feature. (Office Action at 10). Patent Owner submits that this reliance is misplaced. Nakamoto shows a number of elements that comprise the signal processor 100 with various lines and arrows showing logical connections between them. (Barr Decl. at 11 53- 55). The logical connections shown in FIG. 2 show how the various components of the 14180151 -30 - Attorney Docket No. 3059.014REXO BC_GEN_0002237 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 processor interact with each other logically. (Id.). The logical connections depicted in FIG. 2, however, provide little insight into how the components of processor 100 physically couple to one another. (Id.). Nakamoto, however, succinctly describes how the components are physically coupled to each other: ta The signal processor 100, which is fabricated as a semiconductor integrated circuit device, comprises a program memory 2 which stores a program a program counter (PC) 1 which designates addresses where instructions to be carried out in the program are stored, an arithmetic logical processing unit (ALU) 14, a register set 15 which includes an accumulator and a temporary register, a data memory 16 which stores data temporarily, and a debug circuit 50. These components are connected with each other through an internal bus 5. (Nakamoto, 5:27-28) (emphasis added). Thus, Nakamoto discloses connecting the various components of its signal processor 100 via an internal bus 5. In contrast to Nakamoto, the claimed program counter means is directly coupled to the claimed instruction memory means. (Barr Decl. at (65). As is clear in the context of the initial prosecution of the Roy patent, directly coupled has a very particular and specific meaning: two elements are directly coupled to one another if they are connected to each other without any intermediate elements between them. (Id.). An internal bus, such as the one described by Nakamoto, constitutes an intermediate element. (Id.). This exact issue was actually already decided during the initial prosecution of this patent. During the initial prosecution, the original claims recited various elements "connected" to one another. (Barr Decl. at 19 43-45). The Examiner cited U.S. Patent No. 5,473,754 to Folwell et al. to show the claimed "connection." (Id.). Specifically, the Examiner indicated that Folwell showed a first decoder and instruction memory that were connected via a program data bus 24. (Id.). At the time, the Examiner noted that amending the term "connected" to "directly coupled" would overcome the rejection based on Folwell's disclosed connection of the first decoder and instruction memory via the program data bus. 14180151 -31 - Attorney Docket No. 3059.014REXO BC_GEN_0002238 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 (Id.). Applicant amended the claims to recite "directly coupled" and the claims were allowed. (Id.). Thus, "directly coupled" overcame a rejection based on a similar bus during the initial prosecution. (Id.). A person of ordinary skill in the art would, therefore, not view two circuit components connected via a bus to be directly coupled as recited by the claims. (Id.). A person of ordinary skill in the art would, therefore not understand Nakamoto to disclose direct coupling of the program counter to the program memory, but, at best, indirect coupling since Nakamoto describes that they are connected via an internal bus 5. (Barr Decl. at 65). The combination of Augsburg, the IBM Manual and Nakamoto, therefore, still fails to disclose or suggest the claimed program memory "directly coupled" to a program counter. (Barr Decl. at 68). iv. Because Augsburg, the IBM Manual, and Nakamoto Fail to Disclose or Suggest each and every claimed elements, the rejections should be withdrawn. Independent claim 1 recites, amongst other things, (a) "cause register means for indicating information regarding interrupts and exceptions," (b) a "first decoder means being directly coupled to said instruction memory means, said program counter means, and said cause register means," and (c) "a program counter means directly coupled to said instruction memory means." As discussed above, the combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest these features of claim 1. Claim 1 is, therefore, patentable over the combination of Augsburg, the IBM Manual, and Nakamoto and the rejection of claim 1 is improper and should be withdrawn. Dependent claims 2-5 depend from claim 1 and are patentable for at least the same reasons as well as for the additional features they recite. The Patent Owner, therefore, respectfully requests the withdrawal of the rejection of claims 1-5. 1418015 1 - 32 - Attorney Docket No. 3059.014REXO BC_GEN_0002239 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 Similar to claim 1, independent claim 11 recites, among other things (a) "a plurality of cause register means for indicating information regarding interrupts and exceptions for a corresponding one of said plurality of processors, each of said cause register means being directly coupled to a respective one of said processors," and (b) a "a plurality of first decoder means, each said first decoder means directly coupled to a respective one of said instruction memory means, to a respective one of said program counter means, and respective one of said cause register means," and (c) "a plurality of program counter means, each directly coupled to a respective one of said plurality of instruction memory means." As discussed above, the combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest these features of claim 11. Claim 11 is, therefore, patentable over the combination of Augsburg, the IBM Manual, and Nakamoto and the rejection of claim 11 is improper and should be withdrawn. Dependent claims 12-15 and 19-20 depend from claim 11 and are patentable for at least the same reasons as well as for the additional features they recite. The Patent Owner, therefore, respectfully requests the withdrawal of the rejection of claims 11-15 and 19-20. V. NEWLY PRESENTED CLAIMS 23-46 ARE PATENTABLE OVER THE CITED REFERENCES Newly presented claims 23-56 depend either directly or indirectly from one of independent claims 1, 11, 21, and 22 and are patentable for at least the same reasons stated above with respect to claims 1, 11, 21, and 22 as well as for the additional features they recite. The Patent Owner, therefore, respectfully requests that the Office enter the new claims and pass them to issue. 1418015 1 - 33 - Attorney Docket No. 3059.014REXO BC_GEN_0002240 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 VI. CONCLUSION All of the stated grounds of rejection have been properly traversed, accommodated, or rendered moot. The Patent Owner therefore respectfully requests that the Examiner reconsider all presently outstanding rejections and that they be withdrawn. The Patent Owner believes that a full and complete reply has been made to the outstanding Office Action and that the claims under reexamination are allowable over the rejections presented in the Office Action. Prompt and favorable consideration of this Reply is respectfully requested. Respectfully submitted, STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C. vill Do It Michael D. Specht Attorney for Patent Owner Registration No. 54,463 John H. Curry Attorney for Patent Owner Registration No. 65,067 Date: Sep. 27, 2011 1100 New York Avenue, N.W. Washington, D.C. 20005-3934 (202) 371-2600 14180151 1418015 1 - 34 - Attorney Docket No. 3059.014REXO BC_GEN_0002241 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 register means indicate an event including at least one of a change in status of an interrupt line, an internal processor exception, and a jump instruction based on the contents of a register. 8. (Original Patent Claim) A processor according to claim 6, wherein: said data output of said event history buffer means is a bit serial output. 9. (Original Patent Claim) A processor according to claim 6, wherein: said processor is embodied on a chip having a plurality of pins, said first output and said data output are provided via some of said plurality of pins. 10. (Original Patent Claim) A processor according to claim 9, wherein: said first output is an n-bit parallel output, and said data output is a serial output. 11. (Original Patent Claim) An embedded system having a plurality of processors and a real time debugging interface, said system comprising: a) a plurality of instruction memory means for storing instructions to be executed by a respective one of said plurality of processors; b) a plurality of program counter means, each directly coupled to a respective one of said plurality of instruction memory means for indexing contents of said instruction memory means; c) a plurality of cause register means for indicating information regarding interrupts and exceptions for a corresponding one of said plurality of processors, each of said cause register means being directly coupled to a respective one of said processors; and 1418015 1 - 4- Attorney Docket No. 3059.014REXO BC_GEN_0002211 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 d) a plurality of first decoder means, each said first decoder means directly coupled to a respective one of said instruction memory means, to a respective one of said program counter means, and a respective one of said cause register means, each said first decoder means for indicating information about an instruction executed during a clock cycle by a respective one of said processors, each said first decoder means having a first output, wherein each said first output provides information regarding activity of said processor in real time. 12. (Original Patent Claim) An embedded system according to claim 11, wherein: said information regarding processor activity includes information as to at least one of a jump instruction has been executed, a jump instruction based on the contents of a register has been executed, a branch has been taken, and an exception has been encountered. 13. (Original Patent Claim) An embedded system according to claim 11, wherein: said clock cycle is a processor clock cycle, and each said first decoder means updates said information about each instruction executed by a respective processor for each said processor clock cycle of said respective processor. 14. (Original Patent Claim) An embedded system according to claim 13, wherein: each said information about each instruction executed by a respective processor includes an indication whether or not an instruction has been executed since the previous processor cycle of said respective processor. 15. (Original Patent Claim) An embedded system according to claim 11, wherein: each of said first outputs consists of a three bit parallel output. 14180151 -5. Attorney Docket No. 3059.014REXO BC_GEN_0002212 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 16. (Original Patent Claim) An embedded system according to claim 11, further comprising: e) a plurality of second decoder means, each directly coupled to a respective one of said plurality of cause register means, each said second decoder means for indicating information about contents of a respective cause register means; and f) an event history buffer means for storing information regarding processor events, said history buffer means having a data input, a data output, and an enable input, said data input being directly coupled to each of said plurality of cause register means and said enable input being directly coupled to each of said second outputs, wherein each of said second decoder means decodes contents of a respective cause register means and enables said event history buffer to capture contents of said respective cause register means when contents of said respective cause register means indicate a particular event. 17. (Original Patent Claim) An embedded system according to claim 16, wherein: each said second decoder means enables said event history buffer means when contents of a respective cause register means indicate an event including at least one of a change in status of an interrupt line, an internal processor exception, and a jump instruction based on the contents of a register. 18. (Original Patent Claim) An embedded system according to claim 16, wherein: said data output of said event history buffer means is a bit serial output. 1418015 1 -6- Attorney Docket No. 3059.014REXO BC_GEN_0002213 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 19. (Currently Amended) An embedded system according to claim [11] 16, wherein: said system is embodied on a chip having a plurality of pins, said first and second outputs are provided via some of said plurality of pins. 20. (Original Patent Claim) An embedded system according to claim 19, wherein: each of said first outputs is an n-bit parallel output, and said second output is a serial output. 21. (Currently Amended) A processor having a real time debugging interface, said processor comprising: a) instruction memory means for storing instructions to be executed by said processor; b) program counter means coupled to said instruction memory means for indexing said instructions; c) cause register means for indicating cause information regarding interrupts and exceptions; and d) first decoder means for indicating information about an instruction executed by said processor during a clock cycle, said first decoder means being coupled to said instruction memory means, said program counter means, and said cause register means, said first decoder means having a first output, wherein said first output provides information regarding activity of said processor in real time, said clock cycle is a processor clock cycle, said first decoder means updates said information about each instruction executed by said processor for each said processor clock cycle, and said information about each instruction executed by said processor includes an indication whether or not an instruction has been executed since the previous processor cycle. 14180151 -7- Attorney Docket No. 3059,014REXO BC_GEN_0002214 5 Patent Owner's Response to Office Action dated July 29, 2011 ROY et al. Reexamination Control No. 90/011,532 22. (Currently. Amended) An embedded system having a plurality of processors and a real time debugging interface, said system comprising: a) a plurality of instruction memory means for storing instructions to be executed by a respective one of said plurality of processors; b) a plurality of program counter means, each coupled to a respective one of said plurality of instruction memory means for indexing contents of said instruction memory means, c) a plurality of cause register means for indicating cause information regarding interrupts and exceptions for a corresponding one of said plurality of processors, each of said cause register means being coupled to a respective one of said processors; and d) a plurality of first decoder means, each said first decoder means coupled to a respective one of said instruction memory means, to a respective one of said program counter means, and a respective one of said cause register means, each said first decoder means for indicating information about an instruction executed during a clock cycle by a respective one of said processors, each said first decoder means having a first output, wherein cach said first output provides information regarding activity of said processor in real time, said clock cycle is a processor clock cycle, each said first decoder means updates said information about each instruction executed by a respective processor for each said processor clock cycle of said respective processor, and each said information about each instruction executed by a respective processor includes an indication whether or not an instruction has been executed since the previous processor cycle of said respective processor. 1418015_1 - 8- Attorney Docket No. 3059.014REXO BC_GEN_0002215 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 23. (New) A processor according to claim 1. wherein said information comprises cause information. 24. (New) A processor according to claim 1. wherein said information comprises processor related exception conditions and an indication of pending interrupts. * *********** 25. (New) A cirocessor according to claim 24, wherein said indication of pending interrupts includes at least one of an indication of external software, or co-processor interrupt. 26. (New) A processor according to claim 1, further comprising e) event history buffer means for storing information regarding processor events, said event history buffer means having a data input, a data output, and an enable input, said data WALL- input being directly coupled to said cause register means. 27. (New) A processor according to claim 26. wherein said event history buffer means comprises a plurality of buffers. 28. (New) A processor according to claim 26, wherein said event history buffer means is configured to capture contents of said cause register means when enabled by said enable input. 29. (New) A processor according to claim 28. wherein said event history buffer is configured to be enabled when the contents of said cause register means indicates a particular event. 14180151 -9 - Attorney Docket No. 3059.014REXO BC_GEN_0002216