Bicameral LLC v. NXP USA, Inc. et al

Western District of Texas, txwd-6:2018-cv-00294

Exhibit Ex. 331EX4

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7 Exhibit 331EX4 7 DECLARATION OF MICHAEL BARR UNDER 37 C.F.R. § 1.132 90/011,532 BC_GEN_0003165 7 Declaration of Michael Bar Under 37 CER $ 1.132 ROY eral, Reexamn Control No. 90/011,532 103(a) as unpatentable over U.S. Pateni No. 5,473,754 to Folwell et al. ("Folwell"). (See Ex. G at p. 3). In response to the first Office Action, the Applicants filed an amendment on September 8, 1999 amending claims 5, 15, and 23, and incorporating the subject matter of claim 22 into claim 21. (See Ex. H at pp. 1-2). In addition to the amendments, the Applicants stressed the importance of the real-time aspect of the invention and argued that the Folwell reference lacked (1) s program counter means, (2) a first decoder means, and (3) did not teach a decoder that operated in real time. (Id. at pp. 3-5). The Applicants also noted that Folwell failed to disclose coupling the various components of the invention together as claimed. (Id.) 28. On November 24, 1999, the Office issued a second non-final Office Action. The Office Action rejected claims 4. 14, and 23 under the second paragraph of 35 U.S.C. $ 112. objected to claim 23, rejected claims 1, 2, 5, 11-12, 15, 19, and 20 as kinpatentable under 35 U.S.C. $ 103(a) in view of the combination of Folwell and the newly-cited reference U.S. Patent No. 5,440,700 to Kaneko ("Kaneko"). (See Ex. I at pp. 2-3). Additionally, it was noted that the subject matter of dependent claims 6-10 and 16-18 would be allowable. (Id. at P. 8). 29. On February 25, 2000, the Applicants conducted an interview with the Examiner to discuss the outstanding Office Action. (See Ex.) atp. 1). During the course of the interview the parties discussed the meaning of the term "coupled" in the claims. The Examiner noted that if the term coupled were changed to "directly coupled," a new search would be required. Barr Declar3tion Roy.docx Attomey Docket No. 3059.014REXO BC_GEN_0003174 7 Declaration of Michael Barr Under 37 CER $ 1.132 ROY eral, Reexamn Control No. 90/011,532 30. Subsequent to the interview, the Applicants filed a second amendment on March 10, 2000. Amongst other things, the second amendment amended the claims to recite the term "connected" in lieu of "coupled." (See Ex. K at pp. 2-5). Additionally new claims 26 and 27 (corresponding to allowed claims 21 and 22) were added. In their remarks, the Applicants noted that "lit is the understanding of the undersigned that the word 'connected' is typically used to mean directly coupled whereas the word 'coupled' allows for intermediate elements between the elements which are 'coupled."" (ld. at p. 6). 31. On June 6, 2000, the Office issued a third Office Action, which the Examiner made final. The Office Action rejected claims 4, 14, 23, 26. and 27 under the second paragraph of 35 U.S.C. $ 112 and reasserted the rejection of claims 1, 2, 5, 11-12, 15, 19, and 20 as unpatentable under 35 U.S.C. $ 103(a) in view of the combination of Folwell and Kaneko. (Ex. L at pp. 3-4). Claim 23 was rejected as unpatentable over the combination of newly-cited references U.S. Patent No. 6,052,774 to Segars et al. (*Segars") and U.S. Patent No. 5,428,618 to Veki ("Ueki"). (Id. at 4). Claims 24-25 were rejected as unpatentable over the combination of Segars and Folwell. (Id. at 5). Additionally, the Examiner noted that claims 4, 14, and 26-27 would be allowable if rewritten to overcome the $ 112 rejection and the subject matter of claims 6-10 and 16-18 was indicated to be allowable. (Id. at 6). The Examiner also noted that the term "connected" is not synonymous with "directly coupled" because it "does not exclude intermediate clements between coupled elements." (Id. at p. 7). 32. In response to the final Office Action, the Applicants filed a third Amendment. The Examiner, however, did not enter the third amendment. (See Ex. M at p. 1). The Applicants requested that the Examiner reconsider not entering the claim amendments (see Ex, N at pp. 1-2), but the Examiner remained firm (see Ex. O atp. 1). Bar Declaration Roy.docx -10. Anomey Docket No. 3059.014REXO BC_GEN_0003175 7 Declaration of Michael Bar Under 37 CER $1.132 ROY eral, Reexamn Control No. 90/011,532 Accordingly, the Applicants filed a CPA application on September 6, 2000, which introduced the same amendments thai the Examiner had previously declined to enter. The CPA application amended claims 1, 4, 6, 11, 14, 21. and 26-27. Relevantly, claims 1. 6, and 11 were amended to replace "connected" with "directly coupled" as had been originally proposed during the interview with the Examiner. (Ex. Patp. 3). 33. On November 20, 2000, the Office issued a fourth Office Action, which the Examiner inade final. In the Office Action, the Examiner rejected claim 21 under the second paragraph of 35 U.S.C. $ 112 and rejected claims 21 and 24-25 as unpatentable under 35 U.S.C. $ 103(a) in view of various combinations of Segars, Ucki, and Folwell. (Ex. Q at pp. 2-3). Additionally, the Office Action indicated that claims 1-20 and 26-27 were allowable over the prior art of record. (Id at p. 4). 34. On January 19, 2001, the Applicants filed a fifth amendment which amended claim 21 to overcome the $112 and the prior art rejections. In response, the Office issued fifth rejection on April 16, 2001, which the Examiner made final. (Ex. Ratp. 1) The fifth rejection maintained the prior art rejections of claims 21 and 24-25 and indicated that claims 1-20 and 26-27 were allowable. (Id.). 35. In response to the final rejection, the Applicants filed an amendment cancelling claims 21 and 24-25 and the Examiner allowed the remaining claims on August 2, 2001. (Ex. S). Barr Declar3tion Roy.docx -11. Anomey Docket No. 3059.014REXO BC_GEN_0003176 7 Declaration of Michael Barn Under 37 CER $1.132 ROY eral, Reexain Control No. 90/011,332 Subject matter of the Roy Patent 36. I uderstand that the Roy patent relates to a debugging interfice that allows for real-time operation of a processor during debugging. (See Ex. C. at Abstract). Roy describes one embodiment of the invention in the context of an ASIC chip that incorporates a debugger interface for three processors 12a, 12b, and 12c that share a common clock 16 via a clock bus 17. (Ex, C, 4:7-20; FIGS. IA and IB). Each processor includes an instruction RAM (IRAM) 18, an arithmetic logic unit (ALU) 20, and a sequencer 22. (Id.). The sequencers 22 each include a program counter 24 and a cause register 26. (Id). A "cause register" stores current information about interrupts, exceptions, and other processor functions. (Ex. C, 4;17-19). A first decoder 28 is coupled to each IRAM 18 and provides an indication of processor activity. (Ex. C, 4:20-25). Additionally, each cause register 26 is coupled to the data input D of a history buffer 14 and to a second decoder 32. (Ex. C, 6:15.m 26). The history buffer 14 also records a clock signal and an enable signal and makes the data, clock, and enable signals available off chip. (Id.). 37. The Roy patent has four independent claims (claims 1, 11,21 and 22). Independent claim 1 of the Roy patent recites the following: 1. A processor having a real time debugging interface, processor comprising: a) instruction memory means for storing instructions to be executed by said processor b) program counter means directly coupled to said instruction memory means for indexing said instructions; c) cause register means for indicating information regarding interrupts and exceptions and d) first decoder means for indicating information about an instruction executed by said processor during a clock cycle, said first decoder means being directly coupled to said instruction memory means, said program counter incans, and said cause register mcans, said first decoder means having a first output, wherein Har Declaration Roy.docx - 12- Artomey Docket No. 3059.014REXO BC_GEN_0003177 7 Declaration of Michael Barr Under 37 CER. $ 1.132 ROY eral, Reexain Control No. 90/011,532 said first output provides information regarding activity of said processor in real time. 38. Independent claim 11 of the Roy patent recites the following: 11. An embedded system having a plurality of processors and a real time debugging interface, said system comprising: a) a plurality of instruction memory means for storing instructions to be executed by a respective one of said plurality of processors; b) a plurality of program counter means, each directly coupled to a respective one of said plurality of instruction memory means for indexing contents of said instruction memory means; c) a plurality of cause register means for indicating information regarding interrupts and exceptions for a corresponding one of said plurality of processors, cach of said cause register means being directly coupled to a respective one of said processors; and d) a plurality of first decoder mcans, cach said firsi decoder means directly coupled to a respective one of said instruction memory means, to a respective one of said program counter means, and a respective one of said Cause register means, cach said first decoder means for indicating information about an instruction executed during a clock cycle by a respective one of said processors, cach said first decoder means having a first output, wherein each said first output provides information regarding activity of said processor in real time. 39. Independent claim 21 of the Roy patent recites the following: 21. A processor having a real time debugging interface, said processor coinprising: a) instruction memory means for storing instructions to be executed by said processor; b) program counter means coupled to said instruction memory means for indexing said instructions; c) cause register means for indicating infomation regarding interrupts and exceptions; and d) first decoder means for indicating information about an instruction executed by said processor during a. clock cycle, said first decoder means being coupled to said instruction memory means, said program counter means, and said cause register means, said first decoder means having a first output, wherein Barr Declar3tion Roy.docx - 13 - Atomey Docket No. 3059.014REXO BC_GEN_0003178 7 Declaration of Michael Barr Under 37 CER $1.132 ROY eral, Reexain Control No. 90/011,532 said first output provides information regarding activity of said processor in real time, said clock cycle is a processor clock cycle, said first decoder means updates said information about each instruction executed by said processor for each said processor clock cycle, and said information about each instruction executed by said processor includes an indication whether or not an instruction has been executed since the previous processor cycle. 40. Independent claim 22 of the Roy patent recites the following: 22. An embedded systein having & plurality of processors and a real time debugging interface, said system comprising: a) a plurality of instruction memory means for storing instructions to be executed by a respective one of said plurality of processors b) a plurality of program counter means, cach coupled to a respective one of said plurality of instruction memory means for indexing contents of said instruction memory means; c) a plurality of cause register incans for indicating information regarding interrupts and exceptions for a corresponding one of said plurality of processors, cach of said cause register means being coupled to a respective one of said processors, and d) a plurality of first decoder means, cach said first decoder means coupled to a respective one of said instruction memory means, to a respective one of said program counter means, and a respective one of said cause register means, each said first decoder means for indicating information about an instruction executed during a clock cycle by a respective one of said processors, each said first decoder means having a first output, wherein each said first output provides information regarding activity of said processor in real time, said clock cycle is a processor clock cycle, cach said first decoder incans updates said information about each instruction executed by a respective processor for each said processor clock cycle of said respective processor, and cach said information about each instruction executed by a respective processor includes an indication whether or not an instruction has been executed since the previous processor cycle of said respective processor, Barr Declar3tion Roy.docx - 14. Anomey Docket No. 3059.014REXO BC_GEN_0003179 7 Declaration of Michael Barr Under 37 CER $ 1.132 ROY eral, Reexain Control No. 90/011,532 A "Cause Register" In View of the Roy Patent 41. Each of the independent claims recites the term "canse register." The term 'cause register" is not a term of art, but a specific feature described in the Roy Specification. 42. Within the context of the Roy specification, it is clear to me that "cause registers" are used to store "information about interrupts, exceptions, and other processor functions." (Ex. C, 4:18-20). The Specification explains the kind of information stored in the cause register in the context of storing the cause register information in bits 40-18 of the history buffer 14. (Ex. C, 6:39 -- 7:10). As explained by the specification: If cause register infornation is being stored, bit location 40 is used to indicate whether the exception occurred while the processor was executing an instruction in the branch delay slot. (This applies to pipelined processors such as RISC processors.) Bit locations 39 through 35 are used to store processor related exception conditions. Bit locations 34 through 18 are used to store an indication of all pending interrupts (external, sotiware, coprocessor), (Id.) (emphasis added). Said differently, the cause register stores information about the state of both the interrupts and exceptions, which informs the debugger about the cause of the program leaving the normal path of software execution, "Directly Coupled" 43. Within the context of the prosecution history, the specification, and the claim language, I understand the term "directly coupled" to have a specific and particular meaning. Specifically, during the initial prosecution, the term directly coupled was used to mean a physical comection that excludes intermediate elements between coupled clements. (See Ex. L at pp. -4). Thus, two elements are directly coupled if they are connected to each other Bart Declaration Roy.docx - 15. Attomey Docket No. 3059.014REXO BC_GEN_0003180 7 Declaration of Michael Barn Under 37 CER $ 1.132 ROY eral, Reexain Control No. 90/011,532 without any intervening element. If there is an intervening element, then the two clements are noi directly coupled. 44. During the initial prosecution, the original claims recited various elements "connected" to one another. The Examiner cited U.S. Patent No. 5,473,754 to Folwell et al. to show the claimed "comection." (See, e.g. Ex. L at pp. 3-) Specifically, the Examiner indicated that Folwell showed a first decoder and instruction memory that were connected via a program data bus 24. (Id.). 45. The Examiner noted that amending the term "connected" to "directly coupled" would overcome the rejection based on Folwell's disclosed connection of the first decoder and instruction memory via the program data bus. (See, e.g., Ex. O). Applicant amended the claims to recite "directly coupled" and the claims were allowed. (Ex. S). Thus, "directly coupled" overcame a rejection based on a bus during the initial prosecution. (Id.). A person of ordinary skill in the art would, therefore, not view two circuit components connected via a bus to be directly coupled as recited by the claims. THE ASSERTED REFERENCES Augsburg 46. U.S. Patent No. 5,996,092 to Augsburg et al. ("Augsburg") discloses a system and method for tracing program code within a processor having an embedded cache memory around a trigger event. (see Ex. D. Abstract). Augsburg discloses this system and method in the context of integrated circuit 10 shown in FIG. 1 (reproduced below). Barr Declar3tion Roy.docx - 16 - Aromey Docket No. 3059.014REXO BC_GEN_0003181 7 4.. ** wurwum 20 DRIVER TO TRACE TOOL 7. The integrated circuit 10 includes a microprocessor 100 that contains an embedded instruction cache 101. (Ex. D, 5:34-38). Additionally, the microprocesso 100 contains an instruction addresa register (IAR) 10, which Augsburg notes is commonly known as the program counter" (Ex. D, 5:61-65). Control logic 103 receives status information from the microprocessor 100. (Ex. D, 7:3$.$0). The status infomation may include "the execution of an instruction, the direction of any executed branches, and the taking of any exception vectors." (Id.. The control logie 103 encodes the received status infomnation and outputs the encoded status information along bus (Os through driver 107 48. A person of ordinary skill in the art would understand Augsburg to lack among other things, a causa register means such as that described and claimed by Roy, Indeed, Augsburg does not have a cause register kvecause it does not require one. In general, to build a real time debugger, you do not need a cause register. While the cause register described by the Roy patent would provide additional functionality during the course of - 17. Atomey Docket No. 3059.014REXO BC_GEN_0003182 7 Declaration of Michael Barn Under 37 CER $1.132 ROY eral, Reexamn Control No. 90/011,532 debugging, it is not necessary to know the state of the interrupts and exceptions. Indeed, Augsburg describes a method of detecting when an interrupt occurs that does not require knowing which other interrupts and/or exceptions are pending. 49. Augsburg provides very little insight on how the various registers are connected to the components within the microprocessor (such as the instruction cache 101) other than to state that "registers 108-110 are physically accessible by the present invention in well-known manners." (Ex. D. 6:15-17). Accordingly, a person of ordinary skill in the art would not understand Augsburg to describe an IAR 110 that is "directly coupled" to the instruction cache 101. Similarly, a person of ordinary skill in the art would not understand Augsburg does disclose a direct coupling of the control logic 103 to either the IAR 110 or the instruction cache 101. The IBM Manual 50. The IBM manual is a user's manual for the IBM Power PC 403GA that provides an overview and detailed information about the registers and the instruction set of that controller. (See Ex. E xp. XXV). Within the context of the manual, interrupts are actions where the processor saves its old context and begins execution at a pre-determined interrupt- handler address with a modified machine state register (MSR). (ld. at p. 6-1). Exceptions are processor events that can cause similar actions. (Id.). The controller described by the IBM manual allows exceptions to be generated internally and interrupts to be generated by external peripherals, (Id.). 51. In general, when an exception or interrupt occurs, the controller automatically stores the contents of the MSR (a 32-bit register that holds the current context of the Barr Declar3tion Roy.docx - 18 - Anomey Docket No. 3059.014REXO BC_GEN_0003183 7 Declaration of Michael Barn Under 37 CER $1.132 ROY eral, Reexamn Control No. 90/011,532 controller) in one of two Save Restore Registers. (Ex. E at 6-2). If an exception is taken, the contents of the MSR are automatically saved. (Id.). When a retum from interrupt {rfi) or return from critical interrupt (rfci) instruction is executed, the contents of the MSR are restored. (Id.). 52. The IBM Manual also explains that the controller includes an External Interrupt Status Register (EXISR), which contains the status of five external hardware interrupts, the DMA channel interrupts, the JTAG serial port interrupts, and the serial port interrupts. (Id. at p. 6-9). In order to cause an interrupt from an external peripheral, a bit in the External Interrupt Status Register (EXISR) is set. (Id.). Nakamoto 53. Nakamoto describes a non-real time debugging circuit that attempts to overcome a problem in the prior art that required restarting the program operation from the first address after finishing the debug operation using a BRAKE command. (See Ex. F, 1:15- 30). To that end. Nakamoto describes a debug circuit that stops operation of a program in order to perform debug operations. (Ex. F, 3:65.. 4:5; 4:27-46). The debug circuit includes a program counter (PC) I and a program memory 2. (Id., 2:21-23). FIG. 2 (reproduced below) shows a number of the Nakamoto components with their logical connections. Barr Declar3tion Roy.docx - 19. Attomey Docket No. 3059.014REXO BC_GEN_0003184 7 SAT. .. W AS SIRS www BE www.wwww in %% *- www 54. Amongst other things, Nakamoto discloses an instruction decoder and timing controller 3 in communication with the program memory 2, the program counter 1, and a latch register a. (EX. F, 3:4.8, 3:14-23, 3:35-39, FIG. 2). BC_GEN_0003185 7 Declaration of Michael Barn Under 37 CER $1.132 ROY eral, Reexamn Control No. 90/011,532 55. While arrows in FIG. 2 show logical connections, Nakamoto explains in the specifications how various components are physically connected to each other "through an intemal bus 3." (Ex. F, 2:38). Specifically, Nakamoto states: The signal processor 100, which is fabricated as a semiconductor integrated circuit device, comprises a program memory 2 which stores a program, a program counter (PC) 1 which designates addresses where instructions to be carried out in the program are stored, an arithmetic logical processing unit (ALU) 14, a register sex 15 which includes an accumulator and a temporary register, a data memory 16 which stores data temporarily, and a debug circuit 50. These components are connected with each other through an internal bus 5. (Ex, F, 5:27-28) (emphasis added), CLAIM REJECTIONS "Cause register means for indicating information regarding interrupts and exceptions" 56. The Office Action alleges that the IBM Manual's MSR and/or EXISR disclose the claimed cause register means for indicating cause information regarding interrupts and exceptions. (Ex. T at p. 4) However, a person of ordinary skill in the art would understand neither the MSR nor the EXISR to be the claimed cause register means. 57. Roy's "cause register incans' stores information about the state of both interrupts and exceptions, which informs the debugger about the cause of program changes. (Ex, C, 4:18-20; 6:36-7:10). In particular, Roy describes a cause register that stores cause information regarding external interrupts, software interrupts, co-processor interrupts, and exceptions. (ld). In this way, the cause register means can provide the reasons why the program left the normal path of software execution. (Id. at 3:20-21). Additionally, it can Barr Declar3tion Roy.docx -21. Anomey Docket No. 3059.014REXO BC_GEN_0003186 7 Declaration of Michael Barr Under 37 CER $1.132 ROY eral, Reexamn Control No. 90/011,532 provide a trigger (e.g., on the occurrence of an exception, changes of state of an interrupt, etc.) for storing information into an event history buffer. (Id.). 58. The EXISR is not a cause register because it only provides external interrupt status information. (Ex. E at 6-9). That is, it provides only a partial list of causes for changes to the normal software execution path. A person of ordinary skill in the art would understand that a partial list of causes for changes to the normal execution path is contrary to effective software debugging The EXISR, for instance, lacks any information concerning co-processor interrupts, software interrupts, or exceptions. (Id.). Thus, a person of ordinary skill in the art would not understand the EXISR as the equivalent of the claimed cause register means. 59. The MSR is similarly not a cause register. The MSR consists of control bits to cnable groups of interrupts and exceptions, among other things, (Ex. E at 6-2 to 6-4). Essentially, the MSR simply provides a switch for turning the interrupts and exceptions on and off - the bits within the MSR contain NO information about the state of interrupts and exceptions, or the reason why the program left the normal path of software execution. (Id.). Thus, a person of ordinary skill in the art would not view the MSR to be the same as the claimed cause register means. "First decoder means being coupled to said instruction memory meuns, said program counter means, and said cause register means." 60. The Office Action alleges that Nakamoto discloses a first decoder means being coupled to said instruction memory means, said progranı counter means, and said cause register means. (Ex. T at 12). Specifically, the Office Action alleges an equivalency Barr Declar3tion Roy.docx - 22- Attomey Docket No. 3059.014REXO BC_GEN_0003187 7 Declaration of Michael Barn Under 37 CER $ 1.132 ROY eral, Reexamn Control No. 90/011,532 between, amongst other things. Nakamoto's instruction and timing controller 3 and the first decoder and Nakamoto's latch register 6 and the claimed cause register means. (ld.). 61. Nakamoto's instruction decoder and timing controller 3 is not equivalent to the first decoder that is described and claimed by Roy. Despite the fact that both components use the word "decoder" lo describe them, they actually are very different things. As explained by Roy, "the decoder 28 is arranged to indicate whether the program counter has moved its pointer to a new instruction." (Ex.C, 4:29-31). Furthermore, the three bit output of the first decoder 28 provides an indication of processor activity during the previous clock cycle. (Ex. C, 4:26-29). Nakamoto's "instruction decoder and timing controllera does something entirely different than the claimed firsi decoder. Instead of being used to provide an indication of processor activity during a previous clock cycle, Nakamoto's "instruction decoder and timing controller" is used to produce the DLCS and PCCS control signals, which control the latch register 6 and the program counter, respectively. (Ex. F. 2:33-36, 2:61-68. 3:1-3). Thus, Nakamoto discloses that the "instruction decoder and timing controller 3 decodes... instructions to provide a control signal 31 necessary to execute the instructions." (Ex. F, 3:18-20) (emphasis added). The "instruction decoder and timing controller 3" is, therefore, very different from the claimed first decoder. 62. Nakamoto also does not disclose or suggest the claimed cause register means. The Office Action draws an equivalence between Nakamoto's latch register 6 and the claimed cause register means. (Ex. T at 12). This false equivalence appears to stem from a misrcading of Nakamoto - specifically the box labeled 302 that appears in FIG. 3, in which the word "cause" (used as a verb) happens to appear adjacent to the term "register 6." (Ex. T at 12). Box 302 of FIG 3, however, has nothing to do with anything even remotely sinilar to Bart Declaration Roy.docx - 23 Attomey Docket No. 3059.014REXO BC_GEN_0003188 7 Declaration of Michael Barn Under 37 CER $1.132 ROY eral, Reexain Control No. 90/011,332 the claimed *cause register." As discussed above, a cause register indicates cause infonnation regarding interrupts and exceptions. A person of ordinary skill in the art would not understand the latch register 65 to provide this functionality. 63. Thus, even if Nakamoto were to show a direct connection between the instruction and timing controller 3 and the latch register, a person of ordinary skill in the ari would not understand Nakamoto to teach a "first decoder means coupled to said.. cause register means," because the instruction and timing controller is not equivalent to the first decoder and the latch register is not equivalent to the cause register means. "program counter means coupled to said instruction memory means for indexing said instructions." 64. The Office Action alleges that Nakamoto discloses a program counter directly coupled to program memory. (Ex. Tat 11). However, this is not the case. As noted above, Nakamioto describes the program counter i and the program memory 2 "connected with each other through an internal bus." (Ex. F, 2:27-28). 05. A person of ordinary skill in the art would not understand Nakamoto to expressly or inherently disclose or suggest that the program counter 1 and the program memory 2 are directly coupled together. Instead, Nakamoto discloses coupling the program counter 1 and the program memory together indirectly via an internal bus. As I discussed earlier in paragraphs 43.45, a person of ordinary skill in the art would not understand connecting two circuit components together via an internal bus to constitute a direct coupling. Accordingly, a person of ordinary skill in the art would not understand Nakamoto to disclose or suggest direci coupling of the program counter I to the program memory. Barr Declar3tion Roy.docx - 24. Anomey Docket No. 3059.014REXO BC_GEN_0003189 7 Declaration of Michael Barr Under 37 CER $ 1.132 ROY eral, Reexain Control No. 90/011,532 CONCLUSION 66. For at least the above reasons, none of Augsburg, the IBM Manual, and Nakamoto references, taken alone or in combination, discloses or suggests each and every feature of the claimed invention. 67. A person of ordinary skill in the art would not understand the combination of Augsburg and the IBM Manual to disclose or suggest cach and every feature of independent claims 21 and 22. For instance, both claims recite a "cause register means for indicating cause information regarding interrupts and exceptions." For the reasons stated above, neither Augsburg nor the IBM Manual discloses or suggests a cause register that indicates information regarding interrupts and exceptions, 68. A person of ordinary skill in the art would not understand the combination of Augsburg, the IBM Manual, and Nakamoto to disclose or suggest each and every feature of independent claims 1 and 11. For instance, the combination fails to disclose or suggest (a) "cause register means for indicating cause information regarding interrupts and exceptions," (b) "first decoder means being directly coupled to suid instruction memory means, said program counter means, and said cause register means," and (c) "prograin counter ineans directly coupled to the instruction memory means for indexing said instructions," 69, Executed this 24th day of September 2011 in Maryland. Respectfully submitted. Michael Bar Michael Barr Barr Declar3tion Roy.docx - 25 - Atomey Docker No. 3059.014REXO BC_GEN_0003190 7 IN THE UNITED STATES PATENT AND TRADEMARK OFFICE Confirmation No.: 3636 In re reexam of: U.S. Patoni No. 6,321,331 ROY et al. Art Unit: 3992 Reexain Control No.: 90/011,532 Examiner: Woo H. Choi Filed: March 4, 2011 Atty. Dkt. No.: 3059,014REXO For: Real Time Debugger Interface for Embedded Systems Declaration of Michael Barr Under 37 C.F.R. $ 1.132 1, Michael Barr, declare as follows: 1. Thave been retained as a technical expert by Sterne, Kessler, Goldstein & Fox, P.L.L.C., which represents Intellectual Ventures Management of which TR Technologies Foundation LLC is an affiliate in connection with the above-captioned reexamination of U.S. Patent No. 6,321,331 to Roy et al. (hereinafter "Roy" or "the '331 patent") (Attached as Exhibit C). I understand that the '331 patent is currently assigned to TR Technologies Foundation, LLC 2. I have reviewed and am familiar with the Office Action dated July 29, 2011 issued by the U.S. Patent and Trademark Office ("USPTO") in the above-captioned reexamination. I understand that claims 1-5, 11-15, and 19-22 are subject to reexamination and that claims 1, 11,21, and 22 are independent claims. Alty, Dkt. No. 3059.014ROXO BC_GEN_0003166 7 Declaration of Michael Barr Under 37 CER. $ 1.132 ROY eral, Reexain Control No. 90/011,532 3. I have reviewed and am familiar with: a. U.S. Patent No. 5,996,092 entitled System and Method for Tracing Program Execution Within a Processor Before and After a Triggering Event, issued to Augsburg et al. on November 30, 1999 (hereinafter "Augsburg" or "ihe '092 palent") (Attached as Exhibit D); b. IBM PowerPC 403GA User's Manual, Second Edition, March 1995, (online) (retrieved on 2011-2-9) Retrieved using Internet http://iwant.to.surf.free.fr/NCD/HTML/405gaum.pdf (hereinafter "the IBM Manual") (Attached as Exhibit E); and C. U.S. Patent No. 5,361,348 entitled Debug Circuit of a Signal Processor, issued to Nakanoto on November 1, 1994 (hereinafter "Nakamoto" or t'the '348 patent") (Attached as Exhibit F). 4. I have been asked to consider how a person of ordinary skill in the art would understand the claims of the '331 patent subject to reexamination in view of the disclosure of the 331 patent. I have also been asked how a person of ordinary skill in the art would undersiand the applied Augsburg, IBM Manual, and Nakamoto references. In addition, I have been asked to consider whether or not a person of ordinary skill in the art would understand the combination of Augsburg and the IBM Manual to render claims 21 and 22 08 the '331 patent obvious. For the reasons set forth below, it is my opinion that a person of ordinary skill in the art would not find claims 21 and 22 of the '331 patent obvious in view of the combination of Augsburg and the IBM Manual. Barr Declar3tion Roy.docx - 2- Atomey Docker No. 3059.014REXO BC_GEN_0003167 7 Declaration of Michael Bar Under 37 CER $1.132 ROY eral, Reexamn Control No. 90/011,532 5. I have been further asked to consider whether or not a person of ordinary skill in the art would understand the combination of Augsbury, the IBM Manual, and Nakamoto to render claims 1-5, 11-15, and 19-20 of the '331 patent obvious. For the reasons set forth below, it is my opinion that a person of ordinary skill in the art would not find that the combination of Augsburg, the IBM Manual, and Nakamoto renders claims 1-5, 11-15, and 19-20 of the '331 patent obvious, 6. I am being compensated at my standard hourly rate of $350 dollars per hour. My compensation is not dependent on the outcome of this reexamination and in no way affects the substance of my statements during the oral interview or in this declaration. QUALIFICATIONS AND EXPERTISE 7. My Curriculum Vitae is aitached as Exhibit B to this declaration. 8. I hold Bachelor of Science and Master of Science degrees in Electrical Engineering from the University of Maryland ai College Park, which were awarded in 1994 and 1997, respectively. 9. I have authored or co-authored three books and more than 60 technical articles and conference papers regarding the design of so-called "embedded systems" and related technologies. An embedded system is a combination of computer hardware and software, and perhaps additional mechanical or other parts, designed to perform a dedicated function. Embedded systems contain computers, yet are not the sort of producis most of us think of when we hear the word "computer." Of the more than 10 billion new processors manufactured globally last year, only about 2% became the brains of new PCs, Macs, and Unix workstations. The other 9.8 billion went into embedded systems. Microwave ovens, Bart Declaration Roy.docx - 3. Atomey Docket No. 3059.014REXO BC_GEN_0003168 7 Declaration of Michael Barr Under 37 CER $ 1.132 ROY eral, Reexain Control No. 90/011,532 anti-lock brakes, and pacemakers are just a few examples among the dozens of embedded systems we cach routinely utilize. 10. From January 1999 to the present, I have been president and chief technical officer of Netrino, un embedded systems focused engineering consulting and training firm headquartered in Maryland. During this time, I have also served in other leadership positions in the embedded systems industry, including roles as technical editor, cditor-in-chief, contributing editor, and columnist for the monthly Embedded Systems Design magazine and roles as speaker, advisory board member, track chair, and conference chair of annual Embedded Systems Conferences in Silicon Valley, Boston, Chicago, Europe, and India. 11. From 2000-2002, I taught undergraduate and graduate clectrical engineering students at the University of Maryland, where I was an adjunct professor in the Department of Electrical and Computer Engineering, 12. In the years 1994 to 1997, I worked as an engineer at Hughes Network Systems, a maker of telephony and data communications systems headquartered in Maryland. While I was employed at Hughes, my responsibilities included establishing expertise in debugger technology and related projects, including: porting ROM monitor firmware to various embedded processors; selection, configuration, and use of in-circuit emulators; and design of a debugging interface for an ASIC chip. 13. In the years 1997 to 1998, I worked as an engineer at TSI TelSys, a maker of satellite telemetry and data communications systems headquartered in Maryland. While I was employed at TSI TelSys, my responsibilities included the design and implementation of a development and debugging system for an embedded processor, Barr Declar3tion Roy.docx - Attorney Docket No. 3059.014REXO BC_GEN_0003169 7 Declaration of Michael Barr Under 37 CER $1.132 ROY eral, Reexamn Control No. 90/011,532 14. From 1999 to the present. I have been personally involved in several Netrino. led consulting engagements relating to debugger technology, including competitive analysis of the debugging technology innovations of a Norwegian startup company. 15. From 2003 to the present, I have been engaged as an expert witness in numerous U.S. District Court cases, the U.S. Bankruptcy Court, and Canadian courts. 16. Within my body of published books, technical articles, and conference papers I have written about debugger technology, including in at least the following publications: "Introduction to On-Chip Debug," Embedded Systems Programming, March • Barr, Michael. Programming Embedded Systems in C and ChrChapter 5 "Downloading and Debugging." O'Reilly & Associates, 1999. Gunssle, Jack and Michael Barr. Embedded Systems Dictionary. CMP Books, 2003 (defining a number of debugger related terins), A more detailed resume, including a list of my publications, is provided as attached Exhibit MY UNDERSTANDING OF OBVIOUSNESS 17. It is my understanding that "obviousness" is a question of law based on underlying factual issues including the content of the prior art and the level of skill in the art. I understand that for a single reference or a combination of references to render the claimed Barr Declar3tion Roy.docx Astomey Docket No. 3059.014REXO BC_GEN_0003170 7 Declaration of Michael Barn Under 37 CER. $ 1.132 ROY eral, Reexamn Control No. 90/011,532 invention obvious, a person of ordinary skill in the art must have been able to arrive at the claims by altering or combining the applied references. 18. I understand that patent claims are not rendered obvious merely by demonstrating that each of its elements was, independently, known in the prior art. Instead, I understand that it can be important to identify a reason that would have prompted a person of ordinary skill in the relevant field to combine the elements in the way the claimed new invention does. 19. I also understand that when considering the obviousness of a patent claim, one should consider whether a teaching, suggestion, or motivation to combine the references exists so as to avoid imperinissibly applying hindsight when considering the prior art. I understand this test should not be rigidly applied, but that the test can he important to avoiding such hindsight. 20. In addition, it is my understanding that one must consider whether or not there is objective evidence of non-obviousness, which is also referred to as the "secondary considerations of non-obviousness." STATE OF THE INDUSTRY AT THE TIME OF THE INVENTION 21. Debugging techniques at the time of the tīling of the Roy patent (i.e. on April 22, 1998) could be divided into two categories: Trapping and Tracing. 22. "Trapping" debugging techniques involved stepping through prograin instructions at a rate much slower than real-time and/or setting breakpoints. This was sometimes referred to as "stop and look" debugging. In general, trapping techniques stop Barr Declar3tion Roy.docx - Antomey Docket No. 3059.014REXO BC_GEN_0003171 7 Declaration of Michael Barn Under 37 CER $ 1.132 ROY eral, Reexain Control No. 90/011,532 the operation of a program at certain points to allow observation of the state of the system being debugged. A major downside to this kind of "trapping" debugging is that it was not kyseful for identifying timing errors and other problems that only present themselves when a program is running in real-time Examples of "trapping" techniques can be found in, e.g., ROM monitors or the Nakainoto reference. 23. "Tracing" debugging methods overcome some of the problems associated with trapping methods. For instance, tracing allows for the delayed examination of real-time interactions, which are not observable using trapping methods. In general, tracing involves recording transactions performed by a processor as they happen-often by attaching an external device lo the processor under test. Examples of tracing methods are in-circuit emulators, or the Augsburg reference with a limitation. 24. Traditional tracing debugging methods are not without their own problems, though. For instance: a. Some require a separate debug support circuit, which is connected to a system bus. This places an increased electrical load on the bus and can interfere with its operation. This also raises mechanical interconnection issues. h. Some require a great number of additional debug pins on the processor, a vast amount of debug-only mentory, andor cannot keep up with the normal speed of processor activity. €. They cannot be used to see internal bus activity, so they are not appropriate for all debugging situations (e.g., cache memory or ASICs). Barr Declar3tion Roy.docx -7. Anomey Docket No. 3059.014REXO BC_GEN_0003172 7 Declaration of Michael Barr Under 37 CER $1.132 ROY eral, Reexain Control No. 90/011,532 BACKGROUND OF THE 331 PATENT Overview 25. The Roy patent solves the problems associated with traditional debugging techniques. Specifically, the Roy patent accomplishes at least four objectives for providing a debugging interface that were not accomplished by prior art techniques: a. Allows for tracing instructions without loss of real-time context and event interaction, which is extremely useful for finding and debugging timing errors. b. Allows for debugging that does not interfere with the operation of a processor or system bus, €. Allows for debugging that does not require many additional pins on a processor chip. 4. Provides access to a substantial amount of information about the executed instructions. Prosecution History 26. The application that eventually became the Roy patent was filed on April 22, 1998 and assigned application number 09/064,474 ("the "474 application"). Initially, the '474 application contained 25 claims --- 3 independent (claims 1, 11, and 21) and 22 dependent (claims 2-10, 12-20, and 22-25). 27. The Patent Office issued the first action on the merits on June 10, 1999. In the first Office Action, the Examiner rejected all of the pending claims 1-25 under 35 U.S.C. $ Bart Declaration Koy.docx -&n Anomey Docket No. 3059.014REXO BC_GEN_0003173