Bicameral LLC v. NXP USA, Inc. et al

Western District of Texas, txwd-6:2018-cv-00294

Exhibit Ex. 331EX5

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2 Exhibit 331EX5 2 PTO/SB/57 (08-08) Approved for use through 08/31/2010. OMB 0651-0033 U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it displays a valid OMB control number. (Also referred to as FORM PTO - 1465) REQUEST FOR EX PARTE REEXAMINATION TRANSMITTAL FORM one Address to: Mail Stop Ex Parte Reexam Commissioner for Patents Attorney Docket No. 6321331RX P.O. Box 1450 Date: March 4, 2011 Alexandria, VA 22313-1450 ....1. X- This is a request for ex parte reexamination pursuant to 37 CER 1.510 of patent number-_-6,321,331-B1.......... issued November 20, 2001_ . The request is made by: ......... ............... patent owner. . x third party requester. 2. X The name and address of the person requesting reexamination is: Adam C. Davenport Slater & Matsil, L.L.P. 17950 Preston Rd. Suite 1000 Dallas, TX 75252 a. A check in the amount of $ 3. N is enclosed to cover the reexamination fee, 37 CFR 1.20(c) (1); x] b. The Director is hereby authorized to charge the fee as set forth in 37 CFR 1.20(c)(1) to Deposit Account No. 50-1065; or c. Payment by credit card. Form PTO-2038 is attached. 4. X Any refund should be made by check or x credit to Deposit Account No. 50-1065 37 CFR 1.26(c). If payment is made by credit card, refund must be to credit card account. 5. X A copy of the patent to be reexamined having a double column format on one side of a separate paper is enclosed. 37 CFR 1.510(b)(4) 6. CD-ROM or CD-R in duplicate, Computer Program (Appendix) or large table Landscape Table on CD Nucleotide and/or Amino Acid Sequence Submission If applicable, items a.-C. are required. a. | Computer Readable Form (CRF) b. Specification Sequence Listing on: ... in CD-ROM (2 copies) or CD-R (2 copies); or. ii. O paper c. Statements verifying identity of above copies 8. A copy of any disclaimer, certificate of correction or reexamination certificate issued in the patent is included. 9. X Reexamination of claim(s) 1-5, 11-15 and 19-22 is requested. 10. X A copy of every patent or printed publication relied upon is submitted herewith including a listing thereof on Form PTO/SB/08, PTO-1449, or equivalent. 11. An English language translation of all necessary and pertinent non-English language patents and/or printed publications is included. · [Page 1 of 2] This collection of information is required by 37 CFR 1.510. The information is required to obtain or retain a benefit by the public which is to file (and by the USPTO to process) an application. Confidentiality is governed by 35 U.S.C. 122 and 37 CFR 1.11 and 1.14. This collection is estimated to take 2 hours to complete, including gathering, preparing, and submitting the completed application form to the USPTO. Time will vary depending upon the individual case. Any comments on the amount of time you require to complete this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, U.S. Department of Commerce P.O. Box 1450, Alexandria, VA 22313-1450. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Mail Stop Ex Parte Reexam, Commissioner for Patents, P.O. Box 1450, Alexandria, VA 22313-1450. ndividual ca patent and in TO: Mail BC_GEN_0002043 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 The Examiner issued a Final Office Action on June 6, 2000, rejecting claims 4, 14, 23, 26, and 27 under 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the Applicants regard as the invention. Ex. E, 331 File History, Office Action (June 6, 2000). The Examiner further rejected claim 21. under 35 U.S.C. § 102(e) as being anticipated by U.S. Patent No. 6,026,503 to Segars et al. ("Segars"), claims 1, 2, 5, 11, 12, 15, 19, and 20 under 35 U.S.C. § 103(a) as being unpatentable over Folwell in view of Kaneko, claim 23 under 35 U.S.C. § 103(a) as being unpatentable over Segars in view of Ueki, and claims 24 and 25 under 35 U.S.C. § 103(a) as being unpatentable over Segars in view of Folwell. Id. at pp. 2-6. The Examiner also noted claims 3 and 13 as similar to claims 1, 11 and 21, and thus were rejected for the reasons cited with regard to those claims. Id. at p. 6. Claims 4, 14, 26 and 27 were indicated as allowable if rewritten to overcome the § 112, second paragraph, rejections noted in the Office Action and to include all of the limitations of the base claim and any intervening claims. Id. Claims 6-10 and 16-18 once again were objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Id. The Examiner also addressed the Applicants' argument that the terms "connected" and "directly coupled" were synonymous. Id. at pp. 6-7. The Examiner disagreed that the words carried the same meaning stating, "The term connected does not exclude intermediate elements between coupled elements." Id. at p. 7. The Applicants mailed a response on August 1, 2000, canceling claim 23 and amending claims 1, 4, 6, 11, 14, 16, 21, 26, and 27. Ex. E, "331 File History, Amendment (Aug. 1, 2000). Specifically, claims 1, 6, 11, and 16 were each amended to change all occurrences of "connected" to "directly coupled." The Applicants noted, "It is the understanding of the undersigned that the word "connected is typically-used to mean directly-coupled whereas the word "coupled' allows for intermediate elements between the elements which are 'coupled'." Id. The Applicants responded that the changing of "connected" to "directly coupled" made the claims so amended allowable over the prior art. Id. at p. 3.: Claims 4, 14, 26, and 27 were each amended to change "a previous" to "the previous." Id, at pp. 1-3. The Applicants stated that these amendments overcame the § 112 rejection. Id. at p. 4. Page 7 of 28 BC_GEN_0002052 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1. Claim 21 was amended to include the limitations of cancelled claim 23 in order to overcome the rejection under Segars alone. Id. at pp. 2-4. Specifically, claim 21 was amended to include "said step of providing information about processor activity includes providing information about every instruction executed by the processor." Id. at pp. 2-3. With respect to the rejection of claim 23, the Applicants argued the Examiner's stated incentive to combine Segars and Ueki was made only in hindsight and the Examiner cited no evidence to support this stated incentive. Id. at p. 4. The Applicants further argued, "Moreover, it appears these references are not so easily combined. Segars et al. deals with a RISC processor which executes several instructions simultaneously. Ueki et al. appears to deal with a CISC processor with processes one instruction at a time." Id.. . The Examiner issued an Advisory Action on August 11, 2000, refusing to enter the amendments because they would raise new issues that would require further consideration and/or search. Ex. E, "331 File History, Advisory Action (Aug. 11, 2000). The Applicants mailed a Request for Reconsideration on August 15, 2000, which was denied by an Advisory Action mailed August 29, 2000. Ex. E, '331 File History, Request for Reconsideration (Aug. 15, 2000) and Advisory Action (Aug. 29, 2000). In response, the Applicants mailed a Request for a Continued Prosecution Application and a Preliminary Amendment on September 6, 2000. Ex. E, "331 File History, Request under 37 CFR 1.53 (Sep. 6, 2000) and Preliminary Amendment (Sep. 6, 2000). The Preliminary Amendment included the same amendments and remarks from the Amendment filed August 1, 2000. Id. The Examiner issued a Final Office Action on November 20, 2000, objecting to claim 21 and also rejecting claim 21 under 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the Applicants. regard as the invention. Ex. E, 6331 File History, Office Action (Nov. 20, 2000). The Examiner further rejected claims 21, 24, and 25 under 35 U.S.C. _103(a) as being unpatentable over Segars in view of Ueki, and claims 24 and 25 under 35 U.S.C. § 103(a) as being unpatentable over Segars in view of Ueki and further in view of Folwell. Id. at pp. 2-3. Claims 1-20, 26 and 27 were indicated as allowable. Id. at p. 4. The Applicants mailed a response on January 19, 2001, amending claim 21 as "said step of providing information about processor activity includes providing (information that the processor has not executed an instruction during the the processor cycle] an indication every time Page 8 of 28 BC_GEN_0002053 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 the processor stalls that the processor has stalled." Ex. E, 331 File History; Amendment (Jan. 19, 2001), pp. 1-2. With regard to the indefiniteness rejection of claim 21, the Examiner stated that the language "indication whether or not an instruction has been executed since a previous processor cycle" was unclear. "331 File History, Office Action (Nov. 20, 2000), p. 2. The Applicants interpreted this statement to mean that "[t]he Examiner believes that the language 'information that the processor has not executed an instruction during the processor cycle' is unclear" and stated that this language means that the debugger can determine whether the processor has stalled," which was more expressly amended into claim 21. See "331 File History, Amendment (Jan. 19, 2001), pp. 2-3. The Applicants further argued, with regard to claim 21, "Column 13 of [Segars] indicates that a processor stall is indicated when executing a branch instruction. However, there is no suggestion that an indication be provided every time the processor stalls regardless of cause." Id. at p. 3. In response, the Examiner issued a new Final Office Action on April 16, 2001, essentially repeating the g 103 rejections from the November 20, 2000 Action. Ex. E, "331 File History, Office Action (Apr. 16, 2001). In response, the Applicants mailed a response on July 9, 2001, cancelling the rejected claims 21, 24, and 25. Ex. E, '331 File History, Amendment (Jul. 9, 2001). The Examiner subsequently issued a Notice of Allowance on August 2, 2001, allowing: all of the pending claims. Ex. E, "331 File History, Notice of Allowability, (Aug. 2, 2001). The issue fee was mailed on September 10, 2001, and the "331 patent subsequently issued on November 20, 2001. Based on the foregoing, a particularly relevant characteristic upon which the Applicants relied in distinguishing issued claims 1 and 11 from the prior art of record was that several claim elements were "directly coupled." Also, a particularly relevant characteristic upon which the Applicants relied in distinguishing issued claim 21 (application claim 26) from the prior art.of record was the limitation "said information about each instruction executed by said processor includes an indication whether or not an instruction has been executed since the previous processor cycle" of original application claim 4. With regard to issued claim 22 (application claim 27), the Applicants relied upon the limitation "each said information about each instruction executed by a respective processor includes an indication whether or not an instruction has been executed since the previous processor cycle of said respective processor" to distinguish over the Page 9 of 28 BC_GEN_0002054 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 prior art of record. As the Applicants noted in response to the Office Action of November 24, 1999, application claims 26 and 27 correspond to original application claims 4 and 14. Ex. E, '331 File History, Amendment (Mar. 10, 2000), p. 6. The Applicants relied upon the Examiner's indication of allowable subject matter in original application claim 4 and 14 to assert that application claims 26 and 27 were allowable. See id. It is also worth noting that original application claim 4 depended from original application claim 3, which further depended from original application claim 1, and original application claim 14 depended from original application claim 13, which further depended from original application claim 11. D. Claim Interpretation for the Purpose of this Request Pursuant to 37 C.F.R. $ 1.555(b) and MPEP $ 2111, each term in the claim is to be given its broadest reasonable construction consistent with the specification. "[B]road interpretation by the examiner reduces the possibility that the claim, once issued, will be interpreted more broadly than is justified." MPEP $ 2111 (citations omitted). Requester submits that any claim construction submitted herein for the purposes of. illustrating an SNQ is not binding upon the Requester in any other matter, litigation or otherwise, related to the "331 patent. Requester further submits that claim constructions submitted herein do not necessarily comport to the construction of claims under the legal standards used by courts in litigation. See MPEP $ 2286.II (stating that the manner of claim interpretation that is used by courts in litigation is not the manner of claim interpretation that is applicable during prosecution of a pending application before the PTO") (citations omitted). Page 10 of 28 BC_GEN_0002055 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 II. DETAILED EXPLANATION OF THE RELEVANCY AND MANNER OF APPLYING THE PRIOR ART REFERENCES TO EVERY CLAIM FOR WHICH REEXAMINATION IS REQUESTED The present Request provides new, uncited prior art references that read on each and every limitation of claims 1-5, 11-15, and 19-22 of the "331 patent, thereby presenting substantial new questions of patentability. Each of these references, as well as a detailed explanation regarding the manner in which these references disclose each and every limitation of claims 1-5, 11-15, and 19-22, is discussed in the following paragraphs. A. Claims 21 and 22 are unpatentable over Augsburg in view of the IBM Manual under 35 U.S.C. § 103(a) Claims 21 and 22 are invalid as being unpatentable over Augsburg (Ex. B) in view of the IBM Manual (Ex. C), neither of which is a cited reference of the "331 patent, nor was either considered during examination. Augsburg was filed on December 5, 1996, and issued as U.S. Patent Number 5,996,092 on November 30, 1999. The filing date of Augsburg is before the "331 patent's earliest priority date of April 22, 1998, and therefore, Augsburg qualifies as prior art at least under 35 U.S.C. § 102(e). The IBM Manual has a publication date of March 1995, which is more than one year before the "331 patent's earliest priority date of April 22, 1998, and therefore, the IBM Manual qualifies as prior art under 35 U.S.C. § 102(b). Augsburg (Ex. B) is directed to non-invasive, real-time program tracing with an integrated processor. See, e.g., Ex. B, col. 1, lines 16-18; col. 3, lines 6-9. Augsburg teaches an integrated circuit 10, shown in Figure 1, which includes logic for performing the tracing of program code. See, e.g., id. at col. 5, lines 34-38. The integrated circuit 10 includes a microprocessor 100, which Augsburg teaches "may comprise ..., e.g., the PowerPC microprocessor, model no. PPC403GA, available from IBM Corporation." Id. at col. 5, lines 42- 45. The integrated circuit 10 further includes an embedded instruction cache 101 within the microprocessor 100, see, e.g., id. at col. 5, lines 36-38, an instruction address register (IAR) 110 commonly known as the program counter, see, e.g., id. at col. 5, lines 62-65, control logic 103, see, e.g., id. at col. 7, lines 36-38, a bus 105, see, e.g., id. at col. 7, lines 42-45, and a driver 107 with pins 118 that output information to a trace tool, see, e.g., id. at col. 7, lines 42-45. . Augsburg teaches that the microprocessor 100 can execute code in the instruction cache 101 or Page 11 of 28 BC_GEN_0002056 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 other on-chip memory, see, e.g., id, at col. 5, lines 48-51, and that the IAR 110 contains the address of the current instruction being executed within the microprocessor at any one point in time, see, e.g., id. at col. 5, lines 62-65; col. 7, lines 13-15. . EXTERNAL BUS 116 117 MLP 101 103 DEBUG - |INSTAUCTION CACHE * A CONTROL LOGIC AR 108. 109 110 114 NOIT MY TTT FYR S指 COUNTER OFFSET COUNTER 122 DRIVER SERIAL 11810:2) ----- - 119 (0:3) TO TAACE TOOL TO TRACE TOOL FIG. 1 Figure 1 of Augsburg Augsburg teaches that the exact information required to be broadcast for tracing depends on the architecture of the processor being traced. See, e.g., Ex. B, col. 7, lines 5-6. In the implementation described by Augsburg, seven input/output pins broadcast enough information to reconstruct a trace. See, e.g., id. at col. 7, lines 6-8. Three of the seven pins, pins 118 in Figure 1, output encoded execution status (ES) of a two-way superscalar CPU, such as microprocessor 100 in Figure 1. See, e.g., id. at col. 7, lines 9-11. The ES information is binary encoded for each cycle, as shown below: Page 12 of 28 BC_GEN_0002057 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 000-no instructions were executed on this clock cycle; 001-an interrupt occurred, transferring execution to an exception vector address; 010-only first instruction available executed and it was not a taken branch; 011-only first instruction available executed and it was ___a_taken branch; 100_Iwo instructions executed; neither was a taken branch; 101-two instructions executed; the first was a taken branch 110.-two instructions executed; the second was a taken branch; 111.-two instructions executed; both were taken branches Id. at col. 7, lines 6-34. The control logic receives status information from the microprocessor 100. See, e.g., id. at col. 7, lines 36-38. The status information may include the execution of an instruction, the direction of any executed branches, and the taking of any exception vectors. See, e.g., id. at col. 7, lines 38-40. The control logic 103 encodes the received status information using the above encoding. See, e.g., id. at col. 7, lines 40-42. Then, the encoded execution status information is output along the bus 105 through the driver 107 onto pins 118 to the trace tool. See, e.g., id. at col.7, lines 42-44. The encoded information is continuously provided on pins 118. See, e.g., id. at col. 7, lines 45-46. The ES information is sufficient to determine what instructions are executed and which ones are taken branches on each cycle. See, e.g., id. at col. 7, lines 47-49. Augsburg further teaches that "processor 100 could be comprised of a number of processing engines in a multiprocessor or parallel processing architecture." See, e.g., id. at col. 12, lines 17-19. The IBM Manual (Ex. C) is directed to the IBM-PPC403GA-JC 32-bit embedded controller, as well as to subsequent IBM PowerPC 400 embedded controllers. See, e.g., The IBM Manual (Ex. C), preface. Among other things, the IBM Manual teaches that the PPC403GA includes registers associated with exceptions, such as a Machine State Register (MSR) and an External Interrupt Status Register (EXISR). See, e.g., id, at p. 6-1. The MSR is a 32-bit register that holds the current context of the PPC403GA. See, e.g., id. at p. 6-2. The content of the MSR is as follows: Page 13 of 28 BC_GEN_0002058 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 4 WE ILE PR ME 12 13 14 15 16 17 18 19 20 21 22 23 PX 27 28 29 17 Figure 6-1, Machine State Register (MSR) 0:12 reserved WE Wait State Enable 0 - The processor is not in the wait state and continues processing. 1 - The processor enters the wait state and remains in the wait state until an exception is taken or the PPC403GA is reset or an extemal debug tool clears the WE bit. 14 CE Critical interrupt Enable 0 - Critical exceptions are disabled. 1 - Critical exceptions are enabled. CE controls these interrupts: critical interrupt pin, watchdog limer first time-out. 15 LE MSR(ILE) is copied to MSR(LE) when an interrupt is taken. Interrupt Little Encian 0-Interrupt handlers execute in Big-Endian mode. | 1 - Interrupt handiers execute in Little-Endian mode, External Interrupt Enable 0 - Asynchronous exceptions are disabled. 1 - Asynchronous exceptions are enabled. EE controls these interrupts: non-critical extemal, DMA, seriai port, JTAG serial port, programmable interval timer, fixed interval timer. PR Problem State 0 - Supervisor State, all instructions allowed. 1 - Problem State, limited instructions available. reserved Machine Check Enable 0 - Machine check exceptions are disabled 1 - Machine check exceptions are enabled 20:21 reserved 22 DE Debug Exception Enable 0 - Debug exceptions are disabled 1 - Debug exceptions are enabled 23:27 reserved PE Protection Enable 0 - Protection excepions are disabled 1 - Protection exceptions are enabled Protection Exclusive Mode 0 - Protection raode is inclusive as deined in Section 2.10 on page 2-33 1 - Protection maode is exclusive as deinsd in Section 2.10 on page 2-33 reserved Little Endian - Processor executes in Big-Endian made. 1 - Processor executes in Little-Endian mode. Id. at pp. 6-3 to 6-4. The EXISR is a 32-bit register containing the status of the five external hardware interrupts, the DMA channel interrupts, the JTAG serial port interrupts, and the serial port interrupts. See, e.g., id. at p. 6-9. The contents of the EXISR are as follows: Page 14 of 28 BC_GEN_0002059 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 SRIS WRIS DIS D2is Egis Ezis Edis 25 |27 28 29 30 31 stis vtis olis DJis Figure 6-8. External interrupt Status Register (EXISR) Elis Edis CIS Criöcal Interrupt Status 0 - No interrupt pending from the critical interrupt pin 1 - Interrupt pending from the critical interrupt pin reserved SRIS Serial Port Receiver interrupt Status - No interrupt pending from the serial port receiver 1 - Interrupt pending from the serial port receiver STIS Serial Part Tranan ter interrupt Status 0 - No interrupt pending from the serial port transmitter 1 - Interrupt pending from the serial port transmitter JRIS JTAG Serial Port Receiver Interrupt Status O- No interrupt pending from the JTAG serial port receiver 1 - Interrupt pending from the JTAG aerial port receiver JTIS JTAG Serial Port Transmiter Interrupt Status 0-No interrupt pending from the JTAG serial port transmitter 1 - Interrupt pending from the JTAG serial port transmitter DOIS DMA Channel O Interrupt Status 0 - No interrupt pending from DMA Charinel O 1 - Interrupt pending from DMA Channel O D1IS DMA Channel 1 Interrupt Status 0 - No interrupt pending from DMA Channel 1 1 - interrupt pending from DMA Channel 1 10 DZIS DMA Channel 2 Interrupt Status 0 - No interrupt pending from DMA Channel 2 1 - Interrupt pending from DMA Channel 2 11 DUIS OMA Channel 3 inierrupt Status 0 - No interrupt pending from DMA Channel 3 1 - Interrupt pending from DMA Channel 3 12:26 reserved 27 EDIS Exiemal Intempt o Status O- No interrupt pending from Extemal Interrupt o pin 1 - Interrupt pending from External Interrupt o pin EAIS External interrupt 1 Status 0 - No interrupt pending from External Interrupt 1 pin 1 - Interrupt pending from Extemal Interrupt 1 pin 29 EZIS Extemal Interrupt 2 Status 0 - No interrupt pending from External interrupt 2 pin 1 - Interrupt pendkng from External Interrupt 2 pin ESIS Extemal interrupt 3 Stains - No interrupt pending from External interrupt 3 pin 1 - Interrupt pending from External Interrupt 3 pin E4IS External Interrupt 4 Status - No interrupt pending from External interrupt 4 pin 1 - Interrupt pending from Extemal Interrupt 4 pin Id. at pp. 6-10 to 6-11. The following chart demonstrates that each of the elements of claims 21 and 22 of the *331 patent are taught by the combination of Augsburg and the IBM Manual as discussed above in Section I.B and, accordingly, that claims 21 and 22 of the "331 patent are invalid under 35 U.S.C. § 103(a) as being unpatentable over Augsburg in view of the IBM Manual. Augsburg explicitly suggests the use of the PPC403GA as the microprocessor 100, see, e.g., Augsburg (Ex. Page 15 of 28 BC_GEN_0002060 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1. . B), col. 5, lines 42-45. Accordingly, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to combine features of the PPC403GA microprocessor, such as those discussed above and in the chart with respect to the IBM Manual, with the features of the microprocessor 100 taught in Augsburg. . In further regards to claim 22, Augsburg explicitly teaches "processor 100 could be comprised of a number of processing engines in a multiprocessor or parallel processing architecture." See, e.g., Ex. B, col. 12, lines 17-19. Augsburg in combination with the IBM Manual suggests a one-to-one relationship between a microprocessor 100, instruction cache 101, IAR 110, MSR/EXISR, and control logic 103 as is implicitly described in claim 22. Thus, it would have been obvious to a person having ordinary skill at the time of the invention to retain the one-to-one relationship of elements described in Augsburg in a single processor comprised of a multiprocessor system to achieve the recited combination of claim 22. Alternatively, claim 22 merely recites the duplication of components that are also recited in claim 21. The "mere duplication of parts has no patentable significance unless a new and unexpected result is produced." MPEP § 2144.04(VI.B.). Accordingly, it would have been obvious to a person having ordinary skill in the art to duplicate the components of claim 21 to achieve the combination of claim 22. Augsburg et al., U.S. Patent No. 5,996,092 *331 Claim Language ("Augsburg") and IBM, "PowerPC 403GA User's Manual" ("the IBM Manual") 21. A processor having a real time | Augsburg teaches, e.g., a microprocessor 100, which may debugging interface, said processor be a PowerPC microprocessor model no. PPC403GA, comprising: having a non-invasive, real time instruction trace | interface. See, e.g., col. 3:6-9; col. 5:41-45. a) instruction memory means for Augsburg teaches, e.g., an instruction cache 101 for storing instructions to be executed storing instructions to be executed by the microprocessor by said processor; 100. See, e.g., col. 5:36-39, 48-52. b) program counter means coupled Augsburg teaches, e.g., an instruction address register to said instruction memory means (IAR) 110,"commonly known as the program counter," for indexing said instructions; for indexing the instructions. See, e.g., col. 5:62-65; col. 6:12-15. The IAR 110 is embedded on the microprocessor 100 with the instruction cache 101, and thus the IAR 110 is "coupled" to the instruction cache, either directly or indirectly. Please note that "coupled" does not require a direct connection, but "allows for intermediate elements between the elements which are 'coupled'." See, e.g., Amendment dated March 13, 2000 Page 16 of 28 BC_GEN_0002061 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 331 Claim Language c) cause register means for indicating information regarding interrupts and exceptions; and "Augsburg et al., U.S. Patent No. 5,996,092 ("Augsburg") and IBM, "PowerPC 403GA User's Manual" ("the IBM Manual") (Paper 8), p. 6. The IBM Manual for the PPC403GA teaches, e.g., a machine state register (MSR) and/or an external interrupt status register (EXISR) for indicating information regarding interrupts and exceptions. See, e.g., chapter 6, pages 6-1 to 6-4, 6-9 to 6-11. Augsburg teaches, e.g., control logic 103 that encodes status information received from the microprocessor 100 that may include the execution of an instruction, the direction of any executed branches, and the taking of any exception vectors. See, e.g., col. 7:36-40. The information is provided during a clock cycle. See, e.g., col. 7:18, 47-49. d) first decoder means for indicating information about an instruction executed by said processor during a clock cycle, said first decoder means being The control logic 103, the instruction cache 101, the IAR coupled to said instruction memory | 110, (see, e.g., Augsburg Fig. 1), and the MSR and/or means, said program counter EXISR (see, e.g., The IBM Manual, chapter 6) are all means, and said cause register embedded on the microprocessor, and accordingly, are all means, "coupled" together, either directly or indirectly. Please note that "coupled" does not require a direct connection, but "allows for intermediate elements between the elements which are 'coupled'." See, e.g., Amendment dated March 13, 2000 (Paper 8), p. 6. said first decoder means having a first output, Augsburg teaches that the control logic 103 has, e.g., a three bit output (0:2) on pins 118 via bus 105 and driver 107. See, e.g., col. 7:42-46; Fig. 1. wherein said first output provides information regarding activity of said processor in real time, Augsburg teaches that the three bit output on pins 118 provides the encoded status information in real time. See, e.g., col. 3:6-10; col. 7:45-46. said clock cycle is a processor clock cycle, Augsburg teaches that the clock cycle is a processor clock cycle. See, e.g., col. 4:56-58; col. 10:5-6. said first decoder means updates said information about each instruction executed by said processor for each said processor clock cycle, and Augsburg teaches that the control logic 103 outputs the encoded status information about each instruction executed by the microprocessor 100 for each processor clock cycle. See, e.g., col. 7:9-61; col. 4:27-29, 56-58. said information about each | instruction executed by said Augsburg teaches that the encoded status information about each instruction executed by the microprocessor Page 17 of 28 BC_GEN_0002062 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 "331 Claim Language Augsburg et al., U.S. Patent No. 5,996,092 ("Augsburg") and IBM, "PowerPC 403GA User's Manual" ("the IBM Manual") 100 includes an indication whether or not an instruction has been executed since the previous processor cycle. See, e.g., col. 7:18-34. processor includes an indication whether or not an instruction has been executed since the previous processor cycle. ........ ............. .............................---...--...-- 22. An embedded system having a plurality of processors and a real time debugging interface, said system comprising: Augsburg teaches an embedded system that has a plurality of processors. See, e.g., col. 12:17-19. Augsburg teaches, e.g., a microprocessor 100, which may be a PowerPC microprocessor model no. PPC403GA, having a real time, non-invasive instruction trace interface. See, e.g.,col. 3:6-9; col. 5:41-45. Augsburg teaches, e.g., an instruction cache 101 for storing instructions to be executed by the microprocessor 100. See, e.g., col. 5:36-39, 48-52. a) a plurality of instruction memory means for storing instructions to be executed by a respective one of said plurality of processors; b) a plurality of program counter means, each coupled to a respective one of said plurality of instruction memory means for indexing contents of said instruction memory means; c) a plurality of cause register means for indicating information regarding interrupts and exceptions for a corresponding one of said plurality of processors, each of said cause register means being coupled to a respective one of said processors; and Augsburg teaches, e.g., an instruction address register (IAR) 110,"commonly known as the program counter," for indexing the instructions. See, e.g., col. 5:62-65; col. 6:12-15. The IAR 110 is embedded on the microprocessor 100 with the instruction cache 101, and thus the IAR 110 is "coupled" to the instruction cache, either directly or indirectly. Please note that "coupled" does not require a direct connection, but "allows for intermediate elements between the elements which are 'coupled'." See, e.g., Amendment dated March 13, 2000 (Paper 8), p. 6. The IBM Manual for the PPC403GA teaches, e.g., a machine state register (MSR) and/or an external interrupt status register (EXISR) in the microprocessor for indicating information regarding interrupts and exceptions. See, e.g., chapter 6, pages 6-1 to 6-4, 6-9 to 6- 11. The MSR and/or the EXISR are embedded in the microprocessor and thus are "coupled" to the microprocessor, either directly or indirectly. Please note that "coupled" does not require a direct connection, but "allows for intermediate elements between the elements which are coupled'." See, e.g., Amendment dated March 13, 2000 (Paper 8), p. 6. . Augsburg teaches, e.g., control logic 103. See, e.g., at col. 7:36-40. MAI d) a plurality of first decoder means, each said first decoder means The control logic 103, the instruction cache 101, the IAR Page 18 of 28 BC_GEN_0002063 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 '331 Claim Language coupled to a respective one of said instruction memory means, to a respective one of said program counter means, and a respective one of said cause register means, Augsburg et al., U.S. Patent No. 5,996,092 ("Augsburg") and IBM, "PowerPC 403GA User's Manual" ("the IBM Manual"). 110, (see, e.g., Augsburg Fig. 1), and the MSR and/or EXISR (see, e.g., The IBM Manual, chapter 6) are all embedded on the microprocessor, and accordingly, are all "coupled" together, either directly or indirectly. Please note that coupled" does not require a direct connection, but "allows for intermediate elements between the elements which are 'coupled'." See, e.g., Amendment dated March 13, 2000 (Paper 8), p. 6. each said first decoder means for indicating information about an instruction executed during a clock cycle by a respective one of said processors, Augsburg teaches that the control logic 103 encodes status information received from the microprocessor 100 that may include the execution of an instruction, the direction of any executed branches, and the taking of any exception vectors. See, e.g., col. 7:36-40. The information is provided during a clock cycle. See, e.g., col. 7:18, 47-49. each said first decoder means having a first output, Augsburg teaches that the control logic has, e.g., a three bit output [0:2] on pins 118 via bus 105 and driver 107. See, e.g., col. 7:42-46; Fig. 1. wherein each said first output provides information regarding activity of said processor in real time, Augsburg teaches that the three bit output on pins 118 provides the encoded status information in real time. See, e.g., col. 3:6-10; col. 7:45-46. said clock cycle is a processor clock cycle, Augsburg teaches that the clock cycle is a processor clock cycle. See, e.g., col. 4:56-58; col. 10:5-6. each said first decoder means updates said information about each instruction executed by a respective processor for each said processor clock cycle of said respective processor, and Augsburg teaches that the control logic 103 continuously outputs the encoded status information about each instruction executed by the microprocessor 100 for each processor clock cycle. See, e.g., col. 7:9-61; col. 4:27-29, 56-58. each said information about each Augsburg teaches that the encoded status information instruction executed by a about each instruction executed by the microprocessor respective processor includes an | 100 includes an indication whether or not an instruction indication whether or not an has been executed since the previous processor cycle. instruction has been executed since See, e.g., col. 7:18-34. the previous processor cycle of said respective processor. Page 19 of 28 BC_GEN_0002064 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 B. Claims 1-5, 11-15, 19, and 20 are unpatentable over Augsburg in view of the IBM Manual, and further in view of Nakamoto under 35 U.S.C. 103(a) Claims 1-5, 11-15, 19, and 20 are invalid as being unpatentable over Augsburg (Ex. B) in view of the IBM Manual (Ex. C), and further in view of Nakamoto (Ex. D). None of these references-is-a-cited reference of the "331 patent, and none was considered during examination. As previously discussed, Augsburg qualifies as prior art at least under 35 U.S.C. § 102(e), and the IBM Manual qualifies as prior art under 35 U.S.C. § 102(b). See supra II.A. Nakamoto issued as U.S. Patent Number 5,361,348 on November 1, 1994, which is more than one year before the "331 patent's earliest priority date of April 22, 1998, and therefore Nakamoto qualifies as prior art under 35 U.S.C. § 102(b). Summaries of exemplary relevant portions of Augsburg (Ex. B) and the IBM Manual (Ex. C) were previously provided, see supra II.A., and hence, summaries of exemplary portions of these references are omitted here. Nakamoto (Ex. D) is directed to a debug circuit of a signal processor. See, e.g., Nakamoto (Ex. D), col. 1, lines 8-12. Nakamoto teaches a signal processor 100 having, among other things, a program counter (PC) 1, a program memory 2, an instruction decoder and timing controller 3, and a latch register 6 (also indicated as "cause register 6" in box 302 of Figure 3). See, e.g., id. at col. 2, lines 19-23, 28-33, 58-61. Figure 2 is an exemplary configuration of the signal processor 100, as shown below. Page 20 of 28 BC_GEN_0002065 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 FIG.2 DATA MEMORY 16 REGISTER SET ALU INTERNAL BUS 2 PROGRAM MEMORY wwwwwwwwwwwwwwww LATCH REGISTER WSDO uh SHIFT REGISTER LOAD EMULATION CIRCUIT HACS INSTRUCTION DECODER AND TIMING CONTROLLER 50 DEBUG CIRCUIT 200 • PCCS SIGNAL PROCESSOR Figure 2 of Nakamoto The following chart demonstrates that each of the elements of claims 1-5, 11-15, 19, and 20 of the "331 patent are taught by the combination of Augsburg, the IBM Manual, and Nakamoto as discussed above in Section I.B and, accordingly, that claims 1-5, 11-15, 19, and 20 of the "331 patent are invalid under 35 U.S.C. § 103(a) as being unpatentable over Augsburg in view of the IBM Manual, and further in view of Nakamoto. Augsburg explicitly suggests the use of the PPC403GA as the microprocessor 100, see, e.g., Augsburg (Ex. B), col. 5, lines 42-45. Accordingly, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to combine features of the PPC403GA microprocessor, such as those discussed above and in the chart with respect to the IBM Manual, with the features of the microprocessor 100 taught in Augsburg. Further, the combination of Augsburg and the IBM Manual does not explicitly teach how certain elements are coupled, e.g., whether the elements are "directly coupled." However, Nakamoto teaches that the claim elements are directly coupled in a processor. It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine features of Nakamoto with Augsburg and the IBM Manual because a person having ordinary skill in the art could have combined the elements as claimed by known methods with no change in their respective functions. See MPEP $ 2143(A.). The combination would yield nothing more than predictable results to one of ordinary skill in the art. See id. Page 21 of 28 BC_GEN_0002066 2 · Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 In further regards to claim 11, Augsburg explicitly teaches "processor 100 could be comprised of a number of processing engines in a multiprocessor or parallel processing architecture." See, e.g., Ex. B, col. 12, lines 17-19. Augsburg in combination with the IBM Manual suggests a one-to-one relationship between a microprocessor 100, instruction cache 101, IAR 110, MSR/EXISR, and control logic 103 as is implicitly described in claim 11. Thus, it would have been obvious to a person having ordinary skill at the time of the invention to retain the one-to-one relationship of elements described in Augsburg in a single processor comprised of a multiprocessor system to achieve the recited combination of claim 11. Alternatively, claim 11 merely recites the duplication of components that are also recited in claim 1. The "mere duplication of parts has no patentable significance unless a new and unex- pected result is produced." MPEP $ 2144.04(VI.B.). Accordingly, it would have been obvious to a person having ordinary skill in the art to duplicate the components of claim 1 to achieve the combination of claim 11. . BER TETAPI EUR HISTOR IA Augsburg et al., U.S. Patent No. 5,996,092_ ("Augsburg"); IBM, "PowerPC 403GA User's * *331 Claim Language Manual" ("the IBM Manual"); and Nakamoto, U.S. Patent No. 5,361,348 ("Nakamoto") 1. A processor having a real time Augsburg teaches, e.g., a microprocessor 100, which may debugging interface, said processor be a PowerPC microprocessor model no. PPC403GA, comprising: having a non-invasive, real time instruction trace interface. See, e.g., col. 3:6-9; col. 5:41-45. a) instruction memory means for Augsburg teaches, e.g., an instruction cache 101 for storing instructions to be executed storing instructions to be executed by the microprocessor by said processor; 100. See, e.g., col. 5:36-39, 48-52. b) program counter means directly Augsburg teaches, e.g., an instruction address register coupled to said instruction memory (IAR) 110, "commonly known as the program counter," means for indexing said for indexing the instructions. See, e.g., col. 5:62-65; col. instructions; 6:12-15. c) cause register means for indicating information regarding interrupts and exceptions; and Nakamoto teaches, e.g., a program counter (PC) 1 that is directly coupled to, e.g., a program memory 2. See Fig. 2; see, e.g., col. 2:21-23. The IBM Manual for the PPC403GA teaches, e.g., a machine state register (MSR) and/or an external interrupt status register (EXISR) for indicating information regarding interrupts and exceptions. See, e.g., chapter 6, pages 6-1 to 6-4, 6-9 to 6-11. Augsburg teaches, e.g., control logic 103 that encodes status information received from the microprocessor 100 d) first decoder means for indicating information about an Page 22 of 28 BC_GEN_0002067 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 BRENDA 331 Claim Language TETA M. instruction executed by said processor during a clock cycle, Augsburg et al., U.S. Patent No. 5,996,092 ("Augsburg"); IBM, "PowerPC 403GA User's Manual" ("the IBM Manual"); and Nakamoto, U.S. Patent No. 5,361,348 ("Nakamoto") that may include the execution of an instruction, the direction of any executed branches, and the taking of any exception vectors. See, e.g., col. 7:36-40. The information is provided during a clock cycle. See, e.g., col. 7:18, 47-49. said first decoder means being directly coupled to said instruction memory means, said program counter means, and said cause register means, Nakamoto teaches, e.g., an instruction decoder and timing controller 3 that is directly coupled to the program memory 2, the PC 1, and, e.g., the latch register 6 ("cause register 6" in box 302 of Fig. 3). See Fig. 2. said first decoder means having a first output, Augsburg teaches that the control logic 103 has, e.g., a. three bit output [0:2] on pins 118 via bus 105 and driver 107. See, e.g., col. 7:42-46; Fig. 1. wherein said first output provides information regarding activity of said processor in real time. Augsburg teaches that the three bit output on pins 118 provides the encoded status information in real time. See, e.g., col. 3:6-10; col. 7:45-46. | 2. A processor according to claim | See claim 1 above. Augsburg teaches that the encoded status information received from the microprocessor 100 may include the direction of any executed branches and the taking of any exception vectors. See, e.g., col. 7:36-40. said information regarding processor activity includes information as to at least one of a jump instruction has been executed, a jump instruction based on the contents of a register has been executed, a branch has been taken, and an exception has been encountered. See claim 1 above. 3. A processor according to claim 1, wherein: said clock cycle is a processor clock cycle, and Augsburg teaches that the clock cycle is a processor clock cycle. See, e.g., col. 4:56-58; col. 10:5-6. said first decoder means updates said information about each instruction executed by said processor for each said processor Augsburg teaches that the control logic 103 outputs the encoded status information about each instruction executed by the microprocessor 100 for each processor clock cycle. See, e.g., col. 7:9-61; col. 4:27-29, 56-58. Page 23 of 28 BC_GEN_0002068 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 *331 Claim Language Augsburg et al., U.S. Patent No. 5,996,092 (Augsburg"); IBM, "PowerPC 403GA User's Manual" ("the IBM Manual"); and Nakamoto, U.S. Patent No. 5,361,348 ("Nakamoto") clock cycle. See claim 3 above. 4. A processor according to claim 3, wherein: said information about each instruction executed by said processor includes an indication whether or not an instruction has been executed since the previous processor cycle. Augsburg teaches that the encoded status information about each instruction executed by the microprocessor 100 includes an indication whether or not an instruction has been executed since the previous processor cycle. See, e.g., col. 7:18-34. See claim 1 above. 5. A processor according to claim 1, wherein: said first output consists of a three bit parallel output. Augsburg teaches that the control logic 103 has, e.g., a three bit output [0:2] on pins 118 via bus 105 and driver | 107. See, e.g., col. 7:42-46; Fig. 1. | 11. An embedded system having a Augsburg teaches an embedded system that has a plurality plurality of processors and a real 1 of processors. See, e.g., col. 12:17-19. Augsburg teaches, time debugging interface, said e.g., a microprocessor 100, which may be a PowerPC system comprising: microprocessor model no. PPC403GA, having a real time, non-invasive instruction trace interface. See, e.g., col. 3:6-9; col. 5: 41-45. a) a plurality of instruction | Augsburg teaches, e.g., an instruction cache 101 for memory means for storing storing instructions to be executed by the microprocessor instructions to be executed by a 100. See, e.g., col. 5:36-39, 48-52. respective one of said plurality of processors; b) a plurality of program counter Augsburg teaches, e.g., an instruction address register means, each directly coupled to a (IAR) 110,"commonly known as the program counter," respective one of said plurality of for indexing the instructions. See, e.g., col. 5:62-65; col. instruction memory means for 6:12-15. indexing contents of said instruction memory means; Nakamoto teaches, e.g., a program counter (PC) 1 that is directly coupled to, e.g., a program memory 2. See Fig. 2; see, e.g., col. 2:21-23. c) a plurality of cause register | The IBM Manual for the PPC403GA teaches, e.g., a means for indicating information machine state register (MSR) and/or an external interrupt regarding interrupts and exceptions status register (EXISR) in the microprocessor for for a corresponding one of said indicating information regarding interrupts and exceptions plurality of processors, for the microprocessor. See, e.g., chapter 6, pages 6-1 to 6-4, 6-9 to 6-11. Page 24 of 28 BC_GEN_0002069 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 Hitt re *331 Claim Language Augsburg et al., U.S. Patent No. 5,996,092 ("Augsburg"); IBM, "PowerPC 403GA User's Manual" ("the IBM Manual"); and Nakamoto, U.S. Patent No. 5,361,348 ("Nakamoto") LUETTER each of said cause register means being directly coupled to a respective one of said processors; and d) a plurality of first decoder means, The MSR and/or EXISR are directly coupled to the microprocessor by way of being on the microprocessor, like the cause registers 26a is on the processor 12a in the 331 patent. See "331 patent, Figs. 1A and 1B. Augsburg teaches, e.g., control logic 103. See, e.g., col. 7:36-40. each said first decoder means directly coupled to a respective one of said instruction memory means, to a respective one of said program counter means, and a respective one of said cause register means, Nakamoto teaches, e.g., an instruction decoder and timing controller 3 that is directly coupled to the program memory 2, the PC 1, and, e.g., the latch register 6 (cause register 6" in box 302 of Fig. 3). See Fig. 2. each said first decoder means for indicating information about an instruction executed during a clock cycle by a respective one of said processors, Augsburg teaches that the control logic 103 encodes status information received from the microprocessor 100 that may include the execution of an instruction, the direction of any executed branches, and the taking of any exception vectors. See, e.g., col. 7:36-40. The information is provided during a clock cycle. See, e.g., col. 7:18, 47-49. each said first decoder means having a first output, Augsburg teaches that the control logic has, e.g., a three bit output (0:2] on pins 118 via bus 105 and driver 107. See, e.g., col. 7:42-46; Fig. 1. wherein each said first output provides information regarding activity of said processor in real time. Augsburg teaches that the three bit output on pins 118 provides the encoded status information in real time. See, e.g., col. 3:6-10; col. 7:45-46. See claim 11 above. 12. An embedded system according to claim 11, wherein: said information regarding processor activity includes information as to at least one of a jump instruction has been executed, a jump instruction based on the contents of a register has been executed, a branch has been taken, and an exception has been Augsburg teaches that the encoded status information received from the microprocessor 100 may include the direction of any executed branches and the taking of any exception vectors. See, e.g., col. 7:36-40. Page 25 of 28 BC_GEN_0002070 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 BA NNS. 2x 331 Claim Language Augsburg et al., U.S. Patent No. 5,996,092 ("'Augsburg"); IBM, "PowerPC 403GA User's Manual" ("the IBM Manual"); and Nakamoto, U.S. Patent No. 5,361,348 ("Nakamoto") IS encountered. See claim 11 above. 13. An embedded system according to claim 11, wherein: said clock cycle is a processor clock cycle, and Augsburg teaches that the clock cycle is a processor clock cycle. See, e.g., col. 4:56-58; col. 10:5-6. each said first decoder means updates said information about each instruction executed by a respective processor for each said processor clock cycle of said respective processor. Augsburg teaches that the control logic 103 continuously outputs the encoded status information about each instruction executed by the microprocessor 100 for each processor clock cycle. See, e.g., col. 7:9-61; col. 4:27-29, 56-58. See claim 13 above. 14. An embedded system according to claim 13, wherein: each said information about each instruction executed by a respective processor includes an indication whether or not an instruction has been executed since the previous processor cycle of said respective processor. Augsburg teaches that the encoded status information about each instruction executed by the microprocessor 100 includes an indication whether or not an instruction has been executed since the previous processor cycle. See, e.g., col. 7:18-34. See claim 11 above. 15. An embedded systém according to claim 11, wherein: each of said first outputs consists of a three bit parallel output. Augsburg teaches that the control logic 103 has, e.g., a three bit output [0:2] on pins 118 via bus 105 and driver 107. See, e.g., col. 7:42-46; Fig. 1. 19. An embedded system See claim 11 above. according to claim 11, wherein: said system is embodied on a chip | Augsburg teaches that the processor 100"comprised of a having a plurality of pins, number of processing engines in a multiprocessor or parallel processing architecture" is in an integrated circuit 10 on a single silicon chip. See, e.g., col. 5:34-41; col. 12:17-19. The integrated circuit 10 has pins 118 and pins 119. See, e.g., Fig. 1; col. 7:10-11, 62-64. said first and second outputs are provided via some of said plurality of pins. | Augsburg teaches that the "first" output is provided via pins 118. See, e.g., col. 7:45-46. Augsburg teaches that a "second" output is provided via pins 119. See, e.g., col. Page 26 of 28 BC_GEN_0002071 2 PTO/SB/57 (08-08) Approved for use through 08/31/2010. OMB 0651-0033 U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERVE Under the Paperwork Reduction Act of 1995, no persons are required to a collection of information unless it displays a valid OMB control number. 12. X The attached detailed request includes at least the following items: a. A statement identifying each substantial new question of patentability based on prior patents and printed publications. 37 CFR 1.510(b)(1) b. An identification of every claim for which reexamination is requested, and a detailed explanation of the pertinency and manner of applying the cited art to every claim for which reexamination is requested. 37 CFR 1.510(b)(2) A proposed amendment is included (only where the patent owner is the requester). 37 CFR 1.510(e) 13. 14. * a. -It is certified-that-a copy of this request (if-filed by other than the patent-owner) has been served in its entirety on the patent owner as provided in 37 CFR 1.33(c). The name and address of the party served and the date of service are: Schwabe, Williamson & Wyatt PacWest Center, 1211 SW Fifth Avenue, Suite 1900 Portland, Oregon 97204 Date of Service: February 14, 2011 L; or b. A duplicate copy is enclosed since service on patent owner was not possible. 15. Correspondence Address: Direct all communication about the reexamination to: X The address associated with Customer Number: 25962 OR Firm or Individual Name Address City State Zip Country: Telephone Email 16. X The patent is currently the subject of the following concurrent proceeding(s): L a Copending reissue Application No. - O b. Copending reexamination Control No.. C. Copending Interference No. d. Copending litigation styled: Xilinx, Inc. v. Invention Investment Fund I LP et al., (N.D. Cal. Feb. 14, 2011) (No. 4:11-cv-00671-LB) WARNING: Information on this form may become public. Credit card information should not be included on this form. Provide credit card information and authorization on PTO-2038. _March 4, 2011 Date Authorized Signature For Patent Owner Requester Adam C. Davenport Typed/Printed Name 66,311 Registration No. X For Third Party Requester [Page 2 of 2] BC_GEN_0002044 2 CERTIFICATE OF SERVICE The undersigned hereby certifies that a true and accurate copy of this REQUEST FOR EX PARTE REEXAMINATION OF U.S. PATENT NO. 6,321,331 B1 is being served, in its entirety, via First Class Mail, postage prepaid, on the following counsel of record: Schwabe, Williamson & Wyatt PacWest Center, 1211 SW Fifth Avenue, Suite 1900 Portland, Oregon 97204. on the 4th day of March, 2011. Adam C. Davenport BC_GEN_0002045 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 (331 Claim Language INSTA Augsburg et al., U.S. Patent No. 5,996,092 ("Augsburg"); IBM, "PowerPC 403GA User's. Manual" ("the IBM Manual"); and Nakamoto, U.S., Patent No. 5,361,348 ("Nakamoto") 7:62-8:4. (Requestor notes that "said ... second outputs" lacks antecedent basis and is therefore indefinite under 35 U.S.C. $ 112, second paragraph. See MPEP $ 2173.05(e).) 20. An embedded system See claim 19 above. according to claim 19, wherein: each of said first outputs is an n-bit | Augsburg teaches the three bit output [0:2] on three pins parallel output, and 118. See, e.g., col. 7:9-11, 42-46; Fig. 1. The three bit information output on the three pins 118 is a parallel output. said second output is a serial output. Augsburg teaches that the output over pins 119 is a serial output. See, e.g., col. 7:62-8:4. Page 27 of 28 BC_GEN_0002072 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 III. CONCLUSION Because claims 1,-5, 11-15, and 19-22 in the '331 patent are not patentable over the prior; art references discussed herein, substantial new questions of patentability are raised. Further, the references submitted read on each and every limitation of claims 1-5, 11-15, and 19-22 of the '331 patent, and disclose claim elements previously relied upon by the Applicants in distinguishing the claims over the cited prior art during prosecution. For the above reasons, a substantial new question of patentability is raised, and reexamination of U.S. Patent No. 6,321,331 B1 is respectfully requested. - ... Respectfully submitted, 4 March 2011 Date Adam C. Davenport Reg. No. 66,311 Slater & Matsil, L.L.P. 17950 Preston Rd. Suite 1000 Dallas, TX 75252 972-732-1001 972-732-9218 (fax) Page 28 of 28 BC_GEN_0002073 2 IN THE UNITED STATES PATENT AND TRADEMARK OFFICE U.S. Patent No.: 6,321,331 B1 Issued: November 20, 2001 Filed: April 22, 1998 Docket No.: Patentee: 6321331RX Roy et al. For: Real Time Debugger Interface for Embedded Systems Mail Stop Ex Parte Reexam Attn: Central Reexamination Unit Commissioner for Patents P.O. Box 1450 Alexandria, VA 22313-1450 REQUEST FOR EX PARTE REEXAMINATION UNDER 35 U.S.C. SS 302-307 Dear Sir: This is a Request for Ex Parte Reexamination, pursuant to the provisions of 35 U.S.C. $8 302–307 (2002), of claims 1-5, 11-15, and 19-22 of United States Patent No. 6,321,331 B1 ("the "331 patent). The "331 patent, a copy of which is provided as Exhibit A, issued on November 20, 2001, to Roy et al. from an application filed on April 22, 1998. As set forth below, the prior art references submitted herewith were not previously before the Office during the original prosecution of the "331 patent. Furthermore, these references present new, non-cumulative technological teachings not considered during the "331 patent prosecution history. In this request, the references submitted read on each and every limitation of claims 1-5, 11-15, and 19-22 of the "331 patent, and disclose claim elements previously relied upon by the Applicants in distinguishing the claims over the cited prior art during prosecution. In particular, the references submitted read on the limitations of the "directly coupled" elements in claims 1 and 11, which were relied upon during prosecution to distinguish over the prior art- that was of record during the original prosecution. Also, the references submitted read on the limitation "said information about each instruction executed by said processor includes an indication whether or not an instruction has been executed since the previous processor cycle" of claim 21, which was relied upon during prosecution to distinguish over the prior art that was of record during the original prosecution. Further, the references read on the limitation "each said information about each instruction executed by a respective processor includes an indication BC_GEN_0002046 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 whether or not an instruction has been executed since the previous processor cycle of said respective processor" of claim 22, which was relied upon during prosecution to distinguish over the prior art that was of record during the original prosecution. Accordingly, these prior art references present substantial new questions of patentability, and invalidate claims 1-5, 11-15, and 19-22 of the "331 patent. ------- ------------------ -- --- 1. SUBSTANTIAL NEW QUESTION ("SNO") OF PATENTABILITY Section 1.A, below, provides a list of all prior art references relied on in the present request. Section 1.B provides a statement applying each of the references to claims 1-5, 11-15, and 19-22 of the "331 patent. Section I.C provides an overview of the subject matter of the "331 patent and its prosecution history. Section I.D provides an explanation of the claim interpretation for the purpose of this request. A. Listing of Prior Art Patents and Printed Publications Reexamination of claims 1-5, 11-15, and 19-22 of the "331 patent is requested in view of the following references: Exhibit B U.S. Patent No. 5,996,092 to Augsburg et al., filed on December 5, 1996, and issued on November 30, 1999 ("Augsburgº), which is prior art under at least 35 U.S.C. § 102(e). Exhibit C. IBM PowerPC 403GA User's Manual, Second Edition, March 1995, [online], [retrieved on 2011-2-9] Retrieved using Internet <URL: http://i.want.to.surf.free.fr/NCD/HTML/403 gaum.pdf> ("the IBM Manual"), which is prior art under at least 35 U.S.C. § 102(b). Exhibit D U.S. Patent No. 5,361,348 to Nakamoto, issued on November 1, 1994 ("Nakamoto"), which is prior art under at least 35 U.S.C. § 102(b). B. Statement Pointing Out Each SNQ of Patentability In summary, the following rejections are described in the present request. For ease of reference, a page number is also provided to show where the corresponding analysis begins. Page 2 of 28 BC_GEN_0002047 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 1. Claims 21 and 22 are unpatentable over Augsburg in view of the IBM Manual under 35 U.S.C. § 103(a)...... .................11 Claims 21 and 22 are unpatentable over Augsburg (Ex. B) in view of the IBM Manual (Ex. C), under 35 U.S.C. § 103(a). Neither Augsburg nor the IBM Manual was previously before the Office. 2. Claims 1-5, 11-15, 19, and 20 are unpatentable over Augsburg in view of the IBM Manual, and further in view of Nakamoto under 35 U.S.C. § 103(a) .........20 Claims 1-5, 11-15, 19, and 20 are unpatentable over Augsburg (Ex. B) in view of the IBM Manual (Ex. C), and further in view of Nakamoto (Ex. D) under 35 U.S.C. $ 103(a). None of Augsburg, the IBM Manual, and Nakamoto was previously before the Office. C. Overview of the "331 Patent and Its Prosecution History Section I.C.1 provides an overview of the subject matter of the "331 patent, while Section I.C.2 provides an overview of its prosecution history. 1. The "331 Patent The "331 patent (Ex. A) relates generally to systems for the "real time debugging of firmware in embedded systems." See, e.g., Ex. A, "331 patent, col. 1:8-10. The "331 patent contains 22 total claims, with claims 1, 11, 21, and 22 being independent. All of the claims require at least one processor and a real time debugging interface. All of the claims further require instruction memory means, program counter means, cause register means, and first decoder means. 2. The Prosecution History of the "331 Patent A copy of selected portions of the prosecution history of the "331 patent is provided in Exhibit E. The '331 patent issued from U.S. Patent Application Serial No. 09/064,474 ("the '474 application"), filed on April 22, 1998, and naming Subhash C. Roy, Paul Hembrook, Eugene L. Parrella, and Richard Mariano as co-inventors. The 474 application was originally filed with 25 total claims, of which three were independent. Independent application claims 26 and 27 were Page 3 of 28 BC_GEN_0002048 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 added during prosecution. A cross-reference between the issued claims and the application claims from which they issued is provided below for convenience. Issued Appl. Issued Appl. Issued Appl. Issued Appl. Claim Claim Claim Claim Claim Claim Claim Claim | 13 13 19 14. 20 20 15 -21 -26 10 | 16 22 27 19 14 15 10 | 16 17 11 17 12 18 18 In an Office Action dated June 10, 1999, the Examiner rejected application claims 1-25 under 35 U.S.C. § 103(a) as being unpatentable over U.S. Patent No. 5,473,754 to Folwell et al. ("Folwell"). See Ex. E, '331 File History, Office Action, p. 3 (June 10, 1999). In response, the Applicants mailed an amendment on September 10, 1999, canceling application claim 22, and amending claims 5, 15, and 21. Specifically, dependent application claims 5 and 15 were each amended to change "is" to "consists of," and independent application claim 21 (later cancelled) was amended to require "wherein said step of providing information about processor activity includes providing information about every instruction executed by the processor." See Ex. E, "331 File History, Amendment, pp. 1-2 (Sep. 10, 1999). The Applicants also presented arguments distinguishing, inter alia, various elements of the claims from Folwell. In introductory statements, the Applicants stated, In general, the present invention is concerned with providing a real time debugging interface for an embedded system which may contain several processors on a single chip. It is an important object of the invention to provide a real time debugger interface which does not interfere with the operation of the processor(s) or system bus. It is also an important object that the debugger interface of the invention use the fewest number of pins possible while at the same time providing a substantial amount of information about the executed instructions. Id.-at-p. 3. With respect-to independent-application-claim-1, for example, the Applicants-argued -- the term "program counter" was mentioned in Folwell, but Folwell failed to identify it in any figures or to identify it as being "coupled to said instruction memory means for indexing said instructions" as required by application claim 1. See id. at pp. 3-4. With respect to the "first decoder means," the Applicants further argued, "[Folwell] fails to teach or suggest that a decoder is coupled to a program counter or coupled to a cause register." Id. at p. 4. Finally, with regard to real time operation, the Applicants argued: Page 4 of 28 BC_GEN_0002049 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 [W]hen the Applicant states that the present invention (not just the decoder portion of the invention) operates in real time, it means that the operation of the processor is not interrupted or slowed down to collect debugging data. On the contrary, Folwell et al. specifically calls for stopping the execution of the program during certain debugging procedures. Id. at p. 5. With respect to independent application claim 11, for example, the Applicants took issue with the Examiner's assertion that Folwell "obviously suggests that plural elements could be coupled to the same workstation via the expandable SCSI bus" by arguing, "However, contrary to the Examiner's opinion, such a coupling would not result in 'an embedded system having a plurality of processors' as claimed in claim 11. Rather, it would result in a plurality of RSP devices all coupled to the same workstation." Id. The Applicants concluded: Folwell et al. (1) fails to suggest the claimed program counter means coupled to instruction memory means, (2) fails to suggest the coupling of cause registers to processors, (3) fails to suggest first decoder means coupled to instruction memory means, program counter means, and cause register means, and (4) fails to provide information in real time. Id. at p. 6. The Applicants made further arguments distinguishing elements of various dependent claims over Folwell, which arguments are not repeated herein except with regard to claims 3 and 13 and to claims 4, 14, and 23. See id. at pp. 6-12. The Applicants distinguished Folwell from claims 3 and 13 as failing to teach "said first decoder means updates said information about each instruction executed by said processor for each said processor clock cycle" but teaching "only sending information about certain discontinuities in program execution which occur at branches, subroutines, etc." Id. at p. 7. Regarding claims 4, 14, and 23, the Applicants distinguished Folwell because "Folwell et al. cannot perform the function claimed in claims 4, 14, and 23." Id. at p. 8. Those claims recited "said information about each instruction executed by said processor includes an indication whether or not an instruction has been executed since a previous processor cycle." Id. The Applicants quoted Folwell and emphasized the teaching of Folwell that "the debug port ... captures program flow data only when certain discontinuities occur." Id. The Examiner thereafter issued a new Office Action rejecting application claims 4, 14, and 23 under 35 U.S.C. $ 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the Applicants regard as the invention. The Examiner further rejected application claims 1, 2, 5, 11, 12, 15, 19, and 20 under 35 U.S.C. § 103(a) as being unpatentable over Folwell in view of U.S. Patent No. 5,440,700 to Kaneko Page 5 of 28 BC_GEN_0002050 2 Request for Ex Parte Reexamination U.S. Patent No. 6,321,331 B1 ("Kaneko") and rejected claims 3, 13, 21, 24, and 25 under 35 U.S.C. § 103(a) as being unpatentable over Folwell in view of U.S. Patent No. 5,428,618 to Ueki ("Ueki"). Claims 4, 14, and 23 were indicated as allowable if rewritten to overcome the § 112, second paragraph, rejections noted in the Office Action and to include all of the limitations of the base claim and any intervening claims. Claims 6-10 and 16-18 were objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Ex. E, "331 File History, Office Action (Nov. 24, 1999). The Applicants conducted an Examiner Interview on February 25, 2000. Ex. E, "331 File History, Interview Summary (Mar. 3, 2000). The Examiner indicated the Examiner and the Applicants disagreed on the interpretation of the term "coupled." Id. The Examiner further noted that an amendment to "directly coupled" would require a new search. Id. In response to the Office Action of November 24, 1999, and the Examiner Interview of February 25, 2000, the Applicants mailed a response on March 10, 2000, in which they added new claims 26 and 27 and amended claims 1, 6, 11, 16, 21, and 23. Ex. E, "331 File History, Amendment (Mar. 10, 2000). Specifically, the Applicants amended claims 1, 6, 11 and 16 to change "coupled" to "connected" and provided explanatory remarks for the change as follows: It is the understanding of the undersigned that the word "connected" is typically used to mean directly coupled whereas the word "coupled" allows for intermediate elements between the elements which are "coupled." Therefore, the claims have been amended to change the word "coupled" to the word "connected." It is submitted that this is the same as "directly coupled." Id. at p. 6. Independent application claim 21 (later cancelled) was amended to recite "wherein said step of providing information about processor activity includes providing information that the processor has not executed an instruction during the last processor cycle" rather than "wherein ... information about every instruction-executed by the processor." Id. at p. 3. Dependent- application claim 23 (later cancelled) was similarly amended to recite "wherein: said step of providing information about processor activity includes providing information about every instruction executed by the processor" from "wherein: ... information about every instruction executed by the processor." Id. The Applicants indicated new claims 26 and 27 (issued claims 21 and 22) correspond to claims 4 and 14, which the Examiner had indicated as allowable. Id. at p. 6. . Page 6 of 28 -. - . . . BC_GEN_0002051