Bicameral LLC v. NXP USA, Inc. et al

Western District of Texas, txwd-6:2018-cv-00294

Exhibit Hansquine Ex. 1

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4 Hansquine Declaration Exhibit 1 4 USOO6321331B1 (12) United States Patent (10) Patent No.: US 6,321,331 B1 Roy et al. (45) Date of Patent: Nov. 20, 2001 (54) REAL TIME DEBUGGER INTERFACE FOR Primary Examiner John F. Niebling EMBEDDED SYSTEMS Assistant Examiner Stacy Whitmore (75) Inventors: Subhash C. Roy, Stamford; Paul (74) Attorney, Agent, or Firm-David P Gordon; David S Hembrook, New Milford; Eugene L. Jacobson; Thomas A Gallagher Parrella, Monroe; Richard Mariano, Bethel, all of CT (US) (57) ABSTRACT (73) Assignee: Transwitch Corporation, Shelton, CT A debugging interface includes a pair of decoderS and an (US) event history buffer coupled to the Sequencer of a processor. (*) Notice: Subject to any disclaimer, the term of this The first decoder is coupled to the program counter of the patent is extended or adjusted under 35 sequencer and the Instruction RAM of the processor. The U.S.C. 154(b) by 0 days. Second decoder is coupled to the cause register of the (21) Appl. No.: 09/064,474 Sequencer and the event history buffer is also coupled to the (22) Filed: Apr. 22, 1998 cause register. The first decoder provides a three bit real time output which is indicative of the processor activity on a (51) Int. Cl." .................................................... G06F 9/30 cycle by cycle basis. The three bit output indicates Seven (52) U.S. Cl. .............................................................. 712/244 (58) Field of Search ..................................... 712/227, 228, different conditions: whether the last instruction executed by 712/229, 230, 231, 244; 714/23-48, 15, the processor was an inc, an exception, an exception with no 16, 38, 25; 717/4 event history buffer entry, or a branch taken, whether there (56) References Cited has been no instruction executed Since the last clock cycle, U.S. PATENT DOCUMENTS and whether a jump was an immediate jump or a jump to a register. The event history buffer is loaded with more 5,428,618 6/1995 Ueki ..................................... 395/709 detailed information about the instruction last executed 5,440,700 * 8/1995 Kaneko ................................ 712/227 5,473,754 * 12/1995 Folwell .................................. 714/45 when the first decoder indicates that the last instruction was 5,491,793 2/1996 Somasundaram ...................... 714/45 an exception or a jump to a register, and when there is a 5,513,346 4/1996 Satagopan et al. .................... 714/48 5,544.311 8/1996 Harenberg .............................. 714/40 change in State of an interrupt line or an internal processor 5,572,672 11/1996 Dewitt .................................... 714/47 exception. An exemplary implementation of the debugging 5,640,542 6/1997 Whitsel ........................... 395/500.49 5,724.505 3/1998 Argade ................................... 714/45 interface is embodied on an ASIC chip having three pro 6,052,774 * 4/2000 Segars .................................. 712/200 ceSSors. Each processor is provided with a first and Second OTHER PUBLICATIONS decoderS and a single event history buffer for all processors is provided on the chip. Meriam-Webster, "Meriam-Websters's Collegiate Dictio nary, Tenth Ed.", pp. 244-245, and 328, 1997.* 22 Claims, 3 Drawing Sheets * cited by examiner is CLOCK --20a 19 All RAM 28a TIAESTAMP 28, REGSTER DECODER CAUSE REGISTER COUNTER CECOER -20b AL 28b. PROGRA DECODER ! 0 CASE REGISTER COUMER I BECOCER -32b Y.22824 228c. DECODER CAUSE PROGRA, H REGISTER COUNTER ECOEER - 14 4 U.S. Patent Nov. 20, 2001 Sheet 1 of 3 US 6,321,331 B1 i: o | 4 U.S. Patent US 6,321,331 B1 4 U.S. Patent Nov. 20, 2001 Sheet 3 of 3 US 6,321,331 B1 4 US 6,321,331 B1 1 2 REAL TIME DEBUGGER INTERFACE FOR The user can Set Specific bus event conditions for which EMBEDDED SYSTEMS memory is mapped by writing to a set of breakpoint regis ters. A disadvantage of this method is that it requires an BACKGROUND OF THE INVENTION additional set of I/O pins for the chip so that the external 1. Field of the Invention debug memory can be coupled to the chip. This may require a significant number of pins since the addresses to be The invention relates to Systems and methods for debug mapped may be 32 or 64 bits wide. ging Software in real time. More particularly, the invention Still another tracing and trapping method is disclosed in relates to Systems and methods for the real time debugging U.S. Pat. No. 5,513,346 to Satagopan et al. entitled "Error of firmware in embedded Systems, e.g. ASIC chips having Condition Detector for Handling Interrupt in Integrated one or more processors on a Single chip. Circuits Having Multiple Processors." According to this 2. State of the Art method, an interrupt processor controller intercepts all inter Software debugging may be accomplished in a number of rupts and routes them to the appropriate processor in a ways, Some of which are not performed in real time. A multiprocessor chip. The interrupt processor controller traditional debugging technique is to Step through program 15 includes logic which determines when an interrupt will instructions at a rate much slower than the rate at which the cause an error because a previously instigated interrupt has program is designed to run in real time. By Stepping through not been cleared. When Such an error is detected, a bit is set the program instructions one-by-one, errors can be observed in an error detect register, the bit corresponding to an as they happen and the program code lines executed imme interprocessor interrupt channel. The bits in the register are diately prior to the error can be analyzed to find the cause of ORed and a single bit output indicates the occurrence of an the error. This technique is not helpful, however, if the error error. The register may then be examined to determine the in program execution is the result of timing errors or other location of the interrupt error in the executing code. This types of errors which only occur when the program is method does not interfere with the system bus and does not running at real time Speed. AS used herein, the term "real require very many additional pins on the chip. However, the time" means the rate at which a program must execute in 25 debugging information that it provides is limited. order to process the incoming data rate which may be quite The Motorola MPC-860 PowerQuiccTM includes a pro high. gram development System interface port which provides a A widely used technique for debugging a program which three bit output indicative of the State of the program is running in real time is called "tracing. Tracing involves execution as the program is being executed. The MPC-860 recording the transactions performed by the computer as it is a 40 mHz communications controller but the development executes the program code. The trace of activities performed System interface port is only operable at a rate of 4 mHz. by the computer during the time of a failure can be a useful Thus, the port can not be used for real time debugging. The guide in isolating possible causes of the failure. specifications for the MPC-860 are found in the "MPC-860 Another useful debugging tool is to Set breakpoints at 35 POWERQUICC USERS MANUAL, Copyright 1996 Selected places in the program. The breakpoints trap the flow Motorola, Inc., Schaumberg, Ill., the complete disclosure of of the Software and provide insight into whether, when, and which is incorporated herein by reference. how certain portions of the Software are entered and exited. ASIC design using one or more embedded processors An analysis of the flow of the software can provide infor poses additional debugging challenges. The prior art meth mation which is useful in isolating bugs. 40 ods of trapping instructions at a given point in time implies Many State-of-the-art tracing and trapping methods are that the System must be stopped to allow debugging of accomplished by a debug Support circuit which is connected firmware. Once the System is stopped, however, real time to the system bus, i.e. the bus which couples the CPU to events and their timing relationships are lost. If there is a memory. See, for example, U.S. Pat. No. 5,491,793 to firmware bug which is only identifiable in the presence of Somasundaram et al. entitled "Debug Support in a Processor 45 live traffic (during real time operations) it is necessary to Chip." Connecting a debug circuit to the System bus is obtain contextual information about the error before the convenient because addresses, instructions, and data can be firmware is changed. accessed via the System bus. However, coupling the debug SUMMARY OF THE INVENTION Support circuit to the System bus increases the electrical load on the bus and interferes with the operation of the bus. 50 It is therefore an object of the invention to provide a Moreover, operation of the system bus may interfere with debugging interface for tracing instructions without loss of operation of the debug Support circuit. In addition, the real time context and event interaction. System buS may not provide all the information necessary It is also an object of the invention to provide a debugging for debugging a program running on a CPU which uses interface which does not interfere with the operation of a internal cache. These CPUs will not access the system bus 55 processor or System bus. if the information they need is available in cache. If an error It is another object of the invention to provide a debug occurs while the CPU is accessing internal cache, the debug ging interface which does not require many additional pins Support circuit will not be able to access the information it on a processor chip. needs. It is a further object of the invention to provide a debug Another tracing and trapping method is disclosed in U.S. 60 ging interface which provides access to a Substantial amount Pat. No. 5,833,310 to Whistel et al. entitled "On-Chip of information about the executed instructions. In-Circuit-Emulator Memory Mapping and Breakpoint Reg In accord with these objects which will be discussed in ister Modules." According to this method, an internal bus detail below, the debugging interface of the present inven controller is coupled to the memory address bus and a match tion includes a first decoder coupled to the Sequencer of a register. When a memory address written to the address bus 65 processor and to the Instruction RAM (IRAM) of the matches an address in the match register, a memory mapping processor. The first decoder, according to the invention, module maps a memory cycle to an external debug memory. provides a real time three bit output on a cycle by cycle basis 4 US 6,321,331 B1 3 4 which is indicative of the processor activity during the last FIG. 2 is a Schematic block diagram of a debugging clock cycle. According to a presently preferred embodiment, System coupled to a chip embodying a real time debugger the three bit output indicates seven different conditions interface according to the invention. regarding processor activity. In particular, the three bit output indicates whether or not a new instruction has been DETAILED DESCRIPTION OF THE executed Since the last clock cycle, and if a new instruction PREFERRED EMBODIMENTS has been executed, whether the last instruction executed by the processor was an immediate jump, a jump to register, or Referring now to FIG. 1, an exemplary ASIC chip 10 a branch taken. In addition, the three bit output will indicate incorporating a debugger interface according to the inven whether execution of the instruction resulted in an excep tion includes three processors 12a, 12b, 12c, Sharing a tion. By recording this three bit output over time, and common clock 16 via a clock bus 17. Each processor comparing it to the actual instructions listed in the program code, important debugging information is obtained about a includes an instruction RAM (IRAM) 18a, 18b, 18c, an program which was running in real time. arithmetic logic unit (ALU) 20a, 20b, 20c, and a According to a preferred embodiment of the invention, a "Sequencer 22a, 22b, 22c. Each Sequencer includes a Second decoder and an event history buffer are coupled to 15 program counter 24a, 24b, 24c and a cause register 26a, 26b, the cause register of the Sequencer of the processor. In 26c. Each program counter contains an index of the instruc particular, the Second decoder is coupled to the enable input tions in an associated IRAM and a pointer to the index as the of the history buffer and the cause register is coupled to the instructions are executed by the processor. The cause reg data input of the history buffer. The second decoder decodes isterS Store current information about interrupts, exceptions, the contents of the cause register and enables the history and other processor functions. buffer whenever the contents of the cause register indicates According to one aspect of the invention, a first decoder an exception, a jump register instruction, or a change in the 28a, 28b, 28c is coupled to each IRAM 18a, 18b, 18c, and status of an interrupt line. Whenever the history buffer is to each Sequencer 22a, 22b, 22c, i.e., to each program enabled, information from the cause register and the pro counter and each cause register. Each first decoder has a gram counter is loaded into the buffer. By recording the three bit output 30a,30b, 30c which is available off the chip contents of the history buffer over time, and comparing the 25 10 via three pins (0, 1, 2) in real time. information to the actual program code, additional important debugging information is obtained about a program which As mentioned above, the three bit output of each first was running in real time. According to this preferred decoder 28 provides an indication of the processor activity embodiment of the invention, the seventh condition indi during the last clock cycle. Thus, the decoder 28 is arranged cated by the three bit output of the first decoder is whether to indicate whether the program counter has moved its an exception was encountered without writing to the history pointer to a new instruction. The decoder also decodes the buffer. instruction in the IRAM to provide information about the According to the presently preferred embodiment, each instruction, and decodes the contents of the cause register to entry in the event history buffer is forty-four bits. Each provide an indication of an exception encountered during the forty-four bit entry in the history buffer includes the current 35 execution of an instruction. According to a presently pre Sixteen bit time Stamp, twenty three bits from certain fields ferred embodiment, the first decoder 28 generates a three bit of the cause register or program counter, one bit indicating output which is interpreted as shown in Table 1, below. whether the entry is related to a jump or an exception, two bits identifying the processor number (in a multiprocessor TABLE 1. system), one bit identifying whether the history buffer has 40 overflowed, and a time stamp rollover bit. The history buffer Output Mnemonic Description preferably has a depth of at least Sixteen entries. OOO NC No Change An exemplary implementation of the debugging interface OO1 INC Program Counter Increment is embodied on an ASIC chip having three processors. Each O10 J Program Counter Jump Immediate processor is provided with two decoders as described above 45 O11 JR Program Counter Jump Register and a Single event history buffer is provided on the chip. 1OO ECP Exception Encountered Nine pins on the chip are used to provide access to the three 101 110 PBT RSD Program Counter Branch Taken Reserved bit outputs of each first decoder. Three pins on the chip 111 ENH Exception Encountered, No History Buffer provide Serial access (data, clock, and enable) to the contents Entry Written of the event history buffer. These twelve pins on the chip allow a diagnostic device to be coupled to the chip during 50 real time operations without interfering with the operation of The output 000 indicates that there has been no change in the chip. The outputs of the first decoders and the contents the processor Since the last clock cycle; i.e., the processor of the event history buffer can be recorded over time by the has not processed a new instruction and the program counter diagnostic device to provide a real time record of the pointer has not changed. The output 001 indicates that the processing events occurring in the chip during real time. 55 processor has processed the next instruction in the program; This real time record taken together with knowledge of the i.e., the program counter pointer has incremented to the next program code being executed provides a true picture of the instruction in the index. The output 010 indicates that the last processors execution Sequence in real time and thereby instruction processed by the processor was a "hard coded" expedite debugging of code. jump to an instruction; i.e., the instruction in IRAM pointed Additional objects and advantages of the invention will 60 to by the program counter includes code indicating that it is become apparent to those skilled in the art upon reference to a jump instruction to an absolute address in the program. The the detailed description taken in conjunction with the pro output 011 indicates that the last instruction processed by the Vided figures. processor was a jump to an instruction based on the contents BRIEF DESCRIPTION OF THE DRAWINGS of a register; i.e., the instruction in IRAM pointed to by the FIG. 1 is a Schematic block diagram of an exemplary 65 program counter includes code indicating that it is a jump implementation of a real time debugger interface according instruction to a location in the program determined by the to the invention; and value of a variable. The output 100 indicates that since the 4 US 6,321,331 B1 S 6 last clock cycle the processor has encountered an interrupt or When the instruction online 80 is executed, the first decoder an exception; i.e., the contents of the cause register contain indicates that an immediate jump (JI) has occurred and code which indicates an interrupt or exception. The output shows an output of "010". As seen in Tables 2 and 3, the 101 indicates that the last instruction processed by the program jumps to line 30. When the instructions on lines 30 processor was a pc branch taken; i.e., the instruction in and 40 are executed, the first decoder indicates that a IRAM pointed to by the program counter includes code program counter increment (INC) in the execution of the indicating that it is a branch back to another instruction. The program has occurred and shows an output of "001'. When output 110 is not presently used, but is reserved for future line 50 is executed (now for the second time) the first use. The output 111 indicates that Since the last clock cycle decoder indicates that a program counter increment (INC) in the processor has encountered an interrupt or an exception; the execution of the program has occurred and shows an and that no entry was made in the history buffer The output of "001" because the condition (D=7) for the jump in operation of the first decoder 28 and its output is illustrated line 50 is no longer valid. Line 60 is now executed and a with reference to a simple code listing which is shown below jump to a location Stored in a register occurs. The first in Table 2. decoder therefore indicates a jump to register (JR) by TABLE 2 15 showing an output of "011". Referring once again to FIG. 1, according to another LINE NUMBER INSTRUCTION aspect of the invention, each cause register 26a, 26b, 26c is 1O Input A coupled to the data input D of an event history buffer 14 and a Second decoder 32a, 32b, 32c is coupled to each cause 3O C=2 register and to the enable input E of the history buffer 14. 40 D= B- C The clock 16 provides the common clock signal to the clock 50 If D = 7 then Goto 70 input C of the history buffer 14 via the clock bus 17, and a 60 Goto A10 70 B=4 timestamp register 19 is also coupled to the clock bus 17. 8O Goto 30 The contents of the history buffer 14 are made available off 90 End 25 chip by three pins for the data, clock, and enable (D, C, E) of the history buffer 14. According to this aspect of the The listing in Table 2 has one "immediate' or "hard invention, when certain conditions are detected by one of the coded" jump instruction at line 80 and a conditional branch second decoders 32, the history buffer is enabled via the at line 50. It also has one jump instruction, line 60, based on appropriate decoder, and information from the cause register, the timestamp register, and the program counter is the contents of a register, i.e. the value of A which is input stored in the history buffer. More particularly, the second at line 10. The three bit output of the first decoder during decoder 32 enables the history buffer whenever the first execution of the instructions shown in Table 2 is illustrated in Table 3 below where the values of variables A, B, C, and decoder contains code which indicates that the processor is D are also shown. processing an instruction to jump to a location Stored in a 35 register, whenever the first decoder contains code indicating TABLE 3 an exception was encountered, and whenever the first decoder contains code indicating a change in State of an Three interrupt line. Current Next Bt 40 According to a presently preferred embodiment, when the Line Line A. B C D Mnemonic Output history buffer is enabled, it captures forty-four bits of 1O 2O INC OO1 information from the cause register or program counter, and 2O 3O 5 INC OO1 the timestamp register. The forty-four bits of information are 3O 40 5 2 INC OO1 preferably organized as illustrated in Table 4 below. 40 50 5 2 7 INC OO1 50 70 5 2 7 PBT 101 45 70 8O 4 2 7 INC 101 TABLE 4 8O 3O 4 2 7 J O10 3O 40 4 2 7 INC OO1 43 42 41 40-18 17 16 15-0 40 50 4 2 6 INC OO1 50 60 4 2 6 INC OO1 Mode Proc Cause/PC HOVRF TR Time Stamp 60 4 2 6 JR O11 50 The first bit, bit location 43, is a mode identifier indicating When the first instruction (listed in line 10) is executed, whether the entry being Stored has program counter infor the first decoder indicates that a program counter increment mation or cause register information. A two bit processor (INC) in the execution of the program has occurred and identification number is stored in binary form at bit locations shows an output of "001'. AS the program progresses from 55 42, 41. This number is used to indicate which processor's the instruction on line 10 through the instruction on line 40, information is being Stored (in the case of a multiprocessor the first decoder continues to indicate that a program counter system). The next twenty-three bits at bit locations 40 increment (INC) in the execution of the program has through 18 are used to Store cause register information or occurred and continues to show an output of "001'. When program counter information depending on the mode as the instruction on line 50 is executed, the first decoder 60 explained above. If program counter information is being indicates that a program counter branch taken (PBT) has Stored, the contents of the program counter are Stored at bit occurred and shows an output of "101'. As seen in Tables 2 locations 40 through 18. If cause register information is and 3, the program branches to line 70 because the condi being stored, bit location 40 is used to indicate whether the tional expression of line 50 is true based on the variable exception occurred while the processor was executing an D=7. Upon execution of line 70, the first decoder indicates 65 instruction in the branch delay slot. (This applies to pipe that a program counter increment (INC) in the execution of lined processors such as RISC processors.) Bit locations 39 the program has occurred and shows an output of "001'. through 35 are used to Store processor related exception 4 US 6,321,331 B1 7 8 conditions. Bit locations 34 through 18 are used to store an nized that the invention may be applied in other types of indication of all pending interrupts (external, Software, chips having greater or fewer processors. Moreover, while co-processor. The HOVRF field at bit location 17 is used to particular configurations have been disclosed in reference to indicate whether the internal event history buffer has over the indications provided by the first decoders, it will be flowed. The TR bit 16 is used to indicate a timestamp appreciated that other configurations could be used as well, rollover and bits 15 through 0 are used to store a sixteen bit provided that they achieve Substantially the same results as timestamp. According to the presently preferred described herein. It will therefore be appreciated by those embodiment, the forty-four bits captured in the history skilled in the art that yet other modifications could be made buffer 14 are serially output on data pin D over forty-four to the provided invention without deviating from its spirit clock cycles (bit serial output). and Scope as So claimed. As mentioned above, the event history buffer records What is claimed is: information when an event (either an unmasked exception or 1. A processor having a real time debugging interface, a PC jump register instruction) has occurred. According to Said processor comprising: a presently preferred embodiment, this requires an addi a) instruction memory means for storing instructions to be tional mask register per cause register and a free running 15 executed by Said processor, timestamp counter. The event masks are provided by a JTAG b) program counter means directly coupled to said test register load instruction in the Static debug interface. instruction memory means for indexing Said instruc When the cause register bits corresponding to an exception tions, are unmasked or a PC jump register instruction is c) cause register means for indicating information regard encountered, an entry is made in the history buffer. ing interrupts and exceptions, and Those skilled in the art will appreciate that the outputs of d) first decoder means for indicating information about an the first decoder 28 and the contents of the history buffer 14 instruction executed by Said processor during a clock provide a relatively complete indication of each processor's cycle, Said first decoder means being directly coupled execution Sequence in real time, particularly when Viewed in 25 to Said instruction memory means, Said program light of the actual program code which is being executed. counter means, and Said cause register means, Said first Therefore, according to the invention, a debugging System decoder means having a first output, wherein may be coupled to the first decoders and history buffer as Said first output provides information regarding activity illustrated in FIG. 2. of Said processor in real time. Turning now to FIG. 2, the outputs 30a, 30b, 30c of the 2. A processor according to claim 1, first decoders and the D.C.E terminals of the history buffer Said information regarding processor activity includes are coupled to a debugging computer 44 which preferably information as to at least one of a jump instruction has has a copy of the program code Stored therein. The three-bit been executed, a jump instruction based on the contents outputs 30a, 30b, 30c of the first decoders and the D.C.E of a register has been executed, a branch has been terminals of the history buffer are preferably coupled to an 35 taken, and an exception has been encountered. interface buffer 40 which is coupled by a serial, parallel, or 3. A processor according to claim 1, wherein: network connection 42 to the debugging computer 44. The Said clock cycle is a processor clock cycle, and interface buffer 40 is a rate decoupling buffer. In a present embodiment of the invention, the debugger interface is Said first decoder means updates Said information about provided on a 100 MHz three processor system. In that 40 each instruction executed by Said processor for each System, the data rate for reading the event history buffer is Said processor clock cycle. approximately 1 gigabit/sec. Current PCS cannot keep up 4. A processor according to claim 3, wherein: with that data rate. Therefore, the buffer 40 is provided to Said information about each instruction executed by Said prevent the loSS of event history data. processor includes an indication whether or not an AS the program is running on the ASIC 10, the debugging 45 instruction has been executed Since the previous pro computer 44 collects information from the first decoders and ceSSor cycle. the history buffer. The information collected by the com 5. A processor according to claim 1, wherein: puter 44 is associated with each line of code being executed Said first output consists of a three bit parallel output. by the ASIC by stepping through the copy of the code which 6. A processor according to claim 1, further comprising: is Stored in the computer 44. When a bug is encountered, the 50 e) second decoder means directly coupled to said cause complete history of instruction execution leading up to the register means for indicating information about con failure can be reviewed with the computer 44. The debug tents of Said cause register means, Said Second decoder ging System is non-invasive and permits debugging of means having a Second output; and programs operating in real time. f) event history buffer means for storing information There have been described and illustrated herein embodi 55 regarding processor events, Said event history buffer ments of a real time debugger interface for embedded means having a data input, a data output, and an enable systems. While particular embodiments of the invention input, Said data input being directly coupled to Said have been described, it is not intended that the invention be cause register means and Said enable input being limited thereto, as it is intended that the invention be as directly coupled to Said Second output, wherein broad in Scope as the art will allow and that the Specification 60 Said Second decoder means decodes contents of Said be read likewise. Thus, while particular encoding Schemes cause register means and enables Said event history have been disclosed with reference to the first decoder buffer means to capture contents of Said cause reg output and the history buffer contents, it will be appreciated ister means when contents of Said cause register that other encoding Schemes could be utilized provided that means indicate a particular event. they achieve Substantially the same results as described 65 7. A processor according to claim 6, wherein: herein. Also, while the invention has been illustrated with Said Second decoder means enables Said event history reference to a three-processor ASIC chip, it will be recog buffer means when contents of Said cause register 4 US 6,321,331 B1 9 10 means indicate an event including at least one of a register means, each said Second decoder means for change in Status of an interrupt line, an internal pro indicating information about contents of a respective ceSSor exception, and a jump instruction based on the cause register means, and contents of a register. f) an event history buffer means for storing information 8. A processor according to claim 6, wherein: regarding processor events, Said history buffer means Said data output of Said event history buffer means is a bit having a data input, a data output, and an enable input, Serial output. Said data input being directly coupled to each of Said 9. A processor according to claim 6, wherein: plurality of cause register means and Said enable input being directly coupled to each of Said Second outputs, Said processor is embodied on a chip having a plurality of wherein pins, each of Said Second decoder means decodes contents of Said first output and Said data output are provided via a respective cause register means and enables Said Some of Said plurality of pins. event history buffer to capture contents of Said 10. A processor according to claim 9, wherein: respective cause register means when contents of Said first output is an n-bit parallel output, and 15 Said respective cause register means indicate a par ticular event. Said data output is a Serial output. 17. An embedded system according to claim 16, wherein: 11. An embedded System having a plurality of processors each said Second decoder means enables Said event his and a real time debugging interface, Said System comprising: tory buffer means when contents of a respective cause a) a plurality of instruction memory means for Storing register means indicate an event including at least one instructions to be executed by a respective one of Said of a change in Status of an interrupt line, an internal plurality of processors, processor exception, and a jump instruction based on b) a plurality of program counter means, each directly the contents of a register. coupled to a respective one of Said plurality of instruc 18. An embedded system according to claim 16, wherein: tion memory means for indexing contents of Said Said data output of Said event history buffer means is a bit instruction memory means, 25 Serial output. c) a plurality of cause register means for indicating 19. An embedded system according to claim 11, wherein: information regarding interrupts and exceptions for a Said System is embodied on a chip having a plurality of corresponding one of Said plurality of processors, each pins, of Said cause register means being directly coupled to Said first and Second outputs are provided via Some of Said a respective one of Said processors, and plurality of pins. 20. An embedded system according to claim 19, wherein: d) a plurality of first decoder means, each said first each of Said first outputs is an n-bit parallel output, and decoder means directly coupled to a respective one of said Second output is a serial output. Said instruction memory means, to a respective one of 21. A processor having a real time debugging interface, Said program counter means, and a respective one of 35 Said processor comprising: Said cause register means, each Said first decoder means for indicating information about an instruction a) instruction memory means for storing instructions to be executed during a clock cycle by a respective one of executed by Said processor, Said processors, each Said first decoder means having a b) program counter means coupled to said instruction first output, wherein 40 memory means for indexing Said instructions, each Said first output provides information regarding c) cause register means for indicating information regard activity of Said processor in real time. ing interrupts and exceptions, and 12. An embedded System according to claim 11, wherein: d) first decoder means for indicating information about an Said information regarding processor activity includes instruction executed by Said processor during a clock information as to at least one of a jump instruction has 45 cycle, Said first decoder means being coupled to Said been executed, a jump instruction based on the contents instruction memory means, Said program counter of a register has been executed, a branch has been means, and Said cause register means, Said first decoder taken, and an exception has been encountered. means having a first output, wherein 13. An embedded System according to claim 11, wherein: Said first output provides information regarding activity Said clock cycle is a processor clock cycle, and 50 of Said processor in real time, Said clock cycle is a processor clock cycle, each Said first decoder means updates Said information Said first decoder means updates Said information about about each instruction executed by a respective pro each instruction executed by Said processor for each ceSSor for each Said processor clock cycle of Said Said processor clock cycle, and respective processor. 55 Said information about each instruction executed by 14. An embedded System according to claim 13, wherein: Said processor includes an indication whether or not each Said information about each instruction executed by an instruction has been executed Since the previous a respective processor includes an indication whether processor cycle. or not an instruction has been executed Since the 22. An embedded System having a plurality of processors previous processor cycle of Said respective processor. 60 and a real time debugging interface, Said System comprising: 15. An embedded system according to claim 11, wherein: a) a plurality of instruction memory means for Storing each of Said first outputs consists of a three bit parallel instructions to be executed by a respective one of Said output. plurality of processors, 16. An embedded system according to claim 11, further b) a plurality of program counter means, each coupled to comprising: 65 a respective one of Said plurality of instruction memory e) a plurality of Second decoder means, each directly means for indexing contents of Said instruction memory coupled to a respective one of Said plurality of cause means, 4 US 6,321,331 B1 11 12 c) a plurality of cause register means for indicating each Said first output provides information regarding information regarding interrupts and exceptions for a activity of Said processor in real time, corresponding one of Said plurality of processors, each Said clock cycle is a processor clock cycle, of Said cause register means being coupled to a respec each said first decoder means updates Said information tive one of Said processors, and about each instruction executed by a respective pro d) a plurality of first decoder means, each said first cessor for each Said processor clock cycle of Said decoder means coupled to a respective one of Said respective processor, and instruction memory means, to a respective one of Said each Said information about each instruction executed program counter means, and a respective one of Said by a respective processor includes an indication cause register means, each said first decoder means for whether or not an instruction has been executed Since indicating information about an instruction executed the previous processor cycle of Said respective pro during a clock cycle by a respective one of Said CCSSO. processors, each said first decoder means having a first output, wherein 4 USOO632133 1C1 (12) EX PARTE REEXAMINATION CERTIFICATE (9126th) United States Patent (10) Number: US 6,321,331 C1 Roy et al. (45) Certificate Issued: Jul. 10, 2012 (54) REAL TIME DEBUGGER INTERFACE FOR (56) References Cited EMBEDDED SYSTEMS To view the complete listing of prior art documents cited during the proceeding for Reexamination Control Number (75) Inventors: Subhash C. Roy, Stamford, CT (US); 90/011,532, please refer to the USPTO's public Patent Paul Hembrook, New Milford, CT Application Information Retrieval (PAIR) system under the (US); Eugene L. Parrella, Monroe, CT Display References tab. (US); Richard Mariano, Bethel, CT Primary Examiner Woo H Choi (US) (57) ABSTRACT (73) Assignee: TR Technologies Foundation LLC, A debugging interface includes a pair of decoders and an Wilmington, DE (US) event history buffer coupled to the sequencer of a processor. The first decoder is coupled to the program counter of the sequencer and the Instruction RAM of the processor. The Reexamination Request: second decoder is coupled to the cause register of the No. 90/011,532, Mar. 4, 2011 sequencer and the event history buffer is also coupled to the cause register. The first decoder provides a three bit real time output which is indicative of the processor activity on a cycle Reexamination Certificate for: by cycle basis. The three bit output indicates seven different Patent No.: 6,321,331 conditions: whether the last instruction executed by the pro Issued: Nov. 20, 2001 cessor was an inc, an exception, an exception with no event Appl. No.: 09/064,474 history buffer entry, or a branch taken, whether there has Filed: Apr. 22, 1998 been no instruction executed since the last clock cycle, and whether a jump was an immediate jump or a jump to a regis ter. The event history buffer is loaded with more detailed information about the instruction last executed when the first (51) Int. Cl. decoder indicates that the last instruction was an exception G06F II/36 (2006.01) or a jump to a register, and when there is a change in State of an interrupt line or an internal processor exception. An (52) U.S. Cl. ............................... 712/244; 714/E11.212: exemplary implementation of the debugging interface is 714/E11214 embodied on an ASIC chip having three processors. Each processor is provided with a first and second decoders and a (58) Field of Classification Search ........................ None single event history buffer for all processors is provided on See application file for complete search history. the chip. 19 E. ou CAUSE PROGRA DECODER REGISTER COUNTER CAUSE PROGRAM DECODER t REGISTER - counter HisTORY BUFFER DECODER 4 US 6,321,331 C1 1. 2 EX PARTE c) a plurality of cause register means for indicating cause information regarding interrupts and exceptions for a REEXAMINATION CERTIFICATE corresponding one of said plurality of processors, each ISSUED UNDER 35 U.S.C. 307 of said cause register being coupled to a respective one of said processors; and THE PATENT IS HEREBY AMENDED AS d) a plurality of first decoder means, each said first decoder means coupled to a respective one of said INDICATED BELOW. instruction memory means, to a respective one of said program counter means, and a respective one of said Matter enclosed in heavy brackets appeared in the 10 cause register means, each said first decoder means for patent, but has been deleted and is no longer a part of the indicating information about an instruction executed patent; matter printed in italics indicates additions made during a clock cycle by a respective one of said to the patent. processors, each said first decoder means having a first output, wherein AS A RESULT OF REEXAMINATION, IT HAS BEEN 15 each said first output provides information regarding DETERMINED THAT: activity of said processor in real time, said clock cycle is a processor clock cycle, The patentability of claims 1-18 is confirmed. each said first decoder means updates said information about each instruction executed by a respective proces Claims 19, 21 and 22 are determined to be patentable as Sor for each said processor clock cycle of said respec amended. tive processor, and Claim 20 dependent on an amended claim, is determined each said information about each instruction executed by to be patentable. a respective processor includes an indication whether or not an instruction has been executed since the previ 25 ous processor cycle of said respective processor. New claims 23-38 are added and determined to be patent 23. A processor according to claim I, wherein said infor able. mation comprises cause information. 24. A processor according to claim I, wherein said infor 19. An embedded system according to claim 11 16, mation comprises processor related exception conditions wherein: said system is embodied on a chip having a plural 30 and an indication of pending interrupts. ity of pins, said first and second outputs are provided via 25. A processor according to claim 24, wherein said indi some of said plurality of pins. cation of pending interrupts includes at least One of an indi 21. A processor having a real time debugging interface, cation of external, software, or co-processor interrupt. said processor comprising: 26. A processor according to claim I, further comprising: a) instruction memory means for storing instructions to be 35 e) event history buffer means for storing information executed by said processor; regarding processor events, said event history buffer b) program counter means coupled to said instruction means having a data input, a data Output, and an enable input, said data input being directly coupled to memory means for indexing said instructions; said cause register means. c) cause register means for indicating cause information 40 27. A processor according to claim 26, wherein said event regarding interrupts and exceptions; and history buffer means comprises a plurality of buffers. d) first decoder means for indicating information about an 28. A processor according to claim 26, wherein said event instruction executed by said processor during a clock history buffer means is configured to capture contents of said cycle, said first decoder means being coupled to said cause register means when enabled by said enable input. instruction memory means, said program counter 45 29. A processor according to claim 28, wherein said event means, and said cause register means, said first decoder history buffer is configured to be enabled when the contents means having a first output, wherein of said cause register means indicates a particular event. said first output provides information regarding activity of 30. A processor according to claim 29, wherein said par said processor in real time, said clock cycle is a proces ticular event is at least one of a change in status of an inter Sor clock cycle, 50 rupt line, an internal processor exception, or a jump instruc said first decoder means updates said information about tion based on the contents of a register: each instruction executed by said processor for each 31. A processor according to claim I, wherein said cause processor clock cycle, and register means comprises a plurality of registers. 32. A processor according to claim I, wherein said debug said information about each instruction executed by said 55 ging interface is configured to facilitate the correlation of processor includes an indication whether or not an said output of said first decoder means and the information instruction has been executed since the previous pro indicated by said cause register means with actual program cessor cycle. code being executed by said processor: 22. An embedded system having a plurality of processors 33. An embedded system according to claim II, wherein and a real time debugging interface, said system comprising: 60 said information comprises cause information. a) a plurality of instruction memory means for storing 34. An embedded system according to claim II, wherein instructions to be executed by a respective one of said said information comprises processor related exception con plurality of processors; ditions and an indication of pending interrupts. b) a plurality of program counter means, each coupled to a 35. An embedded system according to claim 34, wherein respective one of said plurality of instruction memory 65 said indication of pending interrupts includes at least one of means for indexing contents of said instruction memory an indication of external, software, of co-processor inter means, rupts. 4 US 6,321,331 C1 3 4 36. An embedded system according to claim II, further 37. An embedded system according to claim 36, wherein comprising: said event history buffer means comprises a plurality of buff eFS. e) an event history buffer means for storing information 38. An embedded system according to claim 36, wherein regarding processor events, said history bufer means S said event history buffer means is configured to capture Con having a data input, a data output, and an enable input, tents of enable by said said plurality input. of cause register means when enabled said data input being directly coupled to each of said plurality of cause register means. k. . . .