Bicameral LLC v. NXP USA, Inc. et al

Western District of Texas, txwd-6:2018-cv-00294

Exhibit Kheyfits Ex. 3

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5 Kheyfits Declaration Exhibit 3 5 Control No. Patent Under Reexamination 90/011,532 6,321,331 Office Action in Ex Parte Reexamination Examiner Art Unit MAJID A. BANANKHAH 3992 -- The MAILING DATE of this communication appears on the cover sheet with the correspondence address -- a Responsive to the communication(s) filed on 04 March 2011. loll This action is made FINAL. cp A statement under 37 CFR 1.530 has not been received from the patent owner. A shortened statutory period for response to this action is set to expire 2 month(s) from the mailing date of this letter. Failure to respond within the period for response will result in termination of the proceeding and issuance of an ex parte reexamination certificate in accordance with this action. 37 CFR 1.550(d). EXTENSIONS OF TIME ARE GOVERNED BY 37 CFR 1.550(c). If the period for response specified above is less than thirty (30) days, a response within the statutory minimum of thirty (30) days will be considered timely. Part I THE FOLLOWING ATTACHMENT(S) ARE PART OF THIS ACTION: 1. I Notice of References Cited by Examiner, PTO-892. 3. Li Interview Summary, PTO-474. 2. 11 Information Disclosure Statement, PTO/SB/08. 4. Li Part II SUMMARY OF ACTION la. Claims 1-5,11-15 and 19-22 are subject to reexamination. l b. Li Claims are not subject to reexamination. 2. CI Claims have been canceled in the present reexamination proceeding. 3. CI Claims are patentable and/or confirmed. 4. Claims 1-5, 11-15, 19-22 are rejected. 5. Li Claims are objected to. 6. Li The drawings, filed on are acceptable. 7. Li The proposed drawing correction, filed on has been (7a)11 approved (7b)n disapproved. 8. Li Acknowledgment is made of the priority claim under 35 U.S.C. § 119(a)-(d) or (f). a)EI All b)0 Some* c)E1 None of the certified copies have i Li been received. not been received. 30 been filed in Application No. 40 been filed in reexamination Control No. 50 been received by the International Bureau in PCT application No. * See the attached detailed Office action for a list of the certified copies not received. 9. Li Since the proceeding appears to be in condition for issuance of an ex parte reexamination certificate except for formal matters, prosecution as to the merits is closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 1 1, 453 0.G. 213. 10. Li Other: cc: Requester (if third party requester) U.S. Patent and Trademark Office PTOL-466 (Rev. 08-06) Office Action in Ex Parte Reexamination Part of Paper No. 20110726 BC_GEN_0002143 5 Application/Control Number: 90/011,532 Page 2 Art Unit: 3992 DETAILED EX PARTE REEXAMINATION OFFICE ACTION I.INTRODUCTION This first Office action on the merit is in response to the ex parte Request(03/04/2011) for reexamination of US 6,321,331 to Roy (hereafter '331 Roy) by a third party requester. A.Summary Claims 1-5, 11-15 and 19-22 are rejected. No requested claim is patentable or confirmed. B.References Cited in this Office Action 1. The references discussed herein are as follows: a. U.S. Patent No. 5,996,092 to Augsburg et al., filed on December 5, 1996, and issued on November 30, 1999("Augsburg"). b. IBM PowerPC 403GA User's Manual, Second Edition, March 1995,[online], [retrieved on 2011-2-9] Retrieved using Internet http://i.want.to.surf.free.fr/NCD/HTML/403gaum.pdf> ("the IBM Manual"). c. U.S. Patent No. 5,361,348 to Nakarnoto, issued on November 1, 1994 ("Nakamoto"). C.Reexam Prosecution History In the original Request (03/04/2011), primary reference "Augsburg" in combination with the "IBM Manual" and "Nakamoto" references were alleged to raise substantial new question of patentability against claims 1-5, 11-15 and 19-22 of the Roy '331patent. In the order (04/08/2011) granting Ex Parte reexamination, it was agreed that the combination of primary reference 'a' with other references 'b' and "c' identified above, raises a substantial new question of patentability against claims 1-5, 11-15 and 19-22. II. REJECTIONS A.Summary ofProposed Rejections In the request the Requester alleges that the following grounds of rejections are applicable against claims of Roy '331patent. BC_GEN_0002144 5 Application/Control Number: 90/011,532 Page 3 Art Unit: 3992 Ground #1. Claims 21 and 22 are obvious over Augsburg in view of the IBM Manual, under 35 USC § 103(a). Ground #2. Claims 1-5, 11-15, 19 and 20 are obvious over Augsburg in view of the IBM Manual, and further in view of Nakamoto under 35 USC § 103(a). B. Claim Rejections — Relevant Statutes Claim Rejections -35 USC§103 The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made. C. Detail Analysis a. Ground #1 — "Augsburg and the IBM Manual" Claims 21 and 22 are ejected under 35 U.S.C. § 103(a) as being obvious over Augsburg in View of IBM Manual. RE: claim 21 21. A processor haying a real time debugging interface, said processor comprising: Augsburg teaches a microprocessor 100, which may be a PowerPC microprocessor model no. PPC403GA, having a non-invasive, real time instruction trace interface. See, e.g., col. 3:6-9; col. 5:41-45. a)instruction memory means for storing instructions to be executed by said processor; Augsburg teaches an instruction cache 101 for storing instructions to be executed by the microprocessor 100. See, e.g., col. 5:36-39, 48-52. BC_GEN_0002145 5 Application/Control Number: 90/011,532 Page 4 Art Unit: 3992 b)program counter means coupled to said instruction memory means for indexing said instructions Augsburg teaches, e.g., an instruction address register(IAR)110, "commonly known as the program counter," for indexing the instructions. See, e.g., col. 5:62-65; col. 6:12-15. The IAR 110 is embedded on the microprocessor 100 with the instruction cache 101, and thus the IAR 110 is "coupled" to the instruction cache, either directly or indirectly. Please note that "coupled" does not require a direct connection, but "allows for intermediate elements between the elements w hich are 'coupled'." See, e.g., Amendment dated March 13, 2000(paper 8), p. 6. c)cause register means for indicating information regarding interrupts and exceptions; and The IBM Manual for the PPC403GA teaches, e.g., a machine state register(MSR)and/or an external interrupt status register(EXISR)for indicating information regarding-interrupts and- exceptions. See, e.g., chapter-6, pages 6-1 to 6-4, 6-9 to 6-11. Reasons for Combining Augsburg with the IBM Manual A person of ordinary skill in the art at a time before the invention of the '331 patent would have combined Augsburg with the IBM Manual because: (i) each of Augsburg and the IBM Manual are directed to the same problem: tracing program execution within a processor before and after a triggering event (See, Augsburg abs., and the IBM Manual Chap. 6); (ii) Augsburg teaches an integrated circuit 10, shown in Figure 1, which includes logic for performing the tracing of program code. See, e.g., id. at col. 5, lines 34-38. The integrated circuit 10 includes a microprocessor 100, which Augsburg teaches "may comprise ..., e.g., the PowerPC microprocessor, model no. PPC403GA, available from IBM Corporation." Id. at col. 5, lines 42- 45. (ii) IBM specifically discloses content of general purpose register can be written to the MSR via the move to the machine states register instruction, Id., p. 6-2; and (iii) IBM specifically discloses when an interrupt occurs the bit corresponding to the interrupt is set in the EXISR.Id., p. 6-9. BC_GEN_0002146 5 Application/Control Number: 90/011,532 Page 5 Art Unit: 3992 Further, a person of ordinary skill in the art would have been motivated to combine Augsburg with the IBM Manual because combining the prior art elements of Augsburg with the IBM Manual according to known methods would have yielded predictable results (e.g., content of the register is stored when an exception occurs and for knowing the change of the status of an interrupt), and applying the techniques of IBM Manual to improve Augsburg would have yielded predictable results (e.g., for comparing with the program code for the purpose of debugging). [See MPEP § 2143], because combining the prior art elements of IBM Manual with Augsburg according to known methods would have yielded predictable results (e.g., recording history of the even for the purpose of program analysis during runtime).[See MPEP § 21431 Additionally a person of ordinary skill in the art would have been motivated to combine Augsburg with that of IBM Manual because, Augsburg explicitly suggest the use of the PP403GA as the microprocessor 100, see, e.g., Augsburg, col. 5, lines 42-45. d)first decoder means for indicating information about an instruction executed by said processor during a clock cycle, Augsburg teaches, e.g., control logic 103 that encodes status information received from the microprocessor 100 that may include the execution of an instruction, the direction of any executed branches, and the taking of any exception vectors. See, e.g., col. 7:36-40. The information is provided during a clock cycle. See, e.g., col. 7:18, 47-49. said first decoder means being coupled to said instruction memory means, said program counter means, and said cause register means, The control logic 103, the instruction cache 101, the IAR 110,(see, e.g., Augsburg Fig. 1), and the MSR and/or EXISR (see, e.g., The IBM Manual, chapter 6)are all embedded on the microprocessor, and accordingly, are all "coupled" together, either directly or indirectly. Please note that "coupled" does not require a direct connection, but "allows for intermediate elements between the elements which are 'coupled'." See, e.g., Amendment dated March 13, 2000(Paper 8), p. 6. said first decoder means having a first output, BC_GEN_0002147 5 Application/Control Number: 90/011,532 Page 6 Art Unit: 3992 Augsburg teaches that the control logic 103 has, e.g., a three bit output [0:2] on pins 118 via bus 105 and driver 107. See, e.g., col. 7:42-46; Fig. 1. wherein said first output provides information regarding activity of said processor in real time, Augsburg teaches that the three bit output on pins 118 provides the encoded status information in real time. See, e.g., col. 3:6-10; col. 7:45-46. said clock cycle is a processor clock cycle; Augsburg teaches that the clock cycle is a processor clock cycle: See, e.g., col. 4:56-58, col. 10:5-6. said first decoder means updates said information about each instruction executed by said processor for each said processor clock cycle, and Augsburg teaches that the control logic 103 outputs the encoded status information about each instruction executed by the microprocessor 100 for each processor clock cycle. See, e.g., col. 7:9-61; col. 4:27-29, 56-58. said information about each instruction executed by said processor includes an indication whether or not an instruction has been executed since the previous processor cycle. Augsburg teaches that the encoded status information about each instruction executed by the microprocessor 100 includes an indication whether or not an instruction has been executed since the previous processor cycle. See, e.g., col. 7:18-34. R. claim 22 22. An embedded system having a plurality of processors and a real time debugging interface, said system comprising: BC_GEN_0002148 5 Application/Control Number: 90/011,532 Page 7 Art Unit: 3992 Augsburg teaches an embedded system that has a plurality of processors. See, e.g., col. 12:17-19. Augsburg teaches, e.g., a microprocessor 100, which may be a PowerPC microprocessor model no. PPC403GA, having a real time, non-invasive instruction trace i nterface. See, e.g., col. 3:6-9; col. 5: 41-45. a)a plurality of instruction memory means for storing instructions to be executed by a respective one of said plurality of processors; Augsburg teaches, e.g., an instruction cache 101 for storing instructions to be executed by the microprocessor 100. See, e.g., col. 5:36-39,48-52. b)a plurality of program counter means,each coupled to a respective one of said plurality of instruction memory means for indexing contents of said instruction memory means;, Augsburg teaches', e.g., an instruction address register(IAR)110, "commonly known as the program counter," for indexing the instructions. See, e.g., col. 5:62-65; col. 6:12-15. The EAR 110 is embedded on the microprocessor 100 with the instruction cache 101, and thus the IAR 110 is "coupled" to the instruction cache, either directly or indirectly. Please note that "coupled" does not require a direct connection, but "allows for intermediate elements between the elements which are 'coupled'." See, e.g., Amendment dated March 13, 2000(Paper 8), p. 6. c)a plurality of cause register means for indicating information regarding interrupts and exceptions for a corresponding one of said plurality of processors, each of said cause register means being coupled to a respective one of said processors; and The IBM Manual for the PPC403GA teaches, e.g., a machine state register(MSR)and/or an external interrupt status register(EXISR)in the microprocessor for indicating information regarding interrupts and exceptions. See, e.g., chapter 6, pages 6-1 to 6-4, 6-9 to 6- 11. The MSR and/or the EXISR are embedded in the microprocessor and thus are "coupled" to the microprocessor, either directly or indirectly. Please note that "coupled" does not require a direct connection, but "allows for intermediate elements between the elements which are 'coupled'." See, e.g., Amendment dated March 13, 2000(Paper 8), p. 6. BC_GEN_0002149 5 Application/Control Number: 90/011,532 Page 8 Art Unit: 3992 Reasons for Combining Augsburg with the IBM Manual See the rejection of claim 21 above for the reasons for combining Augsburg with the IBM Manual. d)a plurality of first decoder means, Augsburg teaches, e.g., control logic 103. See, e.g., at col. 7:36-40. each said first decoder means coupled to a respective one of said instruction memory means, to a respective one of said program counter means, and a respective one of said cause-register means, The control logic 103, the instruction cache 101, the IAR 110,(see, e.g., Augsburg Fig. 1), and the MSR and/or EXISR (see, e.g., The IBM Manual, chapter 6)are all embedded on the microprocessor, and accordingly, are all "coupled" together, either directly or indirectly. Please note that "coupled" does not require a direct connection; but "allows for intermediate elements between the elements which are 'coupled'." See, e.g., Amendment dated March 13, 2000(Paper 8), p. 6. each said first decoder means for indicating information about an instruction executed during a clock cycle by a respective one of said processors, Augsburg teaches that the control logic 103 encodes status information received from the microprocessor 100 that may include the execution of an instruction, the direction of any executed branches, and the taking of any exception vectors. See, e.g., col. 7:36-40. The information is provided during a clock cycle. See, e.g., col. 7:18, 47-49. each said first decoder means having a first output, Augsburg teaches that the control logic has, e.g., a three bit output [0:21 on pins 118 via bus 105 and driver 107. See, e.g., c01. 7:42-46; Fig. 1. BC_GEN_0002150 5 Application/Control Number: 90/011,532 Page 9 Art Unit: 3992 wherein each said first output provides information regarding activity of said processor in real time, Augsburg teaches that the three bit output on pins 118 provides the encoded status information in real time. See, e.g., col. 3:6-10; col. 7:45-46. said clock cycle is a processor clock cycle, Augsburg teaches that the clock cycle is a processor clock cycle. See, e.g., col. 4:56-58; col. 10:5-6. each said first decoder means updates said information about each instruction executed by a respective processor for each said processor clock cycle of said respective processor, and Augsburg teaches that the control logic 103 continuously outputs the encoded status information about each instruction executed by the microprocessor 100 for each processor clock cycle. See, e.g., col. 7:9-61; col. 4:27-29, 56-58. each said information about each instruction executed by a respective processor includes an indication whether or not an instruction has been executed since the previous processor cycle of said respective processor. Augsburg teaches that the encoded status information about each instruction executed by the microprocessor 100 includes an indication whether or not an instruction has been executed Since the previous processor cycle. See, e.g., col. 7:18-34. b. Ground #2— "Augsburg and the IBM Manual with Nakamoto" Claims 1-5, 11-15, 19 and 20 are ejected under 35 U.S.C. § 103(a) as being obvious over Augsburg in View of the IBM Manual further in view of Nakamoto. RE: claim 1 1. A processor having a real time debugging interface, said processor comprising: BC_GEN_0002151 5 Application/Control Number: 90/011,532 Page 10 Art Unit: 3992 Augsburg teaches, e.g., a microprocessor 100, which may be a PowerPC microprocessor model no. PPC403GA, having a non-invasive, real time instruction trace interface. See, e.g., col. 3:6-9; col. 5:41-45. a)instruction memory means for storing instructions to be executed by said processor; Augsburg teaches, e.g., an instruction cache 101 for storing instructions to be executed by the microprocessor 100. See, e.g., col. 5:36-39, 48-52. b)program counter means directly coupled to said instruction memory means for indexing said instructions; Augsburg teaches, e.g., an instruction address register (IAR) 110,'commonly known as the program counter," for indexing the instructions. See, e.g., col. 5:62-65; col. 6:12-15. Nakamoto teaches, e.g., a program counter(PC) 1 that is directly coupled to, e.g., a program memory 2. See Fig. 2; See, e.g., col. 2:21-23. The IBM Manual for the PPC403GA teaches, e.g., a machine state register(MSR)and/or an external interrupt status register(EXISR)for indicating information regarding interrupts and exceptions. See, e.g., chapter 6, pages 6-1 to 6-4, 6-9 to 6-11. Reasons for Combining Augsburg and the IBM Manual with Nakamoto A person of ordinary skill in the art at a time before the invention of the '331 patent would have combined Augsburg and IBM Manual with Nakamoto because: (i) each of Augsburg and Nakamoto are directed to the same problem: tracing program or debug program code at real time (See, Augsburg Abs., Nakamoto Abs. and col. 1. 8-12); (ii) Augsburg teaches an integrated circuit 10, shown in Figure 1, which includes logic for performing the tracing of program code. See, e.g., id. at col. 5, lines 34-38. The integrated circuit 10 includes a microprocessor 100, which Augsburg teaches "may comprise ..., e.g., the PowerPC microprocessor, model no. PPC403GA, available from IBM Corporation." Id. at coil 5, lines 42- 45. BC_GEN_0002152 5 Application/Control Number: 90/011,532 Page 11 Art Unit: 3992 (iii) IBM specifically discloses content of general purpose register can be written to the MSR via the move to the machine states register instruction, Id., p. 6-2; and (iv)IBM specifically discloses when an interrupt occurs the bit corresponding to the interrupt is set in the EXISR. Id., p. (v) Nakamoto specifically discloses a program counter that is directly coupled to a program memory,Id., col. 2:21-23. Further, a person of ordinary skill in the art would have been motivated to combine Augsburg and the IBM Manual with Nakamoto because combining the prior art elements of Augsburg and the IBM Manual with Nakamoto according to known methods would have yielded predictable results (e.g., combining the elements as claimed by known methods with no change in their respective functions, and applying the techniques of the IBM Manual and Nakamoto to improve Augsburg would have yielded predictable results (e.g., content of the register is recorded when an exception occurs and for knowing the change of the status of an interrupt and indexing instruction according to the program counter), and applying the techniques of IBM Manual to improve Augsburg would have yielded predictable results (e.g., for comparing with the program code for the purpose of debugging).[See MPEP § 2143] because combining the prior art elements of IBM Manual with Augsburg according to known methods would have yielded predictable results (e.g., recording history of the even for the purpose of program analysis during runtime).[See MPEP § 2143] Additionally a person of ordinary skill in the art would have been motivated to combine Augsburg with that of IBM Manual because, Augsburg explicitly suggest the use of the PP403GA as the microprocessor 100,See, e.g., Augsburg, col. 5, lines 42-45. d)first decoder means for indicating information about an instruction executed by said processor during a clock cycle, Augsburg teaches, e.g., control logic 103 that encodes status information received from the microprocessor 100 that may include the execution of an instruction, the direction of any executed branches, and the taking of any exception vectors. See, e.g., col. 7:36-40. The information is provided during a clock cycle. See e.g., col. 7:18, 47-49. BC_GEN_0002153 5 Application/Control Number: 90/011,532 Page 12 Art Unit: 3992 said first decoder means being directly coupled to said instruction memory means, said program counter means, and said cause register means, Nakamoto teaches, e.g., an instruction decoder and timing controller 3 that is directly coupled to the program memory 2, the PC 1, and, e.g., the latch register 6("cause register 6" in box 302 of Fig. 3). See Fig. 2. See above for the reasons to combine the prior art of Augsburg and the IBM manual with Nakamoto. said first decoder means having a first output, Augsburg teaches that the control logic 103 has, e.g., a three bit output [0:2] on pins 118 via bus 105 and driver 107. See, e.g., col. 7:42-46; Fig. 1. wherein said first output provides information regarding activity of said processor in real time. Augsburg teaches that the three bit output on pins 118 provides the encoded status information in real time. See, e.g. col. 3:6-10: col. 7:45-46. RE: claim 2 2.A processor according to claim 1, See claim 1 above. said information regarding processor activity includes information as to at least one of a jump instruction has been executed, a jump instruction based on the contents of a register has been executed, a branch has been taken, and an exception has been encountered. Augsburg teaches that the encoded status information received on the microprocessor 100 may include the direction of any executed branches and the taking of any exception vectors. See, e.g., col. 7:36-40. RE: claim 3 3. A processor according to claim 1, wherein: BC_GEN_0002154 5 Application/Control Number: 90/011,532 Page 13 Art Unit: 3992 See claim 1 above. said clock cycle is a processor clock cycle, and Augsburg teaches that the clock cycle is a processor clock cycle. See, e.g., col. 4:56-58; col. 10:5-6. said first decoder means updates said information about each instruction executed by said processor for each said processor clock cycle. Augsburg teaches that the control logic 103 outputs the encoded status information about each instruction executed by the microprocessor 100 for each processor clock cycle. See, e.g., col. 7:9-61; col. 4:27-29, 56-58. RE: claim 4 4. A processor according to claim 3, wherein: See claim 3 above. said information about each instruction executed by said processor includes an indication whether or not an instruction has been executed since the previous processor cycle. Augsburg teaches that the encoded status information about each instruction executed by the microprocessor 100 includes an indication whether or not an instruction has been executed since the previous processor cycle. See, e.g., col. 7:18-34. RE: claim 5 5. A processor according to claim 1, wherein: See claim 1 above. said first output consists of a three bit parallel output. Augsburg teaches that the control logic 103 has, e.g., a three bit output [0:2] on pins 118 via bus 105 and driver 107. See, e.g., col. 7:42-46; Fig. 1. RE: claim 11 BC_GEN_0002155 5 Application/Control Number: 90/011,532 Page 14 Art Unit: 3992 11. An embedded system having a plurality of processors and a real time debugging i nterface, said system comprising: Augsburg teaches an embedded system that has a plurality of processors. See, e.g., col. 1 2:17-19. Augsburg teaches, e.g., a microprocessor 100, which may be a PowerPC microprocessor model no. PPC403GA, having a real time, non-invasive instruction trace i nterface. See, e.g., col. 3:6-9; col. 5: 41-45. a)a plurality of instruction memory means for storing instructions to be executed by a respective one of said plurality of 9rocessors; Augsburg teaches, e.g., an instruction cache 101 for storing instructions to be executed by the microprocessor 100. See, e.g., col. 5:36-39, 48-52. b)a plurality of program counter means,each directly coupled to a respective one of said plurality of instruction memory means for indexing contents of said instruction memory means; Augsburg teaches, e.g., an instruction address register(IAR) 110, "commonly known as the program counter," for indexing the instructions. See, e.g., col. 5:62-65; col. 6:12-15. Nakamoto teaches, e.g., a program counter(PC) 1 that is directly coupled to, e.g., a program memory 2. See Fig. 2; See, e.g., col. 2:21-23. For the reasons to combine the prior art of Augsburg and the IBM manual with Nakamoto, see the rejection of claim 1 above. c)a plurality of cause register means for indicating information regarding interrupts and exceptions for a corresponding one of said plurality of processors, The IBM Manual for the PPC403GA teaches, e.g., a machine state register(MSR)and/or an external interrupt status register(EXISR)in the microprocessor for indicating information regarding interrupts and exceptions for the microprocessor. See, e.g., chapter 6, pages 6-1 to 6-4. 6-9 to 6-11. See the rejection of claim 21 above for the reasons to combine the prior art of Augsburg with the IBM manual. BC_GEN_0002156 5 Application/Control Number: 90/011,532 Page 15 Art Unit: 3992 each of said cause register means being directly coupled to a respective one of said processors; and The MSR and/or EXISR are directly coupled to the microprocessor by way of being on the microprocessor, like the cause register 26a is on the processor 12a in the '331 patent. See '331 patent, Figs. 1A and IB. d)a plurality of first decoder means, Augsburg teaches, e.g., control logic 103. See, e.g., col. 7:36-40. each said first decoder means directly coupled to a respective one of said instruction memory means, to a respective one of said program counter means, and a respective one of said cause register means, Nakamoto teaches, e.g., an instruction decoder and timing controller 3 that is directly Coupled to the program memory 2, the PC 1 and, e.g., the latch register 6(".cause register 6" in box 302 of Fig. 3). See Fig. 2. See the rejection of claim 1 above for the reasons to combine the prior art of Augsburg and the IBM manual with Nakamoto. each said first decoder means for indicating information about an instruction executed during a clock cycle by a respective one of said processors, Augsburg teaches that the control logic 103 encodes status information received from the microprocessor 100 that may include the execution of an instruction, the direction of any executed branches, and the taking of any exception vectors. See, e.g., col. 7:36-40. The information is provided during a clock cycle. See, e.g., col. 7:18, 47-49. each said first decoder means having a first output, Augsburg teaches that the control logic has, e.g., a three bit output [0:2] on pins 118 via bus 105 and driver 107. See, e.g., col. 7:42-46; Fig. 1. BC_GEN_0002157 5 Application/Control Number: 90/011,532 Page 16 Art Unit: 3992 wherein each said first output provides information regarding activity of said processor in real time. Augsburg teaches that the three bit output on pins 118 provides the encoded status information in real time. See, e.g., col. 3:6-10; col. 7:45-46. RE: claim 12 12. An embedded system according to claim 11, wherein: See claim 11 above. Si said information regarding processor activity includes information as to at least one of a jump instruction has been executed, a jump instruction based on the contents of a register has been executed, a branch has been taken, and an exception has been encountered. Augsburg teaches that the encoded status information received from the microprocessor 100 may include the direction of any executed branches and the taking of any exception vectors. See, e.g., col. 7:36-40. RE: claim 13 13. An embedded system according to claim 11, wherein: See claim 11 above. said clock cycle is a processor clock cycle, and Augsburg teaches that the clock cycle is a processor clock cycle. See, e.g., col. 4:56-58; col. 10:5-6. each said first decoder means updates said information about each instruction executed by a respective processor for each said processor clock cycle of said respective processor. Augsburg teaches that the control logic 103 continuously outputs the encoded status information about each instruction executed by the microprocessor 100 for each processor clock cycle. See, e.g., col. 7:9-61; col. 4:27-29, 56-58. BC_GEN_0002158 5 Application/Control Number: 90/011,532 Page 17 Art Unit: 3992 RE: claim 14 14. An embedded system according to claim 13, wherein: See claim 13 above. each said information about each instruction executed by a respective processor includes an indication whether or not an instruction has been executed since the previous processor cycle of said respective processor. Augsburg teaches that the encoded status information about each instruction executed by the microprocessor 100 includes an indication .whether or not an instruction has been executed since the previous processor cycle. See, e.g., col. 7:18-34. RE: claim 15 15. An embedded system according to claim 11, wherein: See claim 11 above. each of said first outputs consists of a three bit parallel output. Augsburg teaches that the control logic 103 has, e.g., a three bit output [0:2] on pins 118 via bus 105 and driver 107. See, e.g., col. 7:42-46; Fig. 1. RE: claim 19 19. An embedded system according to claim 11, wherein: See claim 11 above. said system is embodied on a chip having a plurality of pins, Augsburg teaches that the processor 100 "comprised of a number of processing engines in a multiprocessor or parallel processing architecture" is in an integrated circuit 10 on a single silicon chip. See, e.g., col. 5:34-41; col. 12:17 - 19. The integrated circuit 10 has pins 118 and pins 119. See, e.g., Fig. 1; col. 7:10-11, 62-64. said first and second outputs are provided via some of said plurality of pins. BC_GEN_0002159 5 Application/Control Number: 90/011,532 Page 18 Art Unit: 3992 Augsburg teaches that the "first" output is provided via pins 118. See, e.g., col. 7:45-46. Augsburg teaches that a "second" output is provided via pins 119. See, e.g., col. 7:62-8:4. RE: claim 20 20. An embedded system according to claim 19, wherein: See claim 19 above. each of said first outputs is an n-hit parallel output, and Augsburg teaches the three bit output [0:2] on three pins 118. See, e.g., col. 7:9-11, 42- 46; Fig. 1. The three bit information output on the three pins 118 is a parallel output. said second output is a serial output. Augsburg teaches that the output over pins 119 is a serial output. See, e.g., col. 7:62-8:4. III. CONCLUSION AMENDMENT IN REEXMAINATION PROCEEDING The Patent Owner is notified that any proposed amendment to the specification and/or claims in this reexamination proceeding must comply with 37 CFR 1.530(d)-(j), must be formally presented pursuant to 37 CFR 1.52(a) and (b), and must contain any fees required by 37 CFR 1.20(c). In order to ensure full consideration of any amendments, affidavits or declarations, or other documents as evidence of patentability, such documents must be submitted in response to this Office action. Submissions after the next Office action, which is intended to be a final action, will be governed by the requirements of 37 CFR 1.116, after final rejection and 37 CFR 41.33 after appeal, which will be strictly enforced. See MPEP § 2250(IV)for examples to assist in the preparation of proper proposed amendments in reexamination proceedings. SERVICE OF PAPERS BC_GEN_0002160 5 Application/Control Number: 90/011,532 Page 19 Art Unit: 3992 After filing of a request for ex parte reexamination by a third party requester, any document filed by either the patent owner or the third party requester must be served on the other party (or parties where two or more third party requester proceedings are merged) in the reexamination proceeding in the manner provided in 37 CFR 1.248. The document must reflect service or the document may be refused consideration by the Office. See 37 CFR 1.550(f). EXTENSION OF TIME Extensions of time under 37 CFR 1.136(a) will not be permitted in these proceedings because the provisions of 37 CFR 1.136 apply only to "an applicant" and not to parties in a reexamination proceeding. Additionally, 35 U.S.C. 305 requires that ex parte reexamination proceedings "will be conducted with special dispatch"(37 CFR 1.550(a)). Extensions of time in ex parte reexamination proceedings are provided for in 37 CFR 1.550(c). LITIGATION REMINDER The patent owner is reminded of the continuing responsibility under 37 CFR 1.565(a) to apprise the Office of any litigation activity, or other prior or concurrent proceeding, involving Patent No. 6,321,331thr0ughout the course of this reexamination proceeding. The third party requester is also reminded of the ability to similarly apprise the Office of any such activity or proceeding throughout the course of this reexamination proceeding. See MPEP §§ 2207, 2282 and 2286. BC_GEN_0002161 5 Application/Control Number: 90/011,532 Page 20 Art Unit: 3992 Contact Information All correspondence relating to this ex parte reexamination proceeding should be directed: By Mail: Mail Stop "Ex Porte Reexam" Central Reexamination Unit Commissioner for Patents P. 0. Box 1450 Alexandria, VA 22313-1450 By FAX:(571)273-9900 Central Reexamination Unit By hand: Customer Service Window Randolph Building 401 Dulany Street Alexandria, VA 22314 Registered users of EFS-Web may alternatively submit such correspondence via the electronic filing system EFS-Web, at https://sportal.uspto.gov/authenticate/authenticateuserlocalepf.html. EFS-Web offers the benefit of quick submission to the particular area of the Office that needs to act on the correspondence. Also, EFS-Web submissions are "soft scanned" (i.e., electronically uploaded) directly into the official file for the reexamination proceeding, which offers parties the opportunity to review the content of their submissions after the "soft scanning" process is complete. Any inquiry concerning this communication or earlier communications from the Reexamination Legal Advisor or Examiner, or as to the status of this proceeding, should be directed to the Central Reexamination Unit at telephone number(571)272-7705. Signed: Ma id Banankhah, Primary Examiner Central Reexamination Unit 3992 (571)272-3770 Conferees: Ovidio Escalante, Primary Examiner Eric Keasel, SPE GAU 3992 GAU 3992 BC_GEN_0002162 5 Application/Control No. Applicant(s)/Patent Under Reexamination 90/011,532 6,321,331 Notice of References Cited Examiner Art Unit Page 1 of 1 MAJID A. BANANKHAH 3992 U.S. PATENT DOCUMENTS * Document Number Date - Country Code-Number-Kind Code MM-YYYY Name Classification * A US-5,594,905 01-1997 Mita!, Amit 710/260 * B US-5,742,780 04-1998 .Caulk, Jr., Robert L. 712/206 c US- D US- E US- F US- G US- N US- I US- . J US- K US- L US- IA US- FOREIGN PATENT DOCUMENTS Document Number Date * Country Code-Number-Kind Code MM-yyyy Country Name Classification N 0 P Q R S T NON-PATENT DOCUMENTS * Include as applicable: Author, Title Date, Publisher, Edition or Volume, Pertinent Pages) U V W X *A copy of th's reference is not being furnished with this Office action.(See MPEP § 707.05(a)) Dates in MM YYYY format are publication dates. Classifications may be US or foreign. U.S. Patent and Trademark Office PTO-892(Rev. 01-2001) Notice of References Cited Part of Paper No. 20110726 BC_GEN_0002163 5 Application/Control No. Applicant(s)/Patent under Search Notes Reexamination 1 1 I 1 I I 1 1 11 I 90/011,532 Examiner MAJID A. BANANKHAH 6,321,331 Art Unit 3992 SEARCH NOTES SEARCHED (INCLUDING SEARCH STRATEGY) Class Subclass Date Examiner DATE EXMR Reviewed file history 7/24/2011 MB INTERFERENCE SEARCHED Class Subclass Date Examiner, U.S. Patent and Trademark Office Part of Paper No. 20110726 BC_GEN_0002164 5 Reexamination Application/Control No. Applicant(s)/Patent Under Reexamination 90/011,532 6,321,331 Certificate Date Certificate Number 1111 11 III II 11111 1 1 11 Requester Correspondence Address: El Patent Owner Third Party Adam C. Davenport Slater & Matsil, L.L.P. 1 7950 Preston Rd. Suite 1000 Dallas, TX 75252 LITIGATION REVIEW fr /MB/ (examiner initials) (date) Case Name Director Initials U.S. District - California Northern (Oakland), 4:1 Icv671 Xilinx, Inc v. Invention Investment Fund I LP et al / a5'' U.S. District - California Northern (San Jose), 5:1 Icv671 1 Xilinx, Inc v. Invention Investment Fund I LP et al COPENDING OFFICE PROCEEDINGS TYPE OF PROCEEDING NUMBER 1. 2. 3. 4. U.S. Patent and Trademark Office DOC, CODE RXFILJKT BC_GEN_0002165 Page 1 of 1 5 UNITED STATES PATENT AND TRADEMARIL OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark °Mee Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Yuginis 22313-1450 anmuspto.gov FIF I 1111 IIIID III CONFIRMATION NO. 3636 Bib Data Sheet FILING OR 371(c) DATE ATTORNEY SERIAL NUMBER CLASS GROUP ART UNIT DOCKET NO. 90/011,532 03/C4/2011 712 3992 6321331RX RULE APPLICANTS 6,321,331:Residence Not Provided; TR TECHNOLOGIES FOUNDATION LLC(OWNER), WILMINGTON, DE; SLATER & MATSIL, L.L.P.(3RD.PTY.REQ.), DALLAS, TX; SLATER & MATSIL, L.L.P., DALLAS, TX ** CONTINUING DATA ************************* This application is a REX of 09/064,474 04/22/1998 PAT 6,321,331 "* FOREIGN APPLICATIONS Foreign Priority claimed yes LI no TOTAL INDEPENDENT 35 USC 119(a-d) conditions Li yes no Li LI Met after STATE OR SHEETS CLAIMS CLAIMS met Allowance COUNTRY DRAWING 22 4 Verified and Acknowledged Examiners Signature Initials ADDRESS 25943 TITLE Real Time Debugger Interface for Embedded Systems LI All Fees LJ 1.16 Fees(Filing) FILING FEE FEES: Authority has been given in Paper rj1.17 Fees(Processing Ext. of RECEIVED No. to charge/credit DEPOSIT ACCOUNT time) 2520 No. for following: t 1.18 Fees(Issue) j LI Other 1 Credit:1 BC_GEN_0002037 5 Application/Control No. Applicant(s)/Patent under Application Number Reexamination 1 I I 1I I 1 1 90/011,532 Examiner 6,321,331 Art Unit 3992 U.S. Patent and Trademark Office Part of Paper No. 20110310 BC_GEN_0002038 5 MICHAEL D.SPECHT DIRECTOR (202) 772-8756 NISPECHT@SKGF.COM September 27, 2011 Mail Stop "Ex Parte Reexam" Attn: Central Reexamination Unit Commissioner for Patents P.O. Box 1450 Alexandria, VA 22313-1450 Re: Reexamination of U.S. Patent No. 6,321,331 Control No. 90/011,532; Filed: March 4, 2011 For: Real Time Debugger Interface for Embedded Systems Inventors: ROY et al. Our Ref: 3059.014REXO Sir: Transmitted herewith for appropriate action are the following documents: 1. Online Credit Card Payment Authorization in the amount of $2,410.00 to cover: $2,160.00 Reexamination claims in excess of 20 and also in excess of the number of claims in the patent under reexamination; $250.00 Reexamination independent claims in excess of three and also in excess of the number of such claims in the patent under reexamination; 2. Patent Owner's Response to Office Action of July 29, 2011; 3. Exhibit 1: Power Point slides presented in Examiner Interview conducted September 7, 2011 4. Declaration of Michael Barr Under 37 C.F.R. § 1.132; 5. Exhibits to the Declaration of Michael Barr: A. List ofExhibits; B. Curriculum Vitae ofMichael Barr; C. US. Patent No. 6,321,331 to Roy; D. US. Patent No. 5,996,092 to Augsburg et al; E. IBM PowerPC 403GA User's Manual, Second Edition, March 1995; F. US. Patent No. 5,361,348 to Nakamoto; G. Non-Final Office Action in US. Application No. 09/064,474 mailed June 10, 1999; H Amendment and Reply to Office Action filed September 8, 1999 in U.S. Application No. 09/064,474; BC_GEN_0002206 5 Commissioner for Patents September 27, 2011 Page 2 I Non-Final Office Action in US. Application No. 09/064,474 mailed November 24, 1999; J Interview Sununary of interview held February 25, 2000 in US, Application No. 09/064,474; K, Supplemental Amendmentfiled March 10, 2000 in US. Application No. 09/064,474; Final Office Action mailed June 6, 2000 in US Application AV 09/064,474; M Advisory Action mailed August 11, 2000 in US. Application No. 09/064,474: N Reply to Final Office Action and Advisory Action,filed August 15, 2000 in US. Application No. 09/064,474; 0. Advisory Action mailed August 29, 2000 in US, zipplication No 09/V64.474,- P. Request Under 37 C.F.R. § 1.53 filed September 6, 2000 in US Application No, 09/064,474; O Final Office Action mailed November 20, 2000 in US. Application No. 09/064.474; R. Final Office Action mailed April 16, 2001 in US. Application No. 09/064,474; S. Notice ofAllowance mailed August 2, 2001 in US. Application No. 09,1064,474; • Office Action in Ex Porte Reexamination mailed July 29, 2011 in Reexamination Control No. 90/011,532.. 6. Information Disclosure Statement by Patent Owner, 7. Form PTO/SB/08a(2 sheets) listing 26 documents(US1-US26); 8, Form PTO/SI3/08b (1 sheet) listing 5 documents(NPU-NPL5); 9. Copies of cited documents (NPI1-NPL.5); and 10. Certificate of Service. The above-listed documents are filed electronically through EFS-V,7eb. Fee payment is provided through online credit card payment. The U.S. Patent and Trademark Office is hereby authorized to charge any fee deficiency, or credit any overpayment, to our Deposit Account No. 19-0036. Respectfully submitted, STEP:1\TE., KESSLER, GOLDSTEIN & Fox P,L.L,C e" ';' k) \, Michael D. Specht Attorney for Patent Owner Registration No, 54,463 M DS/MC/fIlS .EreCIOSLifeti 1422968_1DOCX M BC_GEN_0002207 5 IN THE UNITED STATES PATENT AND TRADEMARK OFFICE In re U.S. Patent No. 6,321,331 to Confirmation No,: 3636 ROY et al. Art Unit: 3992 Reexam Control No.: 90/011,532 Examiner: Woo H. Choi Filed: March 4, 2011 Atty. Dkt. No.: 3059.014REXO For: Real Time Debugger Interface for Embedded Systems 3 Patent Owners Response to Office Action of July 29, 2011 Mail Stop Ex Pane Reexam Commissioner for Patents P.O. Box 1450 Alexandria, VA 22313-1450 Sir: In reply to the Order Granting Ex Pane Reexamination dated April 8, 2011 and the Office Action dated July 29, 2011, the patent owner TR Technologies Foundation 1,11,C ("Patent Owner")submits the following: Amendments to the Claims, which begin on page 2 ofthis paper; and Remarks, which begin on page 15 of this paper. It is believed that no extensions of time or other fees are required. However, if any fees are necessary to prevent abandonment of this reexamination, then such fees are hereby petitioned and hereby authorized to be charged to our Deposit Account No. 19-0036. BC_GEN_0002208 5 Amendments to the Claims A listing of each claim under reexamination is provided below. The Patent Owner provides this listing of original patent claims 1-22 from the U.S. Patent No. 6,321,331 and a listing of newly presented claims 23-48. 1. (Original Patent Claim) A processor having a real time debugging interface, said processor comprising: a)instruction memory means for storing instructions to be executed by said processor; b) program counter means directly coupled to said instruction memory means for indexing said instructions; c)cause register means for indicating information regarding interrupts and exceptions; and d) first decoder means for indicating infou tation about an instruction executed by said processor during a clock cycle, said first decoder means being directly coupled to said instruction memory means, said program counter means, and said cause register means, said first decoder means having a first output, wherein said first output provides infoimation regarding activity of said processor in real time. 2. (Original Patent Claim) A processor according to claim 1, said information regarding processor activity includes information as to at least one of a jump instruction has been executed, a jump instruction based on the contents of a register has been executed, a branch has been taken, and an exception has been encountered. 2 BC_GEN_0002209 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 3. (Original Patent Claim) A processor according to claim 1, wherein: said clock cycle is a processor clock cycle, and said first decoder means updates said information about each instruction executed by said processor for each said processor clock cycle. 4. (Original Patent Claim) A processor according to claim 3, wherein: said information about each instruction executed by said processor includes an indication whether or not an instruction has been executed since the previous processor cycle. 5. (Original Patent Claim) A processor according to claim 1, wherein: said first output consists of a three bit parallel output. 6. (Original Patent Claim) A processor according to claim 1, further comprising: e)second decoder means directly coupled to said cause register means for indicating information about contents of said cause register means, said second decoder means having a second output; and f)event history buffer means for storing information regarding processor events, said event history buffer means having a data input, a data output, and an enable input, said data input being directly coupled to said cause register means and said enable input being directly coupled to said second output, wherein said second decoder means decodes contents of said cause register means and enables said event history buffer means to capture contents of said cause register means when contents of said cause register means indicate a particular event. 7. (Original Patent Claim) A processor according to claim 6, wherein: said second decoder means enables said event history buffer means when contents of said cause 1418015 1 -3 - Attorney Docket No. 3059.014REXO BC_GEN_0002210 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 register means indicate an event including at least one of a change in status of an interrupt line, an internal processor exception, and a jump instruction based on the contents of a register. 8. (Original Patent Claim) A processor according to claim 6, wherein: said data output of said event history buffer means is a bit serial output. 9. (Original Patent Claim) A processor according to claim 6, wherein: said processor is embodied on a chip having a plurality of pins, said first output and said data output are provided via some of said plurality of pins. 10. (Original Patent Claim) A processor according to claim 9, wherein: said first output is an n-bit parallel output, and said data output is a serial output. 1 1. (Original Patent Claim) An embedded system having a plurality of processors and a real time debugging interface, said system comprising: a)a plurality of instruction memory means for storing instructions to be executed by a respective one of said plurality of processors; b)a plurality of program counter means, each directly coupled to a respective one of said plurality of instruction memory means for indexing contents of said instruction memory means; c) a plurality of cause register means for indicating information regarding interrupts and exceptions for a corresponding one of said plurality of processors, each of said cause register means being directly coupled to a respective one of said processors; and 1 418015_1 -4- Attorney Docket No. 3059.014REX0 BC_GEN_0002211 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 d)a plurality of first decoder means, each said first decoder means directly coupled to a respective one of said instruction memory means, to a respective one of said program counter means, and a respective one of said cause register means, each said first decoder means for indicating infolination about an instruction executed during a clock cycle by a respective one of said processors, each said first decoder means having a first output, wherein each said first output provides infoi[nation regarding activity of said processor in real time. 12. (Original Patent Claim) An embedded system according to claim 11, wherein: said infoiiriation regarding processor activity includes infoiniation as to at least one of a jump instruction has been executed, a jump instruction based on the contents of a register has been executed, a branch has been taken, and an exception has been encountered. 13. (Original Patent Claim) An embedded system according to claim 11, wherein: said clock cycle is a processor clock cycle, and each said first decoder means updates said information about each instruction executed by a respective processor for each said processor clock cycle of said respective processor. 14. (Original Patent Claim) An embedded system according to claim 13, wherein: each said infoi'nation about each instruction execuled by a respective processor includes an indication whether or not an instruction has been executed since the previous processor cycle of said respective processor. 15. (Original Patent Claim) An embedded system according to claim 11, wherein: each of said first outputs consists of a three bit parallel output. 1418015 1 -5- Attorney Docket No. 3059.014REXO BC_GEN_0002212 5 Patent Owner's Response to ROY et at. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 16. (Original Patent Claim) An embedded system according to claim 11, further comprising: e)a plurality of second decoder means, each directly coupled to a respective one of said plurality of cause register means, each said second decoder means for indicating information about contents of a respective cause register means; and f)an event history buffer means for storing information regarding processor events, said history buffer means having a data input, a data output, and an enable input, said data input being directly coupled to each of said plurality of cause register means and said enable input being directly coupled to each of said second outputs, wherein each of said second decoder means decodes contents of a respective cause register means and enables said event history buffer to capture contents of said respective cause register means when contents of said respective cause register means indicate a particular event. 17. (Original Patent Claim) An embedded system according to claim 16, wherein: each said second decoder means enables said event history buffer means when contents of a respective cause register means indicate an event including at least one of a change in status of an interrupt line, an internal processor exception, and a jump instruction based on the contents of a register. 18. (Original Patent Claim) An embedded system according to claim 16, wherein: said data output of said event history buffer means is a bit serial output. 1 418015i 6 Attorney Docket No. 3059.014REX0 BC_GEN_0002213 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 19. (Currently Amended) An embedded system according to claim [11] 16 wherein: said system is embodied on a chip having a plurality of pins, said first and second outputs are provided via some of said plurality of pins. 20. (Original Patent Claim) An embedded system according to claim 19, wherein: each of said first outputs is an n-bit parallel output, and said second output is a serial output. 21. (Currently Amended) A processor having a real time debugging interface, said processor comprising: a)instruction memory means for storing instructions to be executed by said processor; b)program counter means coupled to said instruction memory means for indexing said instructions; c)cause register means for indicating cause information regarding interrupts and exceptions; and d)first decoder means for indicating infolination about an instruction executed by said processor during a clock cycle, said first decoder means being coupled to said instruction memory means, said program counter means, and said cause register means, said first decoder means having a first output, wherein said first output provides infoimation regarding activity of said processor in real time, said clock cycle is a processor clock cycle, said first decoder means updates said infottnation about each instruction executed by said processor for each said processor clock cycle, and said information about each instruction executed by said processor includes an indication whether or not an instruction has been executed since the previous processor cycle. 1 418015 1 - 7- Attorney Docket No. 3059,014REX0 BC_GEN_0002214 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 22. (Currently Amended) An embedded system having a plurality of processors and a real time debugging interface, said system comprising: a)a plurality of instruction memory means for storing instructions to be executed by a respective one of said plurality of processors; b)a plurality of program counter means, each coupled to a respective one of said plurality of instruction memory means for indexing contents of said instruction memory means; c) a plurality of cause register means for indicating cause information regarding interrupts and exceptions for a corresponding one of said plurality of processors, each of said cause register means being coupled to a respective one of said processors; and d)a plurality of first decoder means, each said first decoder means coupled to a respective one of said instruction memory means, to a respective one of said program counter means, and a respective one of said cause register means, each said first decoder means for indicating information about an instruction executed during a clock cycle by a respective one of said processors, each said first decoder means having a first output, wherein each said first output provides information regarding activity of said processor in real time, said clock cycle is a processor clock cycle, each said first decoder means updates said information about each instruction executed by a respective processor for each said processor clock cycle of said respective processor, and each said information about each instruction executed by a respective processor includes an indication whether or not an instruction has been executed since the previous processor cycle of said respective processor. 1418015_1 -8- Attorney Docket No. 3059.014REXO BC_GEN_0002215 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 23. (New) A processor according to claim 1, wherein said information comilrises cause infoimation. 24. (New) A orocessor accordin to claim 1, wherein said information comprises processor related exception conditions and an indication of pending interrupts. 25. (New) processor accordimt: _, wherein -said indication of pending interrupts includes at least one of an indication of external, software,_ or co-processor interrupt. 26. (New) A processor_ accordim to claim 1, further compris,ing; e)event history buffer means for storinL!, information regarding_processor events, said event history buffer means having a data input, a data output, and an enable input said data input being directly coupled to said cause register means. 27. (New) A wocessor according to claim 26, wherein said event history buffer means comarises a tIlurality of buffers. 28. (New) A processor according to claim 26, wherein said event history buffer means is configured to capture contents of said cause re_Oster means when enabled by said enable input. 29. (New) A processor according_ to claim 28, wherein said event history' buffer is contiuured to be enabled when the contents of said cause register means indicates a particular event. 1 418015 1 - 9- Attorney Docket No. 3059.014REXO BC_GEN_0002216 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 30. (New) A processor according to claim 29, wherein said particular event is at least one of a change in status of an interrupt line, an internal processor exception, or a jump instruction based on the contents of a ster. 31. (New) A processor according to claim 1. wherein said cause re2ister means comprises a plurality of registers. 32. (New) A_processor accordine, to claim 1, wherein said debugging,interface is confintestio info Illation indicated by said cause ref,4ister means with actual program code being executed by said processor. 33. (New) An embedded system according to claim 11, wherein said infounation comprises_cgifse_inform__atiori, 34. (New) An embedded system accordint., to claim 11 wherein said infon iation comprises_processor related exception conditions and an indication of pending interrupts. 35. (New) An embedded_systern,,,,,,,,,,,,„claim 34, wherein said indication of pending interrupts includes at least one of an indication of external, software, of co-processor interrupts. 36. (New)An_ embedded system according_ to claim 11,further comprising; 1418015_ 1 - 10 - Attorney Docket No. 3059.014REXO BC_GEN_0002217 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 C)an event history buffer means foi storino,information regarding prg_cessor events, said histo17, buffer means having a data input, a data output, and an enable input, said data input being directls, coupled to each of said plurality of cause register means. 37. (New) An embedded system according to claim 36„ wherein said event history buffer means corn:Prises a plurality of buffers. 38. (New) An embedded system accordina to claim 36, wherein said event history buffer means is configured to c tt ntents of said plurality of cause register means when enabled by said enable input. 39. (New) An embedded system according to claim 38,wherein said event history buffer is configured to be enabled when the contents of said pluralitv of cause reaister means indicates a particular event. 40. (New) An embedded system accordirn.f to claim 29. wherein said particular even is at least one of a chamze in status of an interrupt line, an internal processor exception, or a iump,Instruction based on the contents of a register. 41. (New) An embedded system,peco ng„,„rto,, J.aIm 11, wherein said cause ref.ister means comprises a plurality of registers. 42. (New) An embedded system accordirm to claim 11, wherein said debugaisfe interface is conflored to facilitate the correlation of said output of said first decoder means 1418015,1 - 11 Attorney Docket No. 3059.014REXO BC_GEN_0002218 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 and the infoimation indicated by said cause register means with actual program code beirw, executed by said processor. 43. (New) A.j)rocessor_aecordina to claim,,,,,,,,,whercip_sid cause inforniation comprises processor related exception conditions and an indication of Rend:ingintemipts„ 44. (New) A,processor accordino to claim 43, wherein said indication of pending interrupts includes at least one of an indication of external software, or co-)rocessor interrupt. 45. (New)A processor accordim.! to claim 21, further comprisintl: e)event history buffer means for storing,inforwation regarding _processor events. said event history buffer means havin2. a data input, a data output, and an enable inept, said data input bemm. directly coupled to said cause resister means. 46. (New) A processor accordirw, to claim 45,wherein said event histaQ buffer means is configured to capture contents of said cause register means when enabled b-k said enable input. 47. (New) A W.Pg.essor.accordinaio claim 46. wherein said event history buffer is configured to be enabled when the contents of said cause re,Oster means inchente,s,,a particular event. 1418015_1 - 12 Attorney Docket No. 3059.014REX0 BC_GEN_0002219 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 48. (New) A.,processor accor ino, to claim 47, wherein said articui venijat is. least one of a change in status of an interrupt line, an internal processor exception, or a,jump instruction based on the contents of a retdster. 49. (New) A processor according_toslajtra...................... cause register means comprises a plurality of reolsters. 50. (New) An embedded system according to claim 22, wherein said cause infounation comprises„processor related exception conditions and an indication of pending interrupts. 51. (New) An embedded sk stem according to claim 50, whetein said indication of penditu! interrupts includes at least one of an indication of external, software, or co-processor interrupt. 52. (New) An embedded system accordin:);. to claim 22,, further comprising: e)an event history buffer means for stor:no- information regardinu proces_soi_eyents, said history buffer means havin a data input, a data cjatlzut„and an enable input said data input being,directiv coupled to each of said plurality of cause rezister means. 53. (New) An embedded system according to claim 52, wherein said event history buffer means is con muffed to capture contents of said plurality of cause register means when enabled_by sajd_.enablejun(. 1418015_1 - 13 - Attorney Docket No. 3059.014REXO BC_GEN_0002220 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 54. (New) An embedded system according to claim 53„ wherein said event history buffer is configured to be enabled when the contents of said pluiality of cause register means indicates a particular event. 55. (New) An embedded system according to claim 54, wherein said particular event is at least one of a change in status of an interrupt line, an internal 1.)rocessor exception, or a jump instruction based on the contents of a register. 56. (New) An embedded s.,„stern according to claim 22, wherein said cause register means comprises a plurality of registers. 1418015_1 - 14 - Attorney Docket No. 3059.014REXO BC_GEN_0002221 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 Remarks Issued patent claims 1-5, 11-15, and 19-22 of U.S. Patent No. 6,321,331 to Roy et al. ("Roy" or "the '331 patent") are currently subject to the present ex parte reexamination proceeding. Claims 1, 11, 21, and 22 are independent claims. In accordance with 35 U.S.C. § 305, Patent Owner is presenting new claims 23-56. Pursuant to 37 C.F.R. 1.530(e),, the status of all claim- and an explanation of the support in the disclosure of the '331 patent for newly presented claims 23-56 is provided in Section I. Newly presented claims 23-56 do not enlarge the scope of the claims of the '331 patent. Based on the following remarks, and the Declaration of Michael Barr under 37 C.F.R. § 1.132 submitted herewith ("Barr Decl."), Patent Owner respectfully requests that the Examiner reconsider and withdraw all outstanding rejections and enter, examine, and allow newly presented claims 23-56. Section 1 provides the status of all claims. Section I also presents the added claims and provides an explanation of the support in the disclosure of the '331 patent for newly presented claims 23-56. Section II provides a summary of arguments that support the allowance of all claims subject to this reexamination. Section LH discusses the 'legal standards relevant to the issues in this reexamination. Section IV describes the differences between the applied references and the original patent claims. Section V addresses patentability of newly presented claims 23-56 over the applied references. I. STATUS OF CLAIMS Original issued patent claims 1-5, 11-15, and 19-22 stand rejected. Claims 6-10 and 16-18 are not subject to reexamination. Claims 21 and 22 have been amended to clarify their meaning. Claim 19 has been amended to change its dependency to clam 16. No other amendments have been made to original patent claims 1-22. 1418015_1 - 15 - Attorney Docket No. 3059.014REXO BC_GEN_0002222 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 In accordance with 35 U.S.C. § 305, Patent Owner seeks to add new claims 23-56. Newly presented claims 23-56 have not previously been entered by the Examiner. New claims 23-29 depend from independent claim 1, new claims 30-36 depend from independent claim 11, new claims 37-42 depend from independent claim 21, and new claims 43-48 depend from claim 22. Support for the new claims can be found, inter al/a, in the original claims and in the Specification of the '331 patent at 6:16-38; 6:62 — 7:28; FIGS. lA and 1B. The following table indicates examples of specific support for each of the new claims in the specification of the patent: Claim Example Support Specification at 6:62 - 7:15; FIGS. IA and 23 1B 24 Specification at 7:1-3 25 Specification at 7:1-3 26 Specification at 6:16-26 27 Specification at 6:16-26 28 Specification at 6:39-42 29 Specification at 7:11-13 30 Specification at 6:31-38 31 Specification at 6:16-38 32 Specification at 7:21-28 Specification at 6:62 — 7:15; FIGS. IA and 33 1B 34 Specification at 7:1-3 35 Specification at 7:1-3 36 Specification at 6:16-26 37 Specification at 6:16-26 38 Specification at 6:39-42 39 Specification at 7:11-13 40 Specification at 6:31-38 41 Specification at 6:16-38 42 Specification at 7:21-28 1418015 1 - 16- Attorney Docket No. 3059.014REXO BC_GEN_0002223 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 43 Specification at 7:1-3 44 Specification at 7:1-3 45 Specification at 6:16-26 46 Specification at 6:39-42 47 Specification at 7:11-13 48 Specification at 6:31-38 49 Specification at 6:16-38 50 Specification at 7:1-3 51 Specification at 7:1-3 52 Specification at 6:16-26 53 Specification at 6:39-42 54 Specification at 7:11-13 55 Specification at 6:31-38 56 Specification at 6:16-38 No new matter has been added by any of the claim amendments or new claims. Accordingly, the Patent Owner respectfully requests the entry of the claim amendments and the new claims. II. SUMMARY OF ARGUMENTS The Office Action rejected claims 1-5, 11-15, 19, and 20 under 35 U.S.C. § 103(a) as unpatentable under the combination of U.S. Patent No. 5,996,092 to Augsburg et al. ("Augsburg") in view ofIBM PowerPC 403GA User's Manual, Second Edition, March 1995, [online], [retrieved on 2011-2-9.] Retrieved using interne http://i.want.to.surf.free.friNCD/HTML/403gaum.pdf ("the IBM Manual"), and U.S. Patent No. 5,361,348 to Nakamoto ("Nakamoto"). Additionally, the Office Action rejected claims 21 and 22 under 35 U.S.C. § 103(a) as unpatentable over the combination of Augsburg and the IBM Manual. The Patent Owner respectfully disagrees. 1418015_1 - 17 - Attorney Docket No. 3059.014RFX0 BC_GEN_0002224 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 Claims 21 and 22 With respect to claims 21 and 22, the combination of Augsburg and the IBM Manual fails to disclose or suggest each and every feature of the claimed invention. As amended herein, both claims 21 and 22 recite, among other features, a "cause register means for indicating cause information regarding interrupts and exceptions." The Office Action acknowledges that Augsburg does not teach or disclose the cause register means feature, but alleges that the IBM Manual remedies this deficiency. Specifically, the Office Action relies on the Machine State Register(MSR)and the External Interrupt Status Register (EXISR) to allegedly show the claimed cause register means. However, neither the MSR nor the EXISR teach or disclose a "cause register means for indicating cause information regarding interrupts and exceptions," as recited in claim 21 and similarly in claim 22. The EXISR fails to teach, disclose or suggest this element, because the EXISR only indicates informatiort qkgitt,qxtgniAljiitgpvts, and not about exceptions. The MSR fails to teach, disclose or suggest this element, because it does not indicate cause information regarding interrupts or exceptions. Rather, the MSR acts as a switch to allow a user to enable or disable certain interrupts and exceptions by setting the value of certain bits. Thus, the MSR provides no cause information regarding interrupts or exceptions, but rather simply functionality enabling user settings of exceptions and interrupts. Accordingly, neither the MSR nor the EXISR functions as the claimed cause register means. Thus, the combination of Augsburg and the IBM Manual fails to disclose or suggest each and every claimed feature. The rejection of claims 21 and 22 is, therefore, improper and should be withdrawn. Claims 1-5, 11-15, 19, and 20 With respect to claims 1-5, 11-15, 19, and 20, the combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest each and every claimed feature. For 1418015 1 - 18 - Attorney Docket No. 3059.014REXO BC_GEN_0002225 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 instance, independent claims 1 and 11 recite (a) "a cause register means for indicating infoii iation regarding interrupts and exceptions," (b) "first decoder means being directly coupled to said instruction memory means, said program counter means, and said cause register means," and (c)"program counter means directly coupled to said instruction memory means for indexing instructions." First, the combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest a cause register means for indicating information regarding interrupts and exceptions. As was the case for claims 21 and 22, the Office Action relies on the MSR and EXISR discussed in the IBM Manual to show this claimed feature. However, for reasons similar to those discussed above, the IBM Manual's MSR and EXISR actually fail to perform the function of a cause register means and are., therefore, not analogous. As discussed above, both the MSR and EXISR do not provide information reaardin_v interrupts and exceptions. As discussed above, the MSR acts as a switch to allow a user to enable or disable certain interrupts and exceptions by setting the value of certain bits. Thus, it only provides functionality enabling user settings for interrupts and exceptions. Accordingly, a person of ordinary skill in the art would not understand the IBM Manual to disclose the claimed cause register means. Like Augsburg and the II3M Manual. Nakamoto also fails to disclose or suggest the claimed cause register means. Accordingly, the combination of Augsburg, the IBM Manual, and Nakamoto, lacks this claimed feature. Second, the combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest the claimed decoder means directly coupled to the instruction memory means, program counter means, and cause register means. The Office Action relies on Nakamoto's FIG. 2 to show this claimed feature. Specifically, the Office Action alleges that the claimed feature is taught because Nakamoto shows an instruction decoder and timing controller 3 that is directly coupled to the program memory 2, the PC1, and the latch register 1418015_1 19- Attorney Docket No. 3059.014REX0 BC_GEN_0002226 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 6. As initial matter, even if Nakamoto did show a direct connection between these components, Nakamoto would still fait to show this claimed feature because it does not disclose a first decoder, so it cannot show any features directly coupled to it. The Office Action alleges that the instruction decoder and timing controller 3 is analogous to the claimed first decoder. However, the instruction decoder and timing controller 3 is entirely different from the claimed first decoder. Specificalk t "instruction decoder and timing controller 3" is used during the execution of the current instruction rather than for providing infolination relzarclim activitY of the.processor in real time, as recited by the claims. In addition to failing to show a first decoder, as noted above, Nakamoto fails to show a cause register. Accordingly, even if Nakamoto were to show a first decoder, it would still fail to disclose or suggest directly coupling the first decoder to the cause register means, as recited by the claims. The combination of Augsburg, the IBM Manual, and Nakamoto, therefore, lacks this claimed feature. Third, with regard to the program counter directly coupled to the instruction memory, the Office Action again relies on Nakamoto's FIG. 2 to show this feature. Within the context of Roy, directly coupled means two elements are directly coupled if they are connected to each other with no components in between them. Nakamoto's FIG. 2 does not teach direct coupling. Instead, Nakamoto explains that the prowam counter and the,Ktrogram memoo, shown in FIG. 2 are indirectly coupled through an internal bus. Accordingly, a person of ordinary skill in the art would not understand Nakamoto to disclose or suggest a program counter directly coupled to an instruction memory. Thus, since the combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest each and every claimed feature, the rejection of claims 1-5, 11-15, 19, and 20 is improper and should be withdrawn. 1418015_1 - 20 - Attorney Docket No. 3059.014REXO BC_GEN_0002227 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 REVIEW OF LEGAL STANDARDS GOVERNING THE REJECTIONS Standard ofReview The standard of review for determining patentability is "preponderance of the evidence." (MPEP § 706.1.) The examiner must weigh the evidence presented for and against patentability and if it is more likely than not that the claims are patentable, they must be allowed. (Id.) Patentability is determined Through the lens of one having ordinary skill in the art at the time the application was filed. Phillips v. AWH Corp., 415 F.3d 1303, 1316 (Fed. Cir. 2005)(en bane). Further, the scope of the claims in patent applications is to be determined "not solely on the basis of the claim language, but upon giving claims their broadest reasonable construction 'in light of the specification as it would be interpreted by one of ordinary skill in the art." (Id.)(quoting In re Am. Acad. ofSci. Tech. Ctr., 367 F.3d 1359, 1364(Fed. Cir. 2004)). Claim Construction Despite the fact that patent owners in reexamination do not have the same freedom to amend claims as applicants do during regular prosecution, the Office nonetheless uses the "broadest reasonable interpretation" standard during reexamination. (MPEP § 2258(I)(G); see also In re Trans Texas Holdings, Corp., 498 F.3d 1290, 1292(Fed. Cir. 2007). But use of the broadest reasonable construction standard is not an unfettered license to ignore the specification and the perspective of the skilled artisan. Even under that rubric, the Office must interpret "the scope of claims ... not solely on the basis of the claim language, but upon giving claims their broadest reasonable interpretation 'in livht of the s.•7ecification as it would be interpreted by one of ordinacy skill in the art.' (MPEP § 2111; citing Phillips v. AWH 1418015 1 21 - Attorney Docket No. 3059.014REX0 BC_GEN_0002228 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 Corp., 415 F.3d 1303, 75 USPQ2d 1321 (Fed. Cir. 2005))(emphasis added); see also, In re Am. Acad. ofSci. Tech. Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). Indeed, the Federal Circuit has stated that the "PTO applies to verbiage of the proposed claims the broadest reasonable meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art, taking into account whatever enlightenment by way of definitions or otherwise that may be afforded by the written description contained in applicant's specification." In re Morris, 127 17.3c1 1048, 1054-55 (Fed. Cir. 1997). For instance, in In re Buszard, the Federal Circuit found the PTO's alleged "broadest reasonable interpretation" to be unreasonable where the claims and the specification specifically supported the applicant's construction and were contrary to the Office's construction. In re Buszard, 504 F.3d 1364 1367 (Fed. Cir. 2007). Similarly, in In re Cortright, the Federal Circuit found the PTO's broad interpretation of the term "restoring hair growth" to be unreasonable because it was inconsistent with the disclosure. See In re CortriL;ht, 165 F.3d 1353, 1359 (Fed. Cir. 1999). It is thus well settled that under the "broadest reasonable interpretation" standard, the Office is still required to interpret the claims in a reasonable manner and in light of the specification. The premise for the broadest reasonable interpretation standard is that claims can be readily amended during prosecution of an application. This claim construction standard has been extended to prosecution during reexaminations because patent owners are ostensibly free to amend claims.' However, the freedom of patent owners to amend claims is not practical where the claims under reexamination are involved in simultaneous district court and/or ITC litigation. The reasons are many. First, the doctrine of intervening rights may cut 1 MPEP § 706.1. ("The standard to be applied in all cases is the 'preponderance of the evidence' test. In other words, an examiner should reject a claim if, in view of the prior art and evidence ofrecord, it is more likely than not that the claim is unpatentable."). 1418015 1 - 22 - Attorney Docket No. 3059.014REXO BC_GEN_0002229 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 off past damages where claims are substantively amended. 35 U.S.C. §§ 307(b) and 316(b). Second, the parties may have expended considerable resources in Markman hearings— resources that could be effectively wasted if the claims are substantively amended. Third, because different claim construction standards are applied by the two bodies charged with determining patent validity, the patent owner is often faced with a I lobson's choice of taking inconsistent claim positions during one or the other proceedings.2 Put simply, patent owners are often not free to amend claims in the same way as patent applicants during original prosecution. For all of these reasons, the CRU should interpret "broadest reasonable interpretation" in view of these very real issues faced by Patent Owner in this case and rigidly adhere to the guidelines set forth by the Federal Circuit that the claims must be interpreted in light of the specification as understood by a person of ordinary skill in the art and not in a vacuum. Obviousness "A patent may not be obtained. . if the differences between the subject matter sought to be patented and the subject matter as a whole would have been obvious at the time the invention was made to a person of ordinary skill in the art to which the subject matter pertain." 35 U.S.C. §103(a). In KSR v Teleflex 550 U.S. 398 (2006), the Supreme Court reaffirmed its decision in Graham v. John Deere that held that "the scope and content of the prior art [must] be determined; differences between the prior art and the claims at issue 2 However, when a patent owner loses their ability to amend the claims (e.g., when a patent term expires during the reexamination proceeding), the standard for claim construction moves from the broadest reasonable interpretation standard to a standard "pursuant to the principle set forth by the court in Phillips v. AWH Corp., 415 F.3d 1303, 1316, 75 USPQ2d 1321, 1329 (Fed. Cir. 2005)(words of a claim 'ale generally given their ordinary and customary meaning' as understood by a person of ordinary skill in the art in question at the time of the invention)." MPEP §2258.I.G. 1418015_1 - 23 - Attorney Docket No. 3059.014REX0 BC_GEN_0002230 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 [must] be ascertained; and the level of ordinary skill in the pertinent art [must be] resolved" in order to support a finding of obviousness. Graham v. John Deere Co., 383 U.S. 1, 17 (1966). Graham also set forth "secondary considerations" relevant to nonobviousness such as "commercial success, long felt but unsolved needs,[and] failure of others." Id at 17-18. To guard against impermissible hindsight, the Office must fully articulate its obviousness rejections. See In re Kahn, 441 F.3d 977, 986 (Fed. Cir. 2006). For instance, the Examiner may not use the challenged claims as a roadmap on how or why to combine references. Instead, the Examiner must rely solely on the prior art teachings and knowledge of a person of ordinary skill at the time the invention was made to determine whether an invention is obvious. See id.; see also MPEP 2145.X.A. For this reason, obviousness analysis is not an armchair exercise. If a person of skill in the art would not have identified the proposed combination, or if the proposed modification would have been inoperable, a conclusion of obviousness is improper. Further, "[i]f[a] proposed modification would render the prior art invention being modified unsatisfactory for its intended purpose, then there is no suggestion or motivation to make the proposed modification." MPEP 2143.01.V. Using these legal standards, each of the substantive rejections in the Office Action is addressed below in the order they were presented in the Office Action. IV. RESPONSE TO SUBSTANTIVE REJECTIONS A. Substance of the Interview The Patent Owners would like to thank Examiners Choi, Ferris, and Escalante for taking the time to conduct an interview on September 7, 2011. In attendance for the Patent Owners were: Michael Barr Technical Expert Donald Coulman (Reg. No. 50.406) Patent Owner's Representative Tim Seeley(Reg. No. 53,575) Patent Owner's Representative 1418015_1 - 24 - Attorney Docket No. 3059.014REXO BC_GEN_0002231 5 Patent Owner's Response to ROY et at. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 John Curry(Reg. No. 65,067) Sterne, Kessler, Goldstein & Fox PLLC Lori Gordon (Reg. No. 50,633) Sterne, Kessler, Goldstein & Fox PLLC Ameet Modi Desmarais LLP Michael Specht(Reg. No. 54,463) Sterne, Kessler, Goldstein & Fox PLLC Michael Stadnick Desmarais LLP Robert Sterne (Reg. No. 28,912) Sterne, Kessler, Goldstein & Fox PLLC During the interview, the Patent Owners presented the infoiniation contained in the slides that are attached as Exhibit 1 to this paper. The information contained in the slides discussed during the interview is reflected in the following remarks. B. Independent Claims 21 and 22 are Patentable Over the Combination of Augsburg and the IBM Manual. The Office Action rejected claims 21 and 22 under 35 U.S.C. § 103(a) as allegedly obvious over U.S. Patent No. 5,996,092 to Augsburg et al. ("Augsburg") in view of IBM PowerPC 403GA User's Manual, Second Edition, March 1995, [online], [retrieved on 2011- 2-9] Retrieved using internet http://i.want.to.surf.free.fr/NCD/HTML/403gaum.pdf ("the IBM Manual"). The Patent Owner traverses the rejection because claims 21 and 22 recite subject matter neither taught, disclosed, nor suggested by the combination of Augsburg and the IBM Manual. For instance, neither Augsburg nor the IBM Manual teaches, discloses, or suggests the claimed feature of a "cause register means for indicating cause information regarding interrupts and exceptions." As explained by Roy, "Nile cause registers store current information about interrupts, exceptions, and other processor functions." (Roy, 4:18-20). The specific kind of information stored in the cause register is explained in the context of storing the cause register information in bits 40-18 of the history buffer 14. (Roy, 6:39 - 7:10). As Roy explains, "bit locations 39 through 35 are used to store processor related exception conditions" and "[b]it locates 34 through 18 are used to store an indication of all pending interrupts (external, 1418015_1 - 25 - Attorney Docket No. 3059.014REXO BC_GEN_0002232 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 software, co-processor)." (Id.). Accordingly, the cause register performs at least two important functions, namely, it stores cause info' tation about (a) exception conditions: and (b) the pending interrupts. (Barr Dee!. at l'T1 42). This cause infoiination can be used by the debugger to determine the reasons why the software left the normal path of software execution. (Barr Decl. at 1142). Because Augsburg lacks any disclosure of a cause register, the Office Action relies on the IBM Manual to show this claimed feature. (Barr Decl. at ¶ 48 and 56). Specifically, the Office Action alleges that the IBM Manual teaches the cause register feature because it teaches "a machine state register(MSR) and/or an external interrupt status register (EXISR) for indicating information regarding interrupts and exceptions." (Office Action at p. 4). However, neither the MSR nor the EXISR is a cause register. (Barr Decl. at vi 56-59) The EXISR differs from the claimed cause register because, among other things, the EXISR does not store cause information regarding interrupts and exceptions. (Barr Decl. at if 58). The EXISR only contains information relating to the status of external interrupts. (IBM Manual at p. 6-9). Specifically, the IBM Manual explains that the EXISR contains the status of five external hardware interrupts. (Id.) The EXISR, however, contains no information concerning internal interrupts, co-processor interrupts, software interrupts, or exceptions. (Barr Decl. at 4r, i 59). Thus, a person of ordinary skill in the art would not view the EXISR to be the equivalent of a "cause register means for indicating cause information regarding interrupts and exceptions," as recited by claim 21. (Bart Decl. at ¶ 58). The MSR differs from the claimed cause register because it does not indicate cause infointation regarding interrupts and exceptions. (Barr Decl. at ¶ 59). The IBM Manual discloses that the MSR consists of control bits that enable groups of interrupts and exceptions, among other things. (Id.). These control bits provide no info!' iation about the interrupts and exceptions — they are more correctly viewed as switches for turning the 1418015 1 - 26 - Attorney Docket No. 3059.014REXO BC_GEN_0002233 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 interrupts and exceptions on and off. (Id,). Thus, while the MSR allows the user to control which interrupts and exceptions are enabled, it does not contain any information concerning the cause of a program's deviation from the normal path of software execution. (Id.). Accordingly, the MSR does not teach, disclose or suggest the claimed cause register means. (Id.). Since neither Augsburg nor the IBM Manual discloses or suggests a cause register means for indicating cause information regarding interrupts and exceptions, the rejection of claim 21 is improper and should be withdrawn. The rejection of claim 22, which recites similar features, is improper and should be withdrawn for at least the same reason. The Patent Owner, therefore, respectfully requests the withdrawal of the rejection of claims 21 and 22. C. Claims 1-5, 11-15, and 19-20 are Patentable Over the Combination of Augsburg, the IBM Manual,and Nakamoto. The Office Action rejected claims 1-5, 11-15, and 19-20 under 35 U.S.C. § 103(a) as allegedly unpatentable over the combination of Augsburg, the IBM Manual, and U.S. Patent No. 5,361,348 to Nakamoto ("Nakamoto). Patent Owners traverse the rejection because claims 1-5, 11-15, and 19-20 recite subject matter neither disclosed nor suggested by the combination of Augsburg,the IBM Manual, and Nakamoto. 1. Augsburg, the IBM Manual, and Nakamoto Fail to Disclose or Suggest a Cause Register Means for Indicating Information Regarding Interrupts and Exceptions. The combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest the claimed "cause register means for indicating information regarding interrupts and 1418015_1 - Attorney Docket No. 3059.014REXO BC_GEN_0002234 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 exceptions." Based on the arguments above, neither Augsburg nor the IBM Manual discloses or suggests this claimed feature. Nakamoto, which the Office Action cites for its purported disclosure of other features, fails to remedy the deficiencies that Augsburg and the IBM Manual share with respect to the claimed invention. Namely Nakamoto at least fails to disclose or suggest the claimed cause register means. (Barr Decl. at 1162). The Office Action, however, appears to suggest an equivalence between Nakamoto's latch register 6 and the claimed cause register at one point. (Office Action at 12). The Patent Owner respectfully disagrees. This false equivalence appears to stem from a misreading of Nakamoto — specifically the box labeled 302 that appears in FIG. 3, in which the word "cause" happens to appear adjacent to the word "register." (Office Action at 12). Box 302 of FIG 3, however, has nothing to do with anything even remotely similar to the claimed "cause register." As previously noted, a cause register indicates information regarding interrupts and exceptions. (Barr Decl. at III 62). The latch register 6 does none of this. (Id). Nakamoto does not contain anything called a "cause register." (Id.). Instead, box 302, read properly, simply explains that the instruction decoder and timing controller 3 generates a data latch control signal (DLCS)4, which causes the latch register 6 to latch the accessed data. (Nakamoto, 3:31-34). Tnat is, in Nakamoto, the word "cause" is used as a verb whereas in the patented claims, the word "cause" is used as an adjective. (Id.). Thus, like Augsburg and the IBM Manual, Nakamoto fails to disclose or suggest the claimed "cause register means for indicating information regarding interrupts and exceptions." 1418015_1 - 28 - Attorney Docket No. 3059.014REX0 BC_GEN_0002235 5 Patent Owner's' Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 A ugsburg, the IBM Manual, and Nakamoto Fail to Disclose or Suggest a First Decoder Means Being Directly Coupled to Said Instruction Memory Means, Said Program Counter Means, and Said Cause Register Means. The combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest a "first decoder means being directly coupled to said instruction memory means, said program counter means, and said cause register means," as recited by independent claim 1. To show this feature, the Office Action mistakenly relies on Nakamoto, which purportedly teaches "an instruction decoder and timing controller that is directly coupled to the program memory 2, the PC1, and, e.g., the latch register 6." (Office Action at p. 12). First, Nakamoto fails to disclose or suggest a first decoder means at all, so it cannot disclose a first decoder means directly coupled to anything. Apart from the use of the word "decoder" in describing them, the instruction decoder and timing controller 3 and the claimed first decoder share very little in common. (Barr Decl. at IT 61). As explained by Roy, "the decoder 28 is arranged to indicate whether the program counter has moved its point to a new instruction. ? (Roy, 4:29-31). That indication, which corresponds to processor activity in the previous cycle, is provided by the three bit output of the first decoder 28. (Roy, 4:26-29). To that end, the claims recite a first decoder with a first output that "provides infoiiiiation regarding activity of said processor in real time." (Roy, 8:22-24). Nakamoto's "instruction decoder and timing controller" does something entirely different than the claimed first decoder means. (Barr Decl. at ¶ 61). Instead of providing an indication of processor activity during a previous clock cycle, Nakamoto's "instruction decoder and timing controller 3" is integral to performing the current instruction because it produces the DI,CS and PCCS control signals, which control the latch register 6 and the program counter, respectively. (Id.) As explained by Nakamoto, the "instruction decoder and timing controller 3 decodes... instructions to provide a control signal 31 necessary to 1418015 1 - 29 - Attorney Docket No. 3059.014REX0 BC_GEN_0002236 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 execute the instructions." (Nakamoto, 3:18-20). The "instruction decoder and timing controller 3" is, therefore, very different from the claimed first decoder. (Ban Decl. at ¶ 61). Accordingly, even if Nakamoto were to disclose direct coupling between its instruction decoder and timing controller 3 and various other components, it would still not disclose the claimed "first decoder means being directly coupled to said hist action memoty means, said program counter means, and said cause register means" because Nakamoto's instruction decoder and timing controller 3 is totally different from the claimed first decoder means. (Id.). Additionally, even if Nakamoto were to disclose the claimed first decoder, it would still fail to disclose or suggest a "first decoder means being directly coupled... to said cause register means." (Ban Decl. at "II 63). This is because, as noted above, Nakamoto, like Augsburg and the IBM Manual, fails to disclose or suggest a cause register means as claimed. (Id.). Thus, it could not disclose or suggest first decoder means coupled to said cause register means, as recited by the claims. Augsburg, the IBM Manual, and Nakamoto Fail to Disclose or Suggest a Program Counter Means Directly Coupled to said Instruction Memory Means. The combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest a "program counter means directly coupled to said instruction memory means for indexing said instructions," as recited by claim 1. The Office Action relies on Nakamoto to show this claimed feature. (Office Action at 10). Patent Owner submits that this reliance is misplaced. Nakamoto shows a number of elements that comprise the signal processor 100 with various lines and arrows showing logical connections between them. (Barr Decl. at TT 53- 55). The logical connections shown in FIG. 2 show how the various components of the 1418015 1 - 30 - Attorney Docket No. 3059.014REX0 BC_GEN_0002237 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 processor interact with each other logically. (Id). The logical connections depicted in FIG. 2, however, provide little insight into how the components of processor 100 physically couple to one another. (Id.). Nakamoto, however, succinctly describes how the components are physically coupled to each other: The signal processor 100, which is fabricated as a semiconductor integrated circuit device, comprises a program memory 2 which stores a proRram. a _program counter (PC) 1 which designates addresses where instructions to be carried out in the program are stored, an arithmetic logical processing unit (ALU) 14, a register set 15 which includes an accumulator and a temporary register, a data memory 16 which stores data temporarily, and a debug circuit 50. The_se comppents are_ connected with each other through an internal bus 5. (Nakamoto, 5:27-28) (emphasis added). Thus, Nakamoto discloses connecting the various components of its signal processor 100 via an internal bus 5. In contrast to Nakamoto, the claimed program counter means is directly coupled to the claimed instruction memory means. (Barr Decl. at *i 65). As is clear in the context of the initial prosecution of the Roy patent, directly coupled has a very particular and specific meaning: two elements are directly coupled to one another if they are connected to each other without any intermediate elements between them. (Id.). An internal bus, such as the one described by Nakamoto, constitutes an intermediate element. (Id.). This exact issue was actually already decided during the initial prosecution ofthis patent. During the initial prosecution, the original claims recited various elements "connected" to one another. (Barr Decl. at 1[1f 43-45). The Examiner cited U.S. Patent No. 5,473,754 to Folwell et al. to show the claimed "connection." (Id.). Specifically, the Examiner indicated that Folwell showed a first decoder and instruction memory that were connected via a program data bus 24. (Id.). At the time, the Examiner noted that amending the term "connected" to "directly coupled" would overcome the rejection based on Folwell's disclosed connection of the first decoder and instruction memory via the program data bus. 1 418015 1 -31 - Attorney Docket No. 3059.014REXO BC_GEN_0002238 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 (Id.). Applicant amended the claims to recite "directly coupled" and the claims were allowed. (Id.). Thus, "directly coupled" overcame a rejection based on a similar bus during the initial prosecution. (Id.). A person of ordinary skill in the art would, therefore, not view two circuit components connected via a bus to be directly coupled as recited by the claims. (Id.). A person of ordinary skill in the art would, therefore not understand Nakamoto to disclose direct coupling of the program counter to the program memory, but, at best, indirect coupling since Nakamoto describes that they are connected via an internal bus 5. (Barr Decl. at ¶ 65). The combination of Augsburg, the IBM Manual and Nakamoto, therefore, still fails to disclose or suggest the claimed program memory "directly coupled" to a program counter. (Barr Decl. at II 68). iv. Because Augsburg, the IBM Manual, and Nakamoto Fail to Disclose or Suggest each and every claimed elements, the rejections should be withdrawn. Independent claim 1 recites, amongst other things, (a) "cause register means for indicating information regarding interrupts and exceptions," (h)a "first decoder means being directly coupled to said instruction memory means, said program counter means, and said cause register means," and (c) "a program counter means directly coupled to said instruction memory means." As discussed above, the combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest these features of claim 1. Claim 1 is, therefore, patentable over the combination of Augsburg, the IBM Manual, and Nakamoto and the rejection of claim 1 is improper and should be withdrawn. Dependent claims 2-5 depend from claim 1 and are patentable for at least the same reasons as well as for the additional features they recite. The Patent Owner, therefore, respectfully requests the withdrawal of the rejection of claims 1-5. 1418015 1 - 32 - Attorney Docket No. 3059.014REXO BC_GEN_0002239 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 Similar to claim 1, independent claim 11 recites, among other things (a) "a plurality of cause register means for indicating information regarding interrupts and exceptions for a corresponding one of said plurality of processors, each of said cause register means being directly coupled to a respective one of said processors," and (b) a "a plurality of first decoder means, each said first decoder means directly coupled to a respective one of said instruction memory means, to a respective one of said program counter means, and respective one of said cause register means," and (c) "a plurality of program counter means, each directly coupled to a respective one of said plurality of instruction memory means." As discussed above, the combination of Augsburg, the IBM Manual, and Nakamoto fails to disclose or suggest these features of claim 11. Claim 11 is, therefore, patentable over the combination of Augsburg, the IBM Manual, and Nakamoto and the rejection of claim 11 is improper and should be withdrawn. Dependent claims 12-15 and 19-20 depend from claim 11 and are patentable for at least the same reasons as well as for the additional features they recite. The Patent Owner, therefore, respectfully requests the withdrawal of the rejection of claims 11-15 and 19-20. V. NEWLY PRESENTED CLAIMS 23-46 ARE PATENTABLE OVER THE CITED REFERENCES Newly presented claims 23-56 depend either directly or indirectly from one of independent claims 1, 11, 21, and 22 and are patentable for at least the same reasons stated above with respect to claims 1, 11, 21, and 22 as well as for the additional features they recite. The Patent Owner, therefore, respectfully requests that the Office enter the new claims and pass them to issue. 1418015 1 - 33 - Attorney Docket No. 3059.014REXO BC_GEN_0002240 5 Patent Owner's Response to ROY et al. Office Action dated July 29, 2011 Reexamination Control No. 90/011,532 VI. CONCLUSION All of the stated grounds of rejection have been properly traversed, accommodated, or rendered moot. The Patent Owner therefore respectfully requests that the Examiner reconsider all presently outstanding rejections and that they be withdrawn. The Patent Owner believes that a full and complete reply has been made to the outstanding Office Action and that the claims under reexamination are allowable over the rejections presented in the Office Action. Prompt and favorable consideration ofthis Reply is respectfully requested. Respectfully submitted, STERNE,KESSLER,GOLDSTEIN & Fox P.L.L.C. tr\ \;.:{' / " Michael D. Specht Attorney for Patent Owner Registration No.54,463 John H. Curry;Attorney for Patent Owner Registration No. 65,067 Date: Sep. 27, 2011 1 100 New York Avenue, N.W. Washington, D.C. 20005-3934 (202) 371-2600 1418015_1 1418015) - 34 - Attorney Docket No. 3059.014REXO BC_GEN_0002241 5 I-N THE UNITED STATES Pi TENT AND TRADEMARK OFFICE In re: Ex Parte Reexamination of Confirmation No.: 3636 U.S. Patent No. 6,321,331 to ROY et al. Art Unit: 3992 Control No.: 90/011,532 Examiner: CHOI, Woo H. Filed: March 4, 2011 Atty. Docket: 3059.014REX0 For: Real Time Debugger Interface for Embedded Systems Information Disclosure Statement by Patent Owner Mail Stop "Ex Parte Reexam" Attn: Central Reexamination Unit Commissioner for Patents P.O. Box 1450 Alexandria, VA 22313-1450 Sir: Listed on accompanying IDS Fotins PTO/SB08a equivalent and PTO/SB/08b equivalent are documents that may be considered material to the patentability of this reexamination as defined in 37 C.F.R. §§ 1.56(b), 1.555(b), and 1.933. Copies of the listed documents are provided in compliance with the requirements of 37 C.F.R. §§ 1.97 and 1.98, and with MPEP § 2280.1 In accordance with 37 C.F.R. § 1.97, the filing of this lIDS should not be construed to be an admission that the info'!nation cited in the statement is, or is considered to be, material to patentability as defined in 37 C.F.R. § 1.56(b). Further, the Patent Owner has listed publication dates on the attached IDS Fauns based on information presently available to the undersigned. However, the listed publication dates should not be construed as an admission that the information was actually published on the date indicated. According to MPEP § 2280, the exception for providing copies noted in 37 C.F.R. § 1.98(d) is not applicable to ex parte or inter partes reexamination proceedings. Accordingly, copies of non-patent literature and other non-exempt classes of material are provided. BC_GEN_0002242 5 2- Control No. 90/011,532 Atty. Dkt. No. 3059.014REXO The Patent Owner reserves the right to establish the patentability of the claimed invention over any of the information provided herewith, and/or to prove that this information may not be prior art, and/or to prove that this information may not be enabling for the teachings purportedly offered. Further, this statement should not be construed as a representation that a search has been made, or that information more material to the examination of the present reexamination does not exist. The Examiner is specifically requested not to rely solely on the material submitted herewith. It is respectfully requested that the Examiner initial and return a copy of the enclosed IDS Forms, and indicate in the official file wrapper of this reexamination that the documents cited herein have been considered. Pursuant to 37 C.F.R. § 1.565, TR Technologies Foundation LLC ("the Patent Owner") hereby notifies the Office of concurrent proceedings involving the above captioned U.S. Patent No. 6,321,331 ("the '331 patent"). The '331 patent was the subject of a concurrent proceeding in the United States District Court in the Northern District of California styled Xilinx, Inc., v. Invention Investment Fund 1 LP et al., Civil Action No. 3:11-cv-00671 ("NDCA Action"), filed on February 14, 2011. This action was dismissed as to the '331 patent for lack of standing. The Patent Owner is a defendant in a concurrent proceeding in the United States District Court in the Northern District of California styled Xilinx, Inc., v. Intellectual Ventures Management, LLC et al., Civil Action No. 5:11-cv-04407, filed September 2, 2011. The '331 Patent is an asserted patent therein. BC_GEN_0002243 5 3 Control No. 90/011,532 Atty. Dkt. No. 3059.014REX0 It is expected that the examiner will review the prosecution and cited art in U.S. Patent Application No. 09/064,474, filed April 22, 1998 (now U.S. Patent No. 6,321,331), in accordance with MPEP 2001.06(b), and in related U.S. Patent Application No. 09/918,123, filed July 30, 2001 (now Abandoned), and indicate in the next communication from the office that the art cited in the earlier prosecution history has been reviewed in connection with the present application. It is not believed that any fees are required with submission of this IDS. (See MPEP § 2202.) However, if necessary, the U.S. Patent and Trademark Office is hereby authorized to charge any fee deficiency, or credit any overpayment, to our Deposit Account No. 19-0036. Respectfully submitted, STERNE,KESSLER,GOLDSTEIN & Fox P.L.L.C. 0 C Michael D. Specht Attorney for Patent Owner Registration No. 54,463 Date: ........3 1 100 New York Avenue, N.W. Washington, D.C. 20005-3934 (202) 371-2600 1422396_1.DOCX BC_GEN_0002244