Bicameral LLC v. NXP USA, Inc. et al

Western District of Texas, txwd-6:2018-cv-00294

Exhibit Kheyfits Ex. 4

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Kheyfits Declaration Exhibit 4 IN THE UNITED STATES DISTRICT COURT FOR THE WESTERN DISTRICT OF TEXAS WACO DIVISION § Bicameral LLC, § § Plaintiff § § v. § Case No. 6:18-cv-00294-ADA § NXP USA, Inc., NXP Semiconductors N.V., § Jury Trial Demanded and NXP B.V., § § Defendants. § § § § DEFENDANTS' PRELIMINARY INVALIDITY CONTENTIONS PURSUANT TO SCHEDULING ORDER (DKT. #39) Defendants NXP USA, Inc., NXP Semiconductors N.V., and NXP B.V. (collectively, "NXP" or "Defendants") hereby submit their Preliminary Invalidity Contentions regarding claims asserted by Plaintiff Bicameral, LLC ("Plaintiff" or "Bicameral"), pursuant to the Scheduling Order (Dkt. #39), which provides in relevant part: Defendant serves preliminary invalidity contentions in the form of (1) a chart setting forth where in the prior art references each element of the asserted claim(s) are found, (2) an identification of any limitations the Defendant contends are indefinite or lack written description under section 112, and (3) an identification of any claims the Defendant contends are directed to ineligible subject matter under section 101. Regarding item (1), Defendants provide charts attached hereto "setting forth where in the prior art references each element of the asserted claim(s) are found" and also provide additional information. Defendants' charts are preliminary and are provided with the understanding that whether the pointer cache is modified and/or how it is modified to indicate that the external buffer is in use. Therefore, these claims are invalid under § 112 ¶ 1 at least for lack of written description support. As another example, claim 1 of the '331 Patent recites "first decoder means being directly coupled to said instruction memory means, said program counter means, and said cause register means." The '331 specification fails to explicitly disclose how to understand the term "directly coupled" as highlighted by Plaintiff's own Infringement Contentions. Similarly, claims 1 and 21 of the '331 Patent recite "first output provides information regarding activity of said processor in real time." The '331 specification fails to explicitly disclose how to understand the term "in real time" and what "information" must be provided as output as highlighted by Plaintiff's own Infringement Contentions. The same is true for the "cause register means" and the "decoder means." For example, the "cause register means" is allegedly some information related to both interrupts and exceptions. However, the '331 specification does not provide any basis to distinguish interrupts from exceptions and many processor architectures intermingle the terminology and/or use the same type of "handlers" to perform processing regardless of whether the event is denominated an "interrupt" or an "exception." The '331 specification did not explain the difference between these two events sufficiently to convey that alleged difference meaning to one of ordinary skill in the art. Therefore, these claims are invalid under § 112 ¶ 1 at least for lack of written description support. Because of these exemplary deficiencies in the specifications of the Asserted Patents, the disclosures in the Asserted Patents do not reasonably convey to those skilled in the art that the inventor had possession of the claimed subject matter as of the effective filing date and fail to enable a POSITA to practice the full scope of the Asserted Claims without undue experimentation. 35