Bicameral LLC v. NXP USA, Inc. et al

Western District of Texas, txwd-6:2018-cv-00294

Exhibit Kheyfits Ex. 6

Interested in this case?

Current View

Full Text

3 Kheyfits Declaration Exhibit 6 3 USOO962628OB2 (12) United States Patent (10) Patent No.: US 9,626,280 B2 Ehrlich et al. (45) Date of Patent: Apr. 18, 2017 (54) DEBUG METHOD AND DEVICE FOR (56) References Cited HANDLING EXCEPTIONS AND INTERRUPTS U.S. PATENT DOCUMENTS 6,453,411 B1* 9/2002 Hsu ....................... GO6F 9/38O2 (71) Applicants: Robert N. Ehrlich, Round Rock, TX T11 202 (US); Robert A. McGowan, Cedar 7,752.425 B2 T/2010 Williams et al. Park, TX (US); Michael B. Schinzler, 7,966,479 B1* 6/2011 Thaik .................. G06F 2.99 Austin, TX (US) 7.992,052 B2 8/2011 Moyer et al. 8,032,710 B1 * 10/2011 Ashcraft ............. GO6F9,30072 (72) Inventors: Robert N. Ehrlich, Round Rock, TX T11 133 (US); Robert A. McGowan, Cedar (Continued) Park, TX (US); Michael B. Schinzler, Austin, TX (US) OTHER PUBLICATIONS ARM Limited, "CoreSight Program Flow Trace: Architecture (73) Assignee: NXP USA, INC., Austin, TX (US) snaroo ARS IHI g copyright 1999-2002, 2004 2008, ARM Ltd; printed from <http://infocenterarm.com/help? (*) Notice: Subject to any disclaimer, the term of this topic?.com.arm.doc.ihi0035b/IHI0035B cs pft v1 1 architec patent is extended or adjusted under 35 ture spec.pdf> on Feb. 21, 2013, 288 pages. U.S.C. 154(b) by 692 days. (Continued) Primary Examiner — Michael Sun (21) Appl. No.: 13/932,189 (57) ABSTRACT A method and information processing SVStem provide trace (22) Filed: Jul. 1, 2013 compression for trace NS In N t a branch of a conditional branch instruction having not been taken or (65) Prior Publication Data having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a US 2015/OOO6869 A1 Jan. 1, 2015 conditional indirect branch instruction being taken, wherein the trace address message includes address information (51) Int. Cl. indicating the destination address of the taken branch, and al G06F 9/00 (2006.01) index value indicating a corresponding flag of the history G06F 9/44 (2006.01) buffer. In response to a return from interrupt or return from G06F II/36 (2006.01) exception instruction, a predicted return address is compared to an actual return address. A trace address message is (52) U.S. Cl. generated in response to the predicted and actual return CPC ................................ G06F II/36.36 (2013.01) addresses not matching. A trace address message is not (58) Field of Classification Search E. in Ense to the predicted and actual return None addresses match1ng. See application file for complete search history. 20 Claims, 7 Drawing Sheets 501 -500 DEBUG PROCESSING --SAVE INSTRUCTION ADDRESS OF EXCEPTIONAL --PUSH CURRENT ADDRESS TO STACK --CAPTURE DESTINATION ADDRESS --DETERMINE ADDRESS INFORMATION - -DETERMINEDESTINATION ADDRESS FOR TRACE MESSAGE --LOADPC WITH DESTINATION ADDRESS --INDEX, ICNT -- ADDR --DETERMINE TCODEABCODE --TRANSMIT TRACE MESSAGE 3 US 9,626.280 B2 Page 2 (56) References Cited U.S. PATENT DOCUMENTS 8,037.285 B1 * 10/2011 Thaik .................. GO6F9,30189 T12,211 8,886,920 B2 * 1 1/2014 Olson ........................... 712/237 2005/0010912 A1* 1/2005 Adolphson ........... G06F 8,4441 717/151 2012fO233442 A1* 9, 2012 Shah ..................... G06F 93806 71.2/2O7 2012fO290820 A1* 11/2012 Olson ................... G06F 93806 T12/233 OTHER PUBLICATIONS U.S. Appl. No. 13/932,183, McGowan, R. et al., "Debug Method and Device for Providing Indexed Trace Messages'. Office Action—Non-Final Rejection, mailed Feb. 26, 2016. U.S. Appl. No. 13/932,183, McGowan, R. et al., "Debug Method and Device for Providing Indexed Trace Messages'. Office Action Notice of Allowance, mailed Sep. 22, 2016. U.S. Appl. No. 13/932,183, Mcgowan, R. et al., "Debug Method and Device for Providing Indexed Trace Messages". Office Action— Notice of Allowance, mailed Dec. 21, 2016. * cited by examiner 3 U.S. Patent Apr. 18, 2017 Sheet 1 of 7 US 9,626,280 B2 GLOBAL CONTROL EXECUTION UNITS 119 STACK 109 REGISTER FILES 118 BUS DEBUG MODULE INTERFACE UNIT (BIU) EXTERNAL DEVELOPMENT SYSTEM (E. G., DEBUGGER) AVG. Z 3 U.S. Patent Apr. 18, 2017 Sheet 2 of 7 US 9,626,280 B2 116 St.--------------- 131 TO TRACE MESSAGE GLOBAL ADDRESS REQUEST CONTROL COMPRESSION LOGIC 133 MESSAGE GENERATION MODULE 134 DEBUG CONTROL MODULE INPUT-OUTPUT TO DEBUG INTERCONNECT 135 (I/O) 108 MESSAGE FIFO BUFFER FROM DEBUG GLOBAL CONTROL MODULE 123 3 U.S. Patent Apr. 18, 2017 Sheet 3 of 7 US 9,626,280 B2 822ºZZZ 9 3 U.S. Patent Apr. 18, 2017 Sheet 4 of 7 US 9,626,280 B2 -400 404 403 402 401 TIMESTAMP ICNT INDEX TCODE Af7G. 4 501 -500 START 502 WAIT FOR EXCEPTION/INTERRUPT V 7 Y N 14 1 1 ------------------------4-------- --SAVE ADDRESS OF EXCEPTIONAL -- PUSH CURRENT ADDRESS INSTRUCTION TO STACK --CAPTURE DESTINATION ADDRESS --DETERMINE ADDRESS INFORMATION --DETERMINEDESTINATION ADDRESS --LOADPCWITH DESTINATION FOR TRACE MESSAGE ADDRESS --INDEX, ICNT - - ADDR --DETERMINE TCODE/BCODE --TRANSMIT TRACE MESSAGE - - - - - - - - - - - - - - - - - - - - - - - - - - 3 U.S. Patent Apr. 18, 2017 Sheet S of 7 US 9,626,280 B2 601 60 0 START DOES PREDICTED RETURN ADDRESS = STACK ADDRESS --SEND--TCODE TRACE MESSAGE --BTYPE --ADDR/ICNT --HIST --OTHER --CLEAR HIST BUFFER 3 3 U.S. Patent Apr. 18, 2017 Sheet 7 Of 7 US 9,626,280 B2 MESSAGE RECEIVED ? DOES DOES MESSAGE INCLUDE MESSAGE INCLUDE INDIRECT BRANCH HISTORY FLAG BUFFER CONTENTS NFORATI) YES 804 YES 806 BRANCH INFORMATION CORRESPONDING ENCOUNTERED BRANCHES AS HAVING NOT BEEN TAKEN AND USE HISTORY BUFFER FLAGS HAVING SECOND WALUE TO DETERMINE CORRESPONDING ENCOUNTERED BRANCHES AS HAVING BEEN TAKEN 807 RETRIEVE STORED INDIRECT BRANCH INFORMATION 808 USE INDEX TO ASSOCIATE INDIRECT BRANCH INFORMATION WITH ENCOUNTERED BRANCHES DETERMINED AS HAVING BEEN TAKEN 809 CONSTRUCT REPRESENTATION OF CODE EXECUTION IN DEBUGGER 810 Af7G. S. END ------------ - 3 US 9,626,280 B2 1. 2 DEBUG METHOD AND DEVICE FOR least one embodiment suitable for implementation, for HANDLING EXCEPTIONS AND example, in an external debugger. INTERRUPTS The use of the same reference symbols in different draw ings indicates similar or identical items. CROSS-REFERENCE TO RELATED APPLICATION(S) DETAILED DESCRIPTION OF THE DRAWINGS The present application is related to co-pending U.S. A data processing system is disclosed that includes trace patent application Ser. No. 13/932,183, entitled "DEBUG debugging capabilities to facilitate debugging of program METHOD AND DEVICE FOR PROVIDING INDEXED 10 code for a data processor. A debug module of the data TRACE MESSAGES, filed on an even date herewith, the processor maintains a history buffer, referred to as an entirety of which is herein incorporated by reference. Instruction Flow history Flag Buffer (IFFB), having a plu rality of flags, each of which corresponds to a particular BACKGROUND instruction that typically affects program flow, Such as a 15 branch instruction. The IFFB stores instruction flow history Field of the Disclosure information, Such as branch information, that indicates This disclosure relates generally to debugging facilities whether branches of executed branch instructions were for an information processing system and, more specifically, taken or not taken. For example, each executed branch to debug trace messaging. instruction can correspond to a specific bit location of the Description of the Related Art IFFB where a flag is stored, wherein the flag is set if the New software may be developed using software devel branch of its corresponding branch instruction is taken (the opment tools. Such tools can include an external debugger branch instruction was taken), and the flag is cleared if the connected to a data processor, via a debug interface of the branch was not taken (the branch instruction was not taken). processor, to determine instructions executed by the data So long as the destination address of each taken branch processor, and to present a representation of the executed 25 instruction is deterministic, the external debugger, by virtue instructions to a user. The execution of instructions at the of having a copy of the executing source code, can deter data processor is monitored by a debug processing module mine the instruction flow through the data processor based of the data processor during a debug trace mode. During upon the IFFB flags. However, when a branch is an indirect debug trace mode, the debug processing module can main branch, Such when a conditional indirect branch instruction tain instruction flow history information that is indicative of 30 is executed, the branch destination is indeterminate with the executed instructions. Since data processors can execute respect to the external debugger, and address information instructions very quickly, such history information can rep that indicates the destination address of the taken branch resent large numbers of executed instructions, therefore, it is needs to be provided. Typically this is accomplished by desirable to reduce in the amount of history information that generating and transmitting a trace address message to the is communicated between the debug processing module and 35 external debugger that includes both the valid IFFB flags the external debugger to reduce bandwidth requirements. and the branch destination address information to the exter nal debugger. Based upon the IFFB flags, the external BRIEF DESCRIPTION OF THE DRAWINGS debugger can determine which executed instruction caused the information to be communicated, and can use the trans The present disclosure may be better understood, and its 40 mitted destination address information to determine the numerous features and advantages made apparent to those branch address of the taken conditional indirect branch skilled in the art by referencing the accompanying drawings. instruction. FIG. 1 illustrates a block diagram illustrating a data According to a particular embodiment disclosed herein, processing system in accordance with at least one embodi instead of transmitting the IFFB information and destination ment. 45 address information together in the trace address message, FIG. 2 illustrates a block diagram illustrating a debug the destination address information is transmitted without module of a data processor of FIG. 1 and various storage including the valid IFFB flags, and instead includes an index locations in accordance with at least one embodiment. identifying a specific flag of the IFFB (an indexed flag), FIG. 3 illustrates a block diagram that represents a plu which is transmitted independent of the trace address mes rality of instructions in linear address space in accordance 50 sage. Such as in a Subsequent trace history message. Thus, with a specific example. for a particular taken branch instruction, the destination FIG. 4 illustrates a block diagram representing a trace address information and an index identifying a particular message including a timestamp value in accordance with at flag location of the IFFB can be transmitted to the external least one embodiment. debugger as part of a trace address message, while the IFFB FIG. 5 illustrates a flow diagram illustrating a particular 55 having a flag referenced by the index of the trace address can embodiment of handling exceptions/interrupts by a debug be transmitted to the external debugger, as part of a trace processing module and an exception/interrupt processing history message, in response to the IFFB being Subsequently module in accordance with at least one embodiment. filled. The use of indexed trace messages in this manner can FIG. 6 illustrates a flow diagram illustrating a method of result in a reduction of debug information needed to be handling instructions, including return from exception/inter 60 transmitted. rupt instructions, in accordance with at least one embodi According to another embodiment of implementing ment. debug processing, disclosed herein, an exception/interrupt FIG. 7 illustrates a block diagram that represents a plu causes a trace address message that identifies the instruction rality of instructions in linear address space in accordance that was being executed when the exception/interrupt with at least one embodiment. 65 occurred to be transmitted to an external debugger. In FIG. 8 is a flow diagram illustrating a method for trace addition, the exception/interrupt causes a return address to history buffer utilization improvement in accordance with at be pushed onto a stack of the data processor, and to be stored 3 US 9,626,280 B2 3 4 by a debug processing module as a predicted return address. debugger for receiving trace messages and displaying the In response to a Return From Exception (RFE) instruction, information they contain (with or without decoding the or a Return From Interrupt (RFI) instruction, being information to be displayed), and the like. executed, the debug module compares the predicted address FIG. 2 is a block diagram illustrating a more detailed view to the actual return address that resulted. If the addresses of a particular embodiment of debug module 116, of register match, there is no need for the debug module to generate a file 109, which includes registers 110-115, and of storage trace address message to report the return address, as an locations 120, which by way of example is illustrated as external debugger can determine that return processing will residing local to the debug module 116 for quick access. continue at a deterministic location relative to the instruction Debug module 116 includes trace message request mod that was executing when the exception/interrupt occurred. 10 ule 131, message generation module 132, debug control However, if the addresses don't match, the debug module of module 134, and input-output (10) module 136. Various the data processor will transmit an address trace message to connections to the execution units of FIG. 1 can provide the external debugger providing address information used by information to the components of FIG. 2. For example, the external debugger to determine the actual return address. connection 137 is specifically illustrated in FIG. 2 that FIG. 1 is a block diagram illustrating a data processing 15 provides one or more addresses from the data processor system 100 in accordance with at least one embodiment. system of FIG. 1 to the trace message request module 131, Data processing system 100 includes data processor 101, and a connection between the trace message request module memory 102, debugger 103, and interconnect 104. Data 131 and the global control module 123 is also specifically processor 101 includes global control unit 123, load/store illustrated at FIG. 2. It will be appreciated that other con unit 125, memory management unit (MMU) 122, bus inter nections to the block diagram of FIG. 2 can exist. Message face unit (BIU) 121, instruction fetch unit 126, instruction generation module 132 is capable of generating debug decoder 127, execution units 117, and debug module 116. messages, referred to as trace messages, that transmit vari Global control unit 123 is illustrated to include a process ous information to the external debugger 103 in response to identifier (PID) register 124, and is connected to load/store requests from trace message request module 131. One type unit 125, to MMU 122, to instruction fetch unit 126, to 25 of trace message is a trace address message, which as used instruction decoder 127, to execution units 117, and to debug herein is intended to refer to a trace message that provides module 116. MMU 122 is further connected to instruction address information that can be used to determine the fetch unit 126, to debug module 116, and to BIU 121. address of a particular instruction. Another type of trace Instruction fetch unit 126 is further connected to instruction message is a trace history message, which for example, can decoder 127 and to BIU 121. Instruction decoder 127 is 30 provide IFFB flag information that can be used to determine further connected to execution units 117. Execution units the instructions executed by a data processor. 117 can access a stack 119, and are further connected, via By way of example, various debug?trace information that connection 118, to debug module 116. BIU 121 is further can be transmitted as part of a trace message are illustrated connected to debug processor module 116 and, via connec as stored at registers 110-115. Debug/trace information tion 105, to interconnect 104. Debug module 116 includes 35 specifically illustrated includes: a TCODE value, stored at storage locations 120 that can store address predictions for register 110, that identifies a particular type of message to be return from exception/interrupt commands, and is further sent from debug module 116 to an external debugger, a connected, via connection 108, to external debugger 103 BTYPE value, stored at register 112, that identifies a type (e.g., external development system, and, via connection 107. associated with a particular encountered event that is asso to interconnect 104. Memory 102 is connected to intercon 40 ciated with the trace message. Such as a branch type, an nect 104 via connection 106. interrupt, an exception, and the like; IFFB information, In operation, data processor 101 can communicate with stored at register 114 that stores trace history information memory 102 and other devices (not shown) via interconnect Such as whether specific branches are taken or not taken; 104. Information communicated between memory 102 and direct address information ADDR, stored at register 113, that other devices, such as load/store 125 and MMU 122, can 45 identifies a particular address, such as a destination address transfer through BIU 121. Instruction fetch unit 126 of a branch; an INDEX value (pointer) that identifies the retrieves data processor instructions from BIU 121 under location of a particular flag of the IFFB, which in turn is control of global control module 123. The retrieved instruc associated with a particular instruction or other flow event; tions are communicated to instruction decoder 127 for an ICNT value, stored at register 115, that may store offset decoding, which can occur under control of global control 50 information, such as a number of instructions or addresses, module 123. Execution units 117 execute instructions and that can be used to identify a specific instruction or address generate data that can be stored in register files 109, a stack location relative to a branch instruction that corresponds to 119, a cache (not shown), or placed in the memory 102 (via the INDEX value. For convenience, the data mnemonic of global control module 123, BIU 121 and interconnect 104). each of the registers 110-115 can also be used herein to refer Debugging the operation of data processor 101 and data 55 to the register itself. For example, the index register would processing system 100 is facilitated by the use of debug be understood to refer to the register 111. module 116, which, upon entering a debug mode of opera Thus, it will be appreciated, that as execution units 117 tion, can generate debug messages that include debug infor execute instruction code, debug module 116 can obtain mation for analysis by external development system (debug information about the execution of those instructions via ger) 103. 60 various connections and store the information in registers External debugger 103 may be implemented in a variety 110-115. When debug module 116 has information to send of ways. As examples, external debugger 103 may be a to debugger 103, a debug message can be generated and debugger integrated with a software development system, a send to a trace message with the pertinent information. debugger that may support multiple types of processors, a The information described as being stored in registers specific-purpose debugger for utilizing a processor for a type 65 110-115 does not necessarily need to be stored in registers. of application, a specific-purpose debugger for obtaining, Some or all of such values may be made available for storing, and transmitting program trace information, a inclusion in a trace message directly, for example, by the 3 US 9,626,280 B2 5 6 outputs of circuitry Such as combinational logic or the like. external debugger. It will be appreciated that address infor Trace messages, or information used to generate trace mes mation of a taken indirect conditional branch can be com sages (e.g., values described with respect to registers 110 municated directly as an address value, or indirectly as an 115), may be stored in trace buffers (e.g., first-in-first-out offset relative a predetermined point of reference. (FIFO) buffers) before being transmitted via connection 108. At FIG. 3, branch instruction 211 will eventually be Multiple instances of such trace buffers may be employed executed by the data processor executing instruction code and may be configured in series, in parallel, or in a combi 210. Assuming branch instruction 211 is a conditional indi nation thereof, with each other. For example, debug control rect branch instruction, its execution is evaluated to deter module 134 may include a first-in-first-out (FIFO) buffer mine whether or not its branch (BR1) was taken or not taken. 135 to store trace messages in a particular order for com 10 In the example shown, the branch has been taken, causing munication to an external debugger. A particular manner of instruction flow to progress to a destination instruction 214 collecting and transmitting instruction flow history informa at a destination address ADDR1. Thus, assuming the IFFB tion, and generating trace messages having index values that is empty prior to at the execution of branch instruction 211, reference the instruction flow history information, will be the first flag of the IFFB (BIT 0) of message 229 is set. Other better understood with reference to the following figures. 15 branch specific information, as previously described, can be FIG. 3 is a block diagram including a line 210 that stored in various registers, including the destination address represents a plurality of instructions in linear address space (ADDR1), which can be stored in register 113. Note that by that result in a particular instruction flow, and a set of trace virtue of the external debugger having a source copy of the messages (229-231) that are generated based upon the code being executed, the external debugger knows that BIT instruction flow. It will be appreciated, that line 210 can 0 of the IFFB corresponds to branch instruction 211. represent instruction code that is arranged in an order of According to an embodiment, no trace history message normally advancing instruction execution (e.g., the order of will be generated to communicate the contents of the IFFB execution when a program counter is incremented from an to the external debugger at this time because the IFFB is not instruction to an immediately succeeding instruction). full subsequent to branch instruction 211 being executed. Branch instructions of the illustrated instruction code 210 25 This is different than other debug techniques that transmit are represented by points 211, 213, 215, and 216. As valid flags from the IFFB and address information in instructions are executed, conditional branch instructions response to each conditional indirect branch that is taken So can either be taken to another memory address other than the that the external debugger can correlate the last executed memory address that immediately follows the conditional branch instruction, indicated by the IFFB data, to the address branch instruction, or not taken and simply continue sequen 30 information, which identifies the branch destination. tially to the memory address that immediately follows. It While the IFFB information is not communicated to the will be appreciated that various fields of the debug trace external debugger in response to the branch being taken, a messages 229-231 can correspond to various information trace address message 230 is generated that indicates the stored at register file 109, where trace information can be destination address of the taken branch of instruction 211. In stored prior to generation of the particular messages 229 35 the illustrated embodiment, the trace address message 230 231. includes information TCODE, BTYPE, and information that As instruction flow proceeds along line 210, each encoun includes INDEX1 and ICNT. tered branch instruction is associated with a next available The INDEX of the trace message indicates that the bit in the IFFB, where each associated bit represents a flag message 230 identifies BIT 0 of the IFFB, thereby allowing that indicates whether the branch was taken or not taken for 40 the external debugger to correlate the trace address message its corresponding instruction. Note that message 229 repre 230 specifically to the branch instruction 211. This allows sents a trace history message having a TCODE 209, and a the external debugger to associate the address information of predetermined number of flags, and is generated in response trace address message 230 with branch of instruction 211. to each of the available IFFB flag bits (bit 0 through bit 7) Trace address message 230 can be referred to as an incre being valid, e.g., each IFFB bit is associated with a particular 45 mental trace address message, as its address information instruction or flow event. Once the trace history message is includes ICNT1, which provides an incremental instruction/ generated, the IFFB can be cleared. By way of example, if address count that is added to the address of the branch the branch of an executed branch instruction is not taken, the instruction 211 identified by the INDEX. It will be appre branch instruction's corresponding IFFB flag is cleared, e.g., ciated that a direct trace address message that provides an programmed to a logic Zero. Otherwise, if the branch of the 50 actual address (ADDR) can be generated instead of an executed branch instruction is taken, the branch instruction's incremental trace address message. corresponding IFFB flag is set, e.g., programmed to a logic Instruction code execution continues from instruction 214 OC. and arrives at a conditional branch instruction 215. The No branch destination address information needs to be condition of the conditional branch instruction 215 is evalu sent to an external debugger when a branch is not taken, as 55 ated to determine whether or not the branch is to be taken. flow continues at the address following the instruction. In the example shown, it is determined that the branch BR2 Similarly, no additional branch destination address informa from conditional branch instruction 215 is not taken, and tion needs to be sent to an external debugger when a therefore there is no branch destination address to report. A conditional direct branch is taken, as the destination address second flag (BIT 1) of the IFFB is cleared, indicating the of a direct branch is known by the external debugger by 60 branch was not taken, and flow continues without generating virtue of it having a copy of the source instruction code another trace message at this time. inherently known at compile time. However, the destination From conditional branch instruction 215, instruction code address of a branch is not inherently known by the external execution continues and arrives at conditional branch debugger when a conditional indirect branch is taken. There instruction 216. In the example shown, it is determined that fore, a trace address message that includes additional 65 branch BR3 from conditional branch instruction 216 is to be address information identifying the branch destination taken to instruction 202. Thus, the third flag (BIT 2) of the address needs to be generated for communication to the IFFB is set, and the destination address (ADDR2) of con 3 US 9,626,280 B2 7 8 ditional branch instruction 216 is stored for transmission as column indicates there is a corresponding IFFB flag at the bit part of a trace address message 231. Trace message 231 can location indicated by the integer. The next column, labeled be referred to as a direct address trace address message as it Comment, indicates whether various branch instructions sends the actual address of the destination location, as were taken or not taken. The last column, labeled Trace opposed to an incremental count of instructions or MSG Type, indicates those trace messages generated in addresses. response to the instruction being executed, if any. Instruction code execution continues and arrives at con Execution of the exemplary pseudocode of Table 1 begins ditional branch instruction 213. In the example shown, it is at label event loop (address 0x100) at a time when none of determined that branch BR4 of conditional branch instruc the IFFB flags have been determined. A non-branch instruc tion 213 is not to be taken. Thus, the fourth flag (BIT 3) of 10 tion is executed at address 0x100 that does not result in any the IFFB is cleared and execution of the instruction code continues changes to the IFFB, nor is a trace message generated. Note instructionwith 213.the instruction following conditional branch that that by way of example, that none of the eight bits of the As execution continues and additional conditional branch IFFB contain any valid information s represented by the instructions are encountered (which may include Subsequent 15 eight X indicators. Thus the IFFB is 8 XXxxxx. Also, the instances of the same conditional branch instructions illus- trated at FIG. 3), additional flags in the instruction flow value in the Index column of address 0x100 is X because the non-branch instruction is not associated with any of the history flag buffer are programmed to values representative flags of the IFFB. From address OX100, execution proceeds of whether or not encountered branches were taken or not to address 0x104, where another instruction is executed. taken. As additional conditional indirect branch instructions 20 The instruction executed at address OX104 is a non-branch are encountered and their branches are taken, additional instruction, and therefore does not affect the IFFB, nor does trace messages with indirect branch information are sent any address information need to be transmitted. From from the processor to the debugger. When all of the IFFB address 0x104, execution proceeds to address 0x108, where bits are valid, e.g., a predetermined fullness threshold cri- another instruction is executed. teria is met, a trace history message 229 is generated that 25 The instruction executed at address 0x108 is a conditional includes the IFFB content and a corresponding TCODE direct branch instruction that is taken. Because the branch is value that indicates to the external debugger that the mes- taken, the value in the Index column is Zero (0) to indicate sage includes the IFFB information. Once the IFFB content that the conditional direct branch instruction at address has been captured for transmission as part of trace message, 0x108 corresponds to the first bit (BIT 0) of the IFFB, which it can be cleared, e.g. all flags are invalid. 30 is now set (1) to indicate the branch was taken. Because the The manner in which various trace messages are con- conditional branch was a direct branch, the branch destina structed and communicated to external debugger 103 will be tion is inherently known by the external debugger, e.g., as a further understood with reference to the exemplary pseudo- part of the source code, and there is no need to provide any code listing of Table 1, where each row corresponds to a additional destination address information. Thus, no trace particular instruction of an instruction flow. message is generated at this time, as indicated in the TRACE TABLE 1. instruction Trace MSG Label Address Type IFFB Index Comment Type event loop: Ox100 INSTR 8'bXXXXXXXX X Ox104 INSTR 8'bXXXXXXXX X 0x108 CBRDirect 8'bXXXXXXX1 O Taken None jmp table: Ox200 INSTR 8'bXXXXXXX1 X 0x204 CBRIndirect 8bXXXXXXO1 1 Not taken Ox2O8 INSTR 8"bxxxxxxO1 X 0x20C CBRIndirect 8bXXXXX001 2 Not taken Ox210 INSTR 8"bxxxxx001 X Ox214 CBRIndirect 8bXXXX1001 3 Taken AM(3) do something: Ox300 INSTR 8"bxxxx1001 X Ox304 CBRDirect 8"bxxx11OO1 4 Taken Ox3OC INSTR 8"bxxx11OO1 X Ox310 CBRIndirect 8bXX111001 5 Taken AM(5) Ox218 INSTR 8"bxx111001 X 0x21C CBRDirect 8"bx1111 OO1 6 Taken Ox1OC INSTR 8"bx1111001 X 0x110 CBRDirect 8b11111001 7 Taken HM Ox100 INSTR 8'bXXXXXXXX X A first column of Table 1, "Labels', identifies labels MSGTYPE column. The taken branch instruction at address associated with various address locations of the pseudocode. 0x108 results in a jump to label jmp table (address 0x200), A next column, labeled Address, indicates the address of a where execution continues. corresponding instruction. A next column, labeled Instruc- The instruction executed at address 0x200 is a non-branch tion Type, includes a mnemonic identifying various pseudo- instruction, and therefore does not affect the IFFB, nor does code instructions. A next column, labeled IFFB, indicates any address information need to be transmitted. From the IFFB contents based upon the instruction at the same row address 0x200, execution proceeds to address 0x204. being executed. A next column, labeled Index, indicates The instruction executed at address 0x204 is a conditional whether an instruction has a corresponding IFFB flag, where 65 indirect branch instruction that is not taken. Because the an "X" in the Index column indicates there is no correspond branch is not taken, the value in the Index column is one (1) ing IFFB flag for the instruction, and an integer in the Index to indicate that the conditional indirect branch at address 3 US 9,626,280 B2 10 0x204 corresponds to the second bit (BIT 1) of the IFFB, yielding the various results indicated in Table 1, in the which is now cleared (O) to indicate the branch was not manner described above, until reaching address 0x110. The taken. Instruction flow continues at the next instruction, instruction executed at address 0x110 is a conditional direct which is at address 0x208. Note that after an external branch that is taken, resulting in flow continuing at address debugger receives the IFFB information that it will be able 0x100. Because the branch is taken, the next bit (BIT 7) of to determine that the instruction at address 0x204 was not the IFFB is set, as also indicated by the value seven (7) in taken, and determine proper instruction flow to address the INDEX column. Because the branch instruction at Ox2O8. The instruction executed at address 0x208 is a non-branch address 0x110 is a direct branch, there is no need to provide instruction, and therefore does not affect the IFFB, nor does 10 additional destination information to the external debugger. any address information need to be transmitted. From However, because the IFFB is now full, e.g., all eight bits of address 0x208, execution proceeds to address 0x20C, where the IFFB are valid, the contents of the IFFB register is be another instruction is executed. provided to the external debugger using a trace history The instruction executed at address OX20C is a conditional message, which is represented by the designator "HM' in indirect branch instruction that is not taken. Because the 15 the column labeled Trace MESSAGE Type. In response, the branch is not taken, the next bit (BIT 2) of the IFFB is IFFB, is cleared, as represented by the designator cleared, and the value in the Index column has the value two 8'bXXXXXXXX in the IFFB column. (2) to indicate that the conditional indirect branch instruction Table 2 illustrates an exemplary pseudo code listing that corresponds to IFFB bit BIT 2. Flow continues with the is the same as that described with respect to Table 1, except instruction at address OX210, and no trace message is gen the branch instruction at address 0x110 is a conditional erated. indirect branch instruction that is taken, as opposed to a The instruction executed at address OX210 is a non-branch conditional direct branch instruction. As a result of the instruction, and therefore does not affect the IFFB, nor does conditional indirect branch instruction being taken at any address information need to be transmitted. From address OX110, a trace address message AMC7) is generated, address 0x210, execution proceeds to address 0x214, where 25 having a destination address of 0x100, as is the trace history another instruction is executed. message HM. In response to the IFFB buffer being filled. TABLE 2 instruction Trace Msg Label Address Type IFFB Index Comment Type event loop: Ox100 INSTR 8'bXXXXXXXX X Ox104 INSTR 8'bXXXXXXXX X 0x108 CBRDirect 8'bXXXXXXX1 O Taken None jmp table: Ox200 INSTR 8'bXXXXXXX1 X 0x204 CBRIndirect 8bXXXXXXO1 1 Not taken Ox2O8 INSTR 8"bxxxxxxO1 X 0x20C CBIindirect 8"bxxxxx001 2 Not taken Ox210 INSTR 8"bxxxxx001 X Ox214 CBRIndirect 8bXXXX1001 3 Taken AM(3) do something: Ox300 INSTR 8"bxxxx1001 X Ox304 CBRDirect 8"bxxx11OO1 4 Taken Ox3OC INSTR 8"bxxx11OO1 X Ox310 CBRIndirect 8bXX111001 5 Taken AM(5) Ox218 INSTR 8"bxx111001 X 0x21C CBRDirect 8"bx1111 OO1 6 Taken Ox1OC INSTR 8"bx1111001 X 0x110 CBIindirect 8'b11111 OO1 7 Taken HM, AMC7) Ox100 INSTR 8'bXXXXXXXX X The instruction executed at address OX214 is a conditional It will be appreciated, that the use of trace address indirect branch instruction that is taken, resulting in flow 50 messages having index values that reference specific IFFB continuing at address 0x300. Because the branch is taken, flags allows an external debugger to attribute destination the next bit (BIT 3) of the IFFB register is set, and the value address information of the trace address message to a in the Index column is three (3) to indicate that the condi particular branch instruction that is associated with the tional indirect branch instruction corresponds to IFFB bit indexed branch history bit (flag) identified, even when the BIT 3. Because the branch was an indirect branch, the IFFB flag information and the destination address informa branch destination cannot be determined by the external 55 tion are received at different times. Thus, it will be appre debugger without more information. Thus, a trace address ciated, that the trace address messages and trace history message with an INDEX identifying bit BIT 3 of the IFFB messages are generated independent of one another, e.g., will be generated and provided to the external debugger. trace history messages are generated in response to the IFFB Column Trace MSG Type includes a mnemonic AMC3) that being full, and trace address messages are generated in represents the trace address message, where "AM" indicates 60 response to an indirect branch being taken. It will also be a trace message includes an address, e.g., address 0x300, and appreciated that other types of trace messages can be cor "(3)" indicates that the trace address message is associated related to specific instructions by through the use of IFFB with BIT 3 of the IFFB. The taken branch from address flag indexes, as will be better understood with reference to 0X214 results in a jump to label do something (address the debug timestamp messages described in greater detail 0x300), where execution continues. 65 below. Execution of a particular sequence of instructions contin FIG. 4 illustrates a block diagram representing a trace ues to be executed, beginning at the target address 0x300, timestamp message 400 that includes a timestamp value 3 US 9,626,280 B2 11 12 (TIMESTAMP) that corresponds to particular a particular processing tasks, such as managing an IFFB and generation event. The event causing the timestamp to be generated can of trace messages to communicate the occurrence of the be identified in the trace timestamp message by a particular exception/interrupt. BTYPE (not shown) or TCODE. The instruction that was Block 503 represents tasks implemented by an exception/ executing at the time that the timestamp was generated can 5 interrupt processor that occur during the redirection of be communicated to an external debugger using an index instruction flow to an exception/interrupt handler, and vari value (INDEX) and an instruction/address increment value ous overhead tasks that are used to facilitate a return from (ICNT). In particular, the index value can identify a specific the exception/interrupt when a Return From Exception bit of the IFFB that corresponds to the last executed branch (RFE) instruction or a Return From Interrupt (RFI) instruc instruction prior to the interrupt occurring, and ICNT rep 10 tion is executed. As used herein, the term "RFEOI instruc resents the number of instructions/addresses that occurred tion' is intended to refer to one of either an RFE instruction between the identified last executed branch instruction and or an RFI instruction. when the timestamp event occurred. Therefore, because the Side block 513 indicates at least a portion of the various external debugger can correlate each specific bit of the IFFB tasks performed at block 503 in accordance with a particular to a particular source code instruction, the instruction being 15 embodiment, including: 1) pushing an address based on an executed when the timestamp was generated can be deter exceptional instruction onto a stack of the data processor, mined by counting forward a number of instructions/ad wherein the term "exceptional instruction" as used herein is dresses, ICNT, from the last executed branch instruction as intended to mean to the instruction that was being executed identified by the INDEX field of the timestamp message. at the time an exception/interrupt occurred; 2) determining The ability to associate a trace message with a specific the destination address of the exception/interrupt, e.g., the executed instruction by including an index value that iden first instruction of an exception/interrupt handler; and 3) tifies a particular IFFB flag, which in turn corresponds to a loading a program counter of the data processor with the particular instruction, allows for the debug module of data determined destination address. It will be appreciated that processor to completely fill the IFFB before generating a exception/interrupt handling can also perform additional trace history message to communicate its contents. This can 25 tasks that are associated with redirecting processing in be advantageous over other trace messaging techniques that response to an exception/interrupt not described herein. For provide branch history information and branch destination purposes of discussion, it is presumed herein that execution address information together, or in a fixed relationship to of the exceptional instruction is completed prior to process each other, in response to a conditional indirect branch being ing of the exception/interrupt, and that the address value taken. The ability to transmit full IFFBs, separate from trace 30 pushed onto the stack is the address of the instruction that address messages having destination address information for follows the exceptional instruction that is used to redirect taken branches can reduce the overall trace messaging flow back to the point of exception/interrupt upon receipt of bandwidth needed used to communicate information to an an RFEOI instruction, unless otherwise modified by the external debugger. exception/interrupt handler. By way of example, the use of trace messages having 35 The debug processing block 504 represents various debug index values as described above is used with the particular tasks implemented by a debug processor of the data proces embodiment of debug processing described below, which sor, in response to an exception/interrupt. Side block 514 handles exceptions/interrupts in a manner that can also indicates at least a portion of the various tasks performed at reduce the amount of trace message information. It will be block 504 in accordance with a particular embodiment, appreciated, however, that the exception/interrupt debug 40 including: 1) saving the address pushed on to the stack as a processing technique described below can also be used with predicted return address; 2) capturing the destination address debug systems that do not Support trace messages with determined by the exception/interrupt processor (see block indexes, as described above. 503); 3) determining address information of the exceptional FIGS. 5 and 6 are flow diagrams indicating a manner in instruction and the destination address to be included in a which exceptions and interrupts are handled by a data 45 trace message; 4) determining other trace message informa processor in accordance with a specific embodiment. As tion, including TCODE, BTYPE; 5) trace history buffer used herein, the term "exception/interrupt' is intended to handling, e.g., programming a corresponding flag of the refer to one of either an exception or an interrupt. The use IFFB, corresponding to the INDEX of a trace address of either the term "exception' or the term "interrupt by message; 6) generating and transmitting one or more trace itself is intended to refer specifically to an exception or an 50 messages providing exception/interrupt information, such as interrupt, respectively. The flow of FIG. 5 illustrates a AM (TCODE, INDEX, BTYPE, ICNT, ADDR), where, by particular embodiment of exception/interrupt processing way of example, INDEX and ICNT provide incremental that begins at block 501. At block 502, the exception/ address information that can be used by an external debug interrupt and debug processing portion of a data processor ger to identify the location where the exception interrupt waits for the occurrence of an exception/interrupt. When an 55 occurred, and ADDR provides direct address information exception/interrupt is detected, processing proceeds to identifying the address of the first instruction of an exception blocks 503 and 504, where exception/interrupt processing handler. and debug processing are handled, respectively. It will be It will be appreciated that additional tasks can also be appreciated that the exception and debug processing of performed by the debug processor at 503, for example, an blocks 503 and 504 can occur concurrently, e.g. by different 60 instruction indicator can be determined and communicated portions of a data processor, or, sequentially, e.g., using along with the trace address message that provides infor common resources of the data processor. Thus, an exception/ mation that can be used to determine whether or not execu interrupt processing portion of the data processor can imple tion of the exceptional instruction was completed in ment various tasks to facilitate a change of instruction flow response to the exception/interrupt. that results in the direction of instruction flow to the first 65 FIG. 6 is a flow diagram beginning at 601 that indicates instruction of an exception/handler, and a debug processing the manner in which a data processor handles various types portion of the data processor can implement various debug of instructions, including branch instructions, and RFEOI 3 US 9,626,280 B2 13 14 instructions, in accordance with a specific embodiment. At the actual and predicted return addresses. In one embodi block 602, the type of an executing instruction is determined ment, no history information is maintained indicating Flow proceeds from block 602 to block 612 in response to whether the predicted and actual addresses of particular the executing instruction being an instruction other than a RFEOI instructions resulted in a match or a mismatch. branch or RFEOI instruction. At block 612 normal process- 5 By virtue of receiving the trace address message gener ing continues, which can include various debug processing ated at block 604, the external debugger will know that the (not shown), before returning to block 602. return address of the RFEOI cannot be determined from the Flow proceeds to from block 602 to block 611 in response previously provided information, which was based upon the to the executing instruction being a branch instruction. At location of the interrupted address, and will instead use the block 611, the data processor handles branch debug pro- 10 address information generated at block 604 to determine the cessing in a predefined manner. For example, the specific return address, and reconstruct instruction flow. Conversely, embodiment of handling branch instructions as described when the external debugger does not receive a trace address above can be implemented at block 611. In an alternate message that corresponds to the RFEOI instruction, the embodiment, debug processing of branch instructions can be external debugger knows that the previously received return handled in other manners. 15 address information is correct, based on the interrupted Flow proceeds to from block 602 to block 603 in response instruction, and will reconstruct the instruction flow based to the executing instruction being an RFEOI instruction. At upon the that information. block 603, a predicted return address of the RFEOI instruc Note that according to one embodiment, IFFB processing tion is determined and compared to the actual return address at block 604 and at block 605 both result in a flag of the that is taken in response to the RFEOI instruction. One way 20 IFFB that corresponds to the RFEOI instruction being of determining the predicted return address is to use the programmed to a common value. For example, the bit of the address that was saved by the debugger at block 504 (FIG. IFFB that corresponds to the RFEOI instruction can be set 5), which was the address pushed onto the Stack in response at both block 604 and at block 605. Note that according to to the exception/interrupt. It will be appreciated, that this the present embodiment, there is no need to maintain a saved value is a predicted value in that the corresponding 25 match/mis-match indicator for each occurrence of an excep value that was originally pushed onto the stack may have tion/interrupt. changed. For example, the exception/interrupt handler could FIG. 7 illustrates a block diagram including a line 710 that have changed the original return address pushed onto the represents a plurality of instructions in linear address space stack. having a particular instruction flow during which an excep When the address pushed onto the stack at block 504 has 30 tion/interrupt occurs. In particular, as instructions 710 are not been modified, the predicted return address of the executed, conditional branch instructions, can either be RFEOI instruction will match the actual return address of taken, or not taken, to another memory address as previously the RFEOI instruction, and flow proceeds from block 603 to described. Thus, as instruction flow proceeds along line 710, block 605, otherwise the predicted return address of the each encountered branch instruction corresponds to a next RFEOI instruction will not match the actual return address, 35 available location in the IFFB where information is stored to and flow proceeds to block 604. indicate whether the branch was taken or not. Note that an At block 605, in response to the predicted and actual IFFB 729 is illustrated at FIG. 7 to illustrate the manner in RFEOI addresses matching, various debug processing is which IFFB flags are updated. performed that includes IFFB processing, e.g., updating a During operation, instructions are executed by a data flag of the IFFB that corresponds to the RFEOI instruction, 40 processor until branch instruction 711 is reached, which by and transmission of the IFFB content when the IFFB is full. way of example is a conditional indirect branch instruction. Note, however, that there is no need to send a trace address In the example shown, it is determined that branch BR1 is message based solely on the fact that an RFEOI instruction to be taken to an instruction 714 at destination address was executed, because the return address information pro ADDR1. Thus, the first flag (e.g., bit 0) of the IFFB 729 is vided to the external debugger in the trace address message 45 set, assuming the IFFB 729 register was empty, and the sent at block 504 was correct (e.g., the previously transmit resulting destination address (ADDR1) of the conditional ted INDEX and ICNT information correctly identified the branch is transmitted using a trace address message repre return location based upon instruction that was executing sented in FIG. 7 by the indicator AM(TCODE, INDEX, when the interrupt occurred). Thus the external debugger BTYPE, ADDR1), as previously described. does not need any additional information to reconstruct the 50 According to an embodiment, because register IFFB 729 instruction flow. is not full subsequent to the conditional branch BR1 being If at block 603 it is determined that predicted return taken, no trace message will be sent at this time to commu address does not match the actual return address, flow nicate its contents. It will be appreciated however, that proceeds to block 604 for debug processing. At block 604, according to an alternate embodiment, valid flags of the various debug processing is performed that includes IFFB 55 register IFFB, e.g., those flags that correspond to executed processing, and generating a trace address message that branch instructions or other events, are transmitted in provides address information identifying the actual return response to a conditional branch being taken, as opposed to address of the RFEOI. Various processing is indicated at side waiting until the IFFB is full. In this embodiment, the trace block 624 that indicates a trace address message can be address message that communicates the destination address generated that includes a TCODE, a BTYPE, address infor- 60 may not need to include the index value. mation, and other information. The address information can Instruction code execution continues from instruction 714 be incremental address information or direct address infor and arrives at a instruction 715 when an exception/interrupt mation. occurs. During exception/interrupt processing, the address In addition, a history bit, e.g. a flag of the IFFB, is of the exceptional instruction, for example, is pushed onto a programmed that corresponds to the RFEOI instruction. 65 stack of the data processor, such as stack 119 (FIG. 1), the Note that the value of the history bit is independent with destination address is determined, e.g., ADDR3 in the pres respect to whether a match or mismatch occurred between ent example, and loaded into the data processor's program 3 US 9,626,280 B2 15 16 counter to cause instruction flow to proceed at instruction to an exception/interrupt event will be better understood 721, as indicated by transition line 720. with reference to the exemplary pseudocode listing of Table In response to the exception/interrupt, a debug processor 3, which has the same format as Table 1. Therefore, as performs a variety of tasks, such as described at block 504 illustrated, the pseudocode of Table 3 from address OX100 (FIG. 5). For example, debug processing results in genera 5 through address OX304 executes in the same manner as that tion of the trace address message illustrated in FIG. 7 previously described with respect to Table 1. TABLE 3 Instruction Trace MSG Label Address Type IFFB Index Comment Type event loop: Ox100 INSTR 8'bXXXXXXXX X Ox104 INSTR 8'bXXXXXXXX X 0x108 CBRdirect 8'bXXXXXXX1 O Taken None jmp table: Ox200 INSTR 8"bxXxxxxx1 X 0x204 CBRindirect 8"bXXXXXXO1 1 Not taken Ox208 INSTR 8'bXXXXXX01 X 0x20C CBRindirect 8"bXXXXX001 2 Not taken Ox210 INSTR 8'bXXXXX001 X 0x214 CBRindirect 8"bXXXX1001 3 Taken AM(INDEX = 3) do something: Ox300 INSTR 8'bXXXX1001 X 0x304 CBRdirect 8'bXXX11001 4 Taken Ox3OC INSTR 8'bXX111001 5 E/I Occurs: AM (TCODE, BTYPE, Push 0x310 INDEX = 5, ICNT, onto stack; ADDRe?i handler) load 0x500 into PC efi handler OxSOO INSTR 8'bXX111001 X AM 0x504 CBRindirect 8"bxO111001 6 Not taken 0x508 CBRindirect 8b01111001 7 Not taken HM(TCODE, IFFB) 0x50C CBRindirect 8"bXXXXXXX0 O Not taken OxS10 INSTR 8'bXXXXXXX0 X OxS14 RFEOI 8'bXXXXXX10 1 Predicted No Trace and actual message sent return addresses match end handler Ox310 INSTR 8'bXXXXXX10 X represented by the mnemonic AM (TCODE, INDEX, 35 During execution of the instruction at address 0x30C, BTYPE, ICNT, ADDR3), where INDEX and ICNT repre however, an exception/interrupt occurs, which results in sent address information that an external debugger can use exception processing pushing the return address, OX310, to determine the exceptional instruction 715, and ADDR3 onto the stack of the data processor, and loading a destina provides address information that allows the external debug 40 tion address of the exception/interrupt into the program ger to determine the destination address of the exception/ counter to redirect instruction flow. Also in response to the interrupt handler. In addition, the occurrence of the excep exception/interrupt, a debug processor will: 1) set the next tion/interrupt causes a next bit, BIT 0, of the IFFB to be set. available bit (BIT 5) of the IFFB, as indicated by the The exception/interrupt handler instructions continue to numeral 5 in the INDEX column, which corresponds to the be executed, including the conditional indirect branch 45 occurrence of the exception/interrupt; 2) save the address of instruction 722, which when taken results in a change of the exceptional instruction or the next sequential address for address flow to instruction 723. The taken branch instruction use as a predicted return address (FIG. 2); 3) generate a trace 722 results a trace address message being generated, as address message represented by the pneumonic AM represented by the mnemonic AM(TCODE, INDEX, (TCODE, BTYPE, INDEX=5, ICNT, ADDRe?i handler), BTYPE, ICNT). Instruction flow continues until instruction 50 where the TCODE or BTYPE indicate that the message is 724, which is an RFEOI instruction. for an exception/interrupt, INDEX=5 indicates that bit 5 of In response to executing the RFEOI instruction, the debug the IFFB corresponds to the exception/interrupt, and ADDR module of the integrated circuit will compare the actual efi handler indicates the address information identifying return address, e.g., the return address value loaded into the the first address of the exception/interrupt handler is pro program counter of the data processor, with the predicted 55 vided. Note that the IFFB is not full and therefore not yet return address, e.g., the address of the exceptional instruc transmitted via a trace history message. tion 715 which was previously saved. If the actual and The first instruction of the exception handler, at address predicted addresses match, as occurs when instruction flow 0x500, is a non-branch instruction, and therefore does not follows dashed transition line 728, no address message is affect the IFFB, nor does any address information need to be sent to the external debugger. If the actual and predicted 60 transmitted. From address 0x500, execution proceeds to instructions do not match, as occurs when instruction flow address 0x504, where another instruction is executed. follows dashed transition line 729, and a trace address The instruction executed at address 0x504 is a conditional message represented by the mnemonic AM (TCODE, indirect branch instruction that is not taken. Because the BTYPE, ADDR4) is generated, wherein ADDR4 is infor branch is not taken, the next bit (BIT 6) of the IFFB is mation identifying the actual taken address. 65 cleared, which allows the external debugger to know that the The manner in which various trace messages are gener instruction flow continues at the next instruction, which is at ated and communicated to an external debugger in response address 0x508, and no trace address message is generated. 3 US 9,626,280 B2 17 18 The instruction executed at address 0x508 is a conditional 0x510 is a non-branch instruction, and therefore does not indirect branch instruction that is not taken. Because the affect the IFFB, nor does any address information need to be branch is not taken, the next bit (BIT 7) of the IFFB is transmitted. cleared, which allows the external debugger to know that the Table 4 lists a pseudocode that is similar to a portion of instruction flow continues at the next instruction and no the pseudocode of table 3, except that the actual return trace address message is generated. However, a trace history address and predicted return address of the RFEOI instruc message is generated as the IFFB is now full. The IFFB is tion do not match. Therefore, the results of executing the cleared, and instruction flow continues at address 0x50C. pseudocode of Table 4 from address 0x200 through 0x510 The instruction executed at address 0x50C is an indirect are the same as described with respect to Table 3. However, branch instruction that is not taken. Because the branch is 10 the RFEOI instruction executed at address OX514 of Table 4 not taken, the next bit (BIT 0) of the IFFB is cleared, which has resulted in a return address from the exception/interrupt allows the external debugger to know that the instruction that is different than the predicted, or expected, return flow continues at the next instruction, which is at address address. This is detected by the debug processing module of OX510, and no trace address message is generated. the data processor, e.g., by comparing a value Stored at Instruction 0x510 is a non-branch instruction, and there- 15 memory 120 to the value loaded in the program counter. As fore does not affect the IFFB, nor does any address infor- a result, a trace address message is generated having the mation need to be transmitted. From address 0x510, execu- actual return address information that is needed by the tion proceeds to address 0x514, where another instruction is debugger. Thus, Table 4 indicates that a trace address executed. message represented by the mnemonic AM(TCODE, The instruction executed at address 0x514 is an RFEOI 20 BTYPE, INDEX=1, ADDRend handler) is sent based instruction that causes the instruction flow to be redirected upon execution of the RFEOI instruction at address 0x514. TABLE 4 Instruction Label Address Type IFFB Index Comment Trace MSG Type jmp table: Ox200 INSTR 8"bxXxxxxx1 X 0x204 CBRindirect 8"bXXXXXXO1 1 Not taken Ox208 INSTR 8'bXXXXXXO1 X 0x20C CBRindirect 8"bXXXXX001 2 Not taken Ox210 INSTR 8'bXXXXX001 X 0x214 CBRindirect 8"bXXXX1001 3 Taken AM(INDEX = 3) do something: Ox300 INSTR 8'bXXXX1001 X 0x304 CBRdirect 8'bXXX11001 4 Taken Ox3OC INSTR 8'bXX111001 5 E/I Occurs: AM (TCODE, BTYPE, Push 0x310 INDEX = 5, ICNT, onto stack; ADDRe?i handler) load 0x500 into PC efi handler OxSOO INSTR 8'bXX111001 X AM 0x504 CBRindirect 8"bxO111001 6 Not taken 0x508 CBRindirect 8b01111001 7 Not taken HM(TCODE, IFFB) 0x50C CBRindirect 8"bXXXXXXX0 O Not taken OxS10 INSTR 8'bXXXXXXX0 X OxS14 RFEOI 8'bXXXXXX10 1 Predicted AM (TCODE, BTYPE, and actual INDEX = 1, return addresses ADDRend handler) do not match end handler Ox710 INSTR 8'bXXXXXX10 X from the exception/interrupt handler to the instruction fol The initial pseudocode of Table 5 is the same as the initial lowing the exceptional instruction, which is at address pseudocode of Table 3. Therefore, from address 0x100 0x30C. Because a change of flow occurs, the next bit (BIT so through address 0x304 the pseudocode of Table 5 imple 1) of the IFFB is set, which indicates that an instruction ments the same operation as the psuedocode of Table 3, but redirection has occurred. Because the RFEOI instruction is handled differently by the debug processor. - In particular, d the i ion fl be redi d to th dicted instead of generating messages with index values, and cause t e 1nStruct1On ow to be redirected to the predicte completely filling the IFFB before generating a trace history instruction, e.g., the predicted and actual return address ss message, the embodiment of Table 5 maintains a variable matched, as evidenced in Table 3 by the instruction 0x310 size IFFB that is transmitted each time a trace address being the instruction executed after the RFEOI instruction at message is sent for a branch instruction or for an exception/ address OX514, no trace address message is sent. Instruction interrupt event. TABLE 5 Instruction Label Address Type IFFB Comment Trace MSG Type event loop: Ox1OO INSTR 1b1 Ox104 INSTR 0x108 CBRdirect Taken None 3 US 9,626,280 B2 19 20 TABLE 5-continued instruction Label Address Type IFFB Comment Trace MSG Type jmp table: Ox200 INSTR 2"b11 0x204 CBRindirect 3b110 Not taken Ox2O8 INSTR 3b110 0x20C CBRindirect 4"b1100 Not taken Ox210 INSTR 4'b1100 Ox214 CBRindirect S'b11001 Taken AHM(TCODE, BTYPE, ADDR, HIST = 4b1001) do something: 0x300 INSTR 1'b Ox304 CBRdirect 2"b11 Taken Ox3OC INSTR 3b111 E/I Occurs AHM(TCODE, BTYPE, ICNT, ADDR, HIST = 2b11) efi handler OxSOO INSTR 1'b 0x504 CBRindirect 2"b10 Not taken 0x508 CBRindirect 3b100 Not taken 0x50C CBRindirect 4"b1000 Not taken OxS10 INSTR 4'b1 OOO Ox514 RFEOI Sb.1 OOO1 end handler Ox310 INSTR 1'b For example, at address 0x100 there are no flags stored in mnemonic AHM(TCODE, BTYPE, ICNT, ADDR, HIST), the IFFB buffer, as represented by the value 1'b1, where the where ICNT indicates the number of instruction executed portion "1'b' of the term "1'b1" indicates that the term between the last branch instruction and the exception/inter represents one binary bit, which follows the portion "1"b'. 25 rupt, which allows the external debugger to determine where Thus, the term 1"b1 represents a single bit value of "1". the exception/interrupt happened, and HIST represents which corresponds to a stop bit. At instruction 0x108, information needed to report the two IFFB flags currently however, a set flag has been added to the IFFB, as repre stored in the IFFB, e.g., 211. sented by the value 2"b11, based upon execution of the direct Instruction flow continues at instruction 0x500, with the branch instruction at address OX100. Because the instruction 30 IFFB being updated as described above, until the RFEOI flow of a direct branch instruction can be predicted by an instruction at address 0x514, at which time a set flag is added external debugger, no trace address message is generated. to the IFFB, as indicated by the value 5'b10001, that Instruction flow continues as described previously, until corresponds to the RFEOI instruction. Furthermore, the address 0x204, which is a conditional indirect branch debug processor determines that the actual return address instruction that is not taken. This results in a cleared flag 35 from the RFEOI instruction matched the predicted return being added to the IFFB, as represented by the value 3b110. address, and therefore does not generate a trace address/ Because the instruction flow following a not taken condi history message, as the external debugger can determine the tional indirect branch can be predicted by an external return address from the ICNT value that was previously debugger, no trace address message is generated. generated in response to the interrupt. Thus, the debug At address OX20C another cleared bit is added to the IFFB 40 processor does not need to transmit either destination to indicate the conditional indirect branch was not taken address information or the contents of the IFFB at this time. resulting in the IFFB value 4'b1100. At address 0x214 a It will be appreciated, however, that if the predicted return conditional indirect branch is taken, which results in a set address did not match the actual return address, that the flag being added to the IFFB, as represented by the IFFB debug process would generate a trace address message value 5'b11001. Furthermore, because the external debugger 45 represented by the mnemonic AM(TCODE, BTYPE, has no way of knowing the destination address of a taken ADDR, HIST=5'b10001) to convey the taken return address. indirect branch, a trace address/history message is shown to FIG. 8 is a flow diagram illustrating a method for deter be generated that provides address information of the des mining program trace information at the external debugger tination instruction, and the contents of the IFFB. The trace 103, based upon messages using index values as described address/history message is represented by the mnemonic 50 herein. Method 800 begins in block 801. From block 801, AHM(TCODE, BTYPE, ADDR, HIST), where HIST rep method 800 continues to decision block 802. In decision resents information needed to report the four IFFB flags, block 802, a decision is made as to whether or not a message represented by the value 4'b1001, of the IFFB. has been received. If not, method 800 returns to decision Instruction flow continues at instruction 0x300 following block 802. If so, method 800 continues to decision block the taken branch. The contents of IFFB have been cleared in 55 803. In decision block 803, a decision is made as to whether response to the branch instruction at address OX214 having or not the message includes indirect branch information, been taken. which can be indicated by a particular TCODE or BYTPE Instruction flow continues, with the IFFB being updated value. If so, method 800 continues to block 804. In block as described above, until instruction 0x30C, during which an 804, indirect branch information is stored and used by the execution/interrupt occurs. In response, a set flag is added to 60 external debugger to determine instruction flow. From block the IFFB, as indicated by the value 3'b111. Furthermore, 804, method 800 returns to decision block 802. If a decision because the external debugger has no way of knowing that is made in decision block 803 that the message does not the exception/interrupt occurred, a trace address message is include indirect branch information, method 800 continues generated that reports 1) the occurrence of the interrupt, e.g., to decision block 805. In decision block 805, a decision is via a particular BTYPE or TCODE value, 2) the address of 65 made as to whether or not the message includes IFFB the destination instruction, and 3) the contents of the IFFB. contents. If not, method 800 returns to decision block 802. The trace address message reported is illustrated to have the If so, method 800 continues to block 806. 3 US 9,626,280 B2 21 22 In block 806, flags of the IFFB buffer that are cleared used actual return address in response to determining the mis to determine corresponding branches in the debugger's copy match, otherwise, not generating the trace address message of the instruction code as not having been taken, and flags identifying the actual return address in response to deter that are set are used to determine corresponding branches in mining match. the debugger's copy of the instruction code as having been In an embodiment of the first aspect, the predicted return taken. From block 806, method 800 continues to block 808. address is based upon an address of an exceptional instruc In block 808, stored indirect branch information is retrieved, tion. In a particular embodiment, the predicted return and flow proceeds to block 808, where indirect branch address is the same as the address of the exceptional information is associated with branch instructions that are instruction that was being executed. In a further particular determined as having been taken. From block 808, method 10 embodiment, the predicted return address is an address of an 800 continues to block 809. In block 809, a representation of instruction after the exceptional instruction. code execution is constructed in the debugger. From block In another embodiment of the first aspect, the method 809, method 800 continues to block 810, where it ends. includes, prior to determining the match or mismatch, gen Although the invention is described herein with reference erating a second trace address message in response to to specific embodiments, various modifications and changes 15 can be made without departing from the scope of the present occurrence of the exception/interrupt, the second trace invention as set forth in the claims below. Accordingly, the address message comprising information from which the specification and figures are to be regarded in an illustrative predicted return address can be determined. In a particular rather than a restrictive sense, and all such modifications are embodiment, the information includes an indicator whether intended to be included within the scope of the present execution of the exceptional instruction was completed. In invention. an even more particular embodiment, the method includes in For example, debugger 103 may obtain the values of any response to the instruction type indicating the exceptional or all of registers 110-115, for example, by receiving trace instruction is of a first type the predicted address has a first messages via connection 108, which may, for example, be a value, and in response to the instruction type indicating the serial port or a parallel port for conveying trace messages. 25 exceptional instruction is of a second type the predicted For example, data processor 101 may provide the values of address has a second value. any or all of registers 110-115 to debugger 103. Alterna In yet another embodiment of the first aspect, the method tively, a Joint Test Access Group (JTAG) connection allow includes, in response to the exception/interrupt, generating a ing debugger 103 to access a memory map of data processor trace history message having a first indicator corresponding 101, may allow access to memory 102, registers 110-115, 30 to the exception/interrupt, wherein the trace history message memory external to data processor 101, and the like. In such is generated independent as to a fullness of a history buffer case, debug module 116 may store values that may otherwise comprising the first indicator. In a particular embodiment, be stored in registers 110-115 at any memory locations the generated trace history message further comprises a accessible to debug module 116 and debugger 103. Debug second indicator corresponding to execution of a branch ger may use Such values to trace program code instructions 35 instruction. being executed on data processor 101. Such tracing may be In still another embodiment of the first aspect, the method performed in real-time (i.e., as the program code instructions includes, in response to the exception/interrupt, adding a are being executed by execution units 117 of data processor first indicator corresponding to the exception/interrupt to a 101). Examples of operations that may be performed in history buffer, wherein a trace history message comprising real-time include the storing of values in registers 110-115 of 40 the first indicator is generated in response to the history debug module 116, the transmission of trace messages from buffer meeting a fullness criteria. In still yet another further debug module 116 to debugger 103, the analysis of trace embodiment of the first aspect, the method includes assert messages at debugger 103, and the like. ing a history indicator in response to the RFEOI instruction In other embodiments, instruction flow history flag buffer being executed, wherein the history indicator is asserted register 114 may have additional bits. For example, addi 45 independent of determining match or mismatch. In even tional bits, may be stored in instruction flow history flag another embodiment of the first aspect, the method includes buffer register 114 by shifting bits already stored in instruc no history information is maintained indicating whether the tion flow history flag buffer register 114 away from an end match or mismatch was detected. of instruction flow history flag buffer register 114 at which In a second aspect of the disclosure, a data processing the additional bit or bits is to be stored and storing the 50 system can include a data processor core, and a debug additional bit or bits at that end of instruction flow history module coupled to the data processor core, the debug flag buffer register 114. module configured to determine if a predicted return address In another embodiment, a trace address message that of an Return From Exception or Return from Interrupt communicates the occurrence of an exception/interrupt can (RFEOI) instruction results in a match or a mismatch with include an instruction type field that includes an indicator as 55 an actual return address of the RFEOI instruction, and to to whether execution of the exceptional instruction com send a trace address message identifying the actual return pleted or aborted. This information can be used by the address in response to determining mismatch, otherwise, not debugger to determine proper instruction flow in response to sending the trace address message in response to determin an RFEOI instruction. ing match. In a first aspect of the present disclosure, a method can 60 In an embodiment of the second aspect, the debug module include, in response to an occurrence of an exception/ determines the predicted return address based upon an interrupt, executing an exception/interrupt handler, deter address of an exceptional instruction. In another embodi mining if a predicted return address of a Return From ment of the first aspect, the debug module is further con Exception Or Interrupt (RFEOI) instruction of the excep figured to, prior to determining the match or mismatch, tion/interrupt handler results in a match or a mismatch with 65 generate a second trace address message in response to an actual return address of the RFEOI instruction, and occurrence of an exception/interrupt, the second trace generating a first trace address message identifying the address message comprising information from which the 3 US 9,626,280 B2 23 24 predicted return address can be determined. In a particular 2. The method of claim 1, wherein the predicted return embodiment, the information includes an instruction type of address is based upon an address of an exceptional instruc an exceptional instruction. tion. In yet another embodiment of the second aspect, the 3. The method of claim 2, wherein the predicted address debug module is further configured to, in response to an 5 is the same as the address of the exceptional instruction that exception/interrupt corresponding the RFEOI instruction, was being executed. generate a trace history message having a first indicator 4. The method of claim 2, wherein the predicted address corresponding to the exception/interrupt instruction inde is an pendent as to fullness of a trace history buffer comprising the tion. address of an instruction after the exceptional instruc first indicator. In still another particular embodiment, the 10 debug module is further configured to, in response to an 5. The method of claim 1 further comprising: exception/interrupt corresponding the RFEOI instruction, prior to determining the match or mismatch, generating a add a first indicator corresponding to the exception/interrupt second trace address message in response to occurrence to a history buffer, and to generate a trace history message of the exception/interrupt, the second trace address based upon the history buffer in response to the history 15 message comprising information from which the pre buffer meeting a fullness criteria. dicted return address can be determined. In a third aspect of the present disclosure, a method can 6. The method of claim 5, wherein the information include determining that a Return From Exception Or Inter includes an indicator whether execution of the exceptional rupt (RFEOI) instruction has been executed at a data pro instruction was completed. cessor, and in response to determining that a first trace * 7. The method of claim 6, wherein in response to the address message has been received corresponding to the instruction type indicating the exceptional instruction is of a RFEOI instruction, reporting instruction flow subsequent to the RFEOI instruction as continuing at a first return address first type the predicted address has a first value, and in response to the instruction type indicating the exceptional provided as part of the first trace address message, other wise, in response to determining that a first trace address 25 instruction second value. is of a second type the predicted address has a message has not been received corresponding to the RFEOI instruction, reporting instruction flow Subsequent to the 8. The method of claim 1 further comprising: RFEOI instruction as continuing at a second return address in response to the exception/interrupt, generating a trace that is based upon information received prior to execution of history message having a first indicator corresponding the RFEOI instruction. 30 to the exception/interrupt, wherein the trace history In an embodiment of the third aspect, the method includes message is generated independent as to a fullness of a receiving a second trace address message providing the history buffer comprising the first indicator. second return address, the second trace address message 9. The method of claim 8, wherein the generated trace received in response to an occurrence of an exception/ history message further comprises a second indicator cor interrupt event, and the second return address based upon the responding to execution of a branch instruction. address of an exceptional instruction. 10. The method of claim 1 further comprising: Those skilled in the art will recognize that boundaries between the functionality of the above described operations in response to the exception/interrupt, adding a first are merely illustrative. The functionality of multiple opera indicator corresponding to the exception/interrupt to a tions may be combined into a single operation, and/or the 40 history buffer, wherein a trace history message com functionality of a single operation may be distributed in prising the first indicator is generated in response to the additional operations. Moreover, alternative embodiments history buffer meeting a fullness criteria. may include multiple instances of a particular operation, and 11. The method of claim 1 further comprising: the order of operations may be altered in various other asserting a history indicator in response to the RFEOI embodiments. 45 instruction being executed, wherein the history indica Benefits, other advantages, and solutions to problems tor is asserted independent of determining match or have been described above with regard to specific embodi mismatch. ments. However, the benefits, advantages, solutions to prob lems, and any feature(s) that may cause any benefit, advan tion is The 12. method of claim 1, wherein no history informa tage, or Solution to occur or become more pronounced are 50 was detected. indicating whether the match or mismatch maintained not to be construed as a critical, required, or essential feature of any or all the claims. 13. A data processing system comprising: a data processor core; and What is claimed is: a debug module coupled to the data processor core, the 1. A method comprising: 55 debug module configured in response to an occurrence of an exception/interrupt, to determine if a predicted return address of an Return executing an exception/interrupt handler, From Exception or Return from Interrupt (RFEOI) determining if a predicted return address of a Return From instruction results in a match or a mismatch with an Exception Or Interrupt (RFEOI) instruction of the 60 actual return address of the RFEOI instruction, and exception/interrupt handler results in a match or a mismatch with an actual return address of the RFEOI to send a trace address message identifying the actual instruction; and return address in response to determining mismatch, generating a first trace address message identifying the otherwise, not sending the trace address message in actual return address in response to determining the response to determining match. mismatch, otherwise, not generating the trace address 65 14. The data processing system of claim 13, wherein message identifying the actual return address in debug module determines the predicted return address based response to determining match. upon an address of an exceptional instruction. 3 US 9,626,280 B2 25 26 15. The data processing system of claim 13, wherein the 19. A method comprising: debug module is further configured to, prior to determining determining that a Return From Exception Or Interrupt the match or mismatch, generate a second trace address (RFEOI) instruction has been executed at a data pro message in response to occurrence of an exception/interrupt, ceSSOr, in response to determining that a first trace address the second trace address message comprising information 5 message has been received corresponding to the RFEOI from which the predicted return address can be determined. instruction, reporting instruction flow subsequent to the 16. The data processing system of claim 15, wherein the RFEOI instruction as continuing at a first return address information includes an instruction type of an exceptional provided as part of the first trace address message, instruction. 17. The data processing system of claim 13, wherein the 10 otherwise, in response to determining that a first trace debug module is further configured to, in response to an address message has not been received corresponding exception/interrupt corresponding the RFEOI instruction, to the RFEOI instruction, reporting instruction flow generate a trace history message having a first indicator Subsequent to the RFEOI instruction as continuing at a corresponding to the exception/interrupt instruction inde second return address that is based upon information pendent as to fullness of a trace history buffer comprising the 15 received prior to execution of the RFEOI instruction. first indicator. 20. The method of claim 19 further comprising: 18. The data processing system of claim 13, wherein the receiving a second trace address message providing the debug module is further configured to, in response to an second return address, the second trace address mes exception/interrupt corresponding the RFEOI instruction, Sage received in response to an occurrence of an add a first indicator corresponding to the exception/interrupt exception/interrupt event, and the second return to a history buffer, and to generate a trace history message address based upon the address of an exceptional based upon the history buffer in response to the history instruction. buffer meeting a fullness criteria.