Bicameral LLC v. NXP USA, Inc. et al

Western District of Texas, txwd-6:2018-cv-00294

Exhibit Kheyfits Ex. 7

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1 Kheyfits Declaration Exhibit 7 1 THE COMMISSIONER OF PATENTS AND TRADEMARKS Sehington, D.C. 20231 04/22/98 Asmitted herewith for filing is the patent application of II Ventor(s): Subhash C. Roy, Paul Hembrook, Eugene L. Parrella and Richard Mariano .1 ll For: REAL TIME DEBUGGER INTERFACE FOR EMBEDDED SYSTEMS Enclosed are: | X | 2 sheets of drawings. X Assignment Recordation Sheet Assi * Assignment of the Invention to TranSwitch Corporation 2 verified statements to establish small entity status under 2 yerified, statements to estab 37 CFR 1.9 and 37 CFR 1.27. A Declaration and Power of Attorney document. U Preliminary Amendment and Remarks The filing fee has been calculated as shown below: SMALL ENTITY ! LARGE ENTITY RATE FEE FOR NO. FILED NO. EXTRA BASIC FEE TOTAL CLAIMS 25-20 INDEP CLAIMS I 3 - 3 1 0 MULT. DEPENDENT CLAIMS PRESENTED $ 395 55 OR | RATE FEE $ 790 | x 22 198 x 82 +270 X 11 x 41 +135 011 TOTAL $450 TOTAL $988 U Please charge my Deposit Account No. - - in the amount of • A duplicate copy of this sheet is enclosed. to cover the filing / assignment A check in the amount of $490.00 recordation fee is enclosed. The Commissioner is hereby authorized to charge payment of the following fees associated with this communication or credit any overpayment to Deposit Account No.07-1732. A duplicate copy of this sheet is enclosed. Any additional filing fees required under 37 CFR 1.16. D Any patent application processing fees under 37 CFR 1.17. The Commissioner is hereby authorized to charge payment of the following fees during the pendency of this application or credit any overpayment to Deposit Account No.-, A duplicate copy of this sheet is enclosed. Any patent application processing fees under 37 CFR 1.17. U The issue fee set in 37 CFR 1.18 at or before mailing of the Notice of Allowance, pursuant to 37 CFR 1.311(b). 65 Woods End Road Stamford, CT 06905 (203) 329-1160 Land Tenue David P. Gordon Reg. No. 29,995 BC_GEN_0000147 1 TRA-040 2 executed by the processor was an immediate jump, a jump to register, or a branch taken. In addition, the three bit output will indicate whether execution of the instruction resulted in an exception. By recording this three bit output over time, and comparing it to the actual instructions listed in the program code, important debugging information is obtained about a program which was running in real time. 7 According to a preferred embodiment of the invention, a second decoder and an event history buffer are coupled to the cause register of the sequencer of the processor. In particular, the second decoder is coupled to the enable input of the history buffer and the cause register is coupled to the data input of the history buffer. The second decoder decodes the contents of the cause register and enables the history buffer whenever the contents of the cause register indicates an exception, a jump register instruction, or a change in the status of an interrupt line. Whenever the history buffer is enabled, information from the cause register and the program counter is loaded into the 20 buffer. By recording the contents of the history buffer over time, and comparing the information to the actual program code, 22 additional important debugging information is obtained about a 23 program which was running in real time. According to this 24 preferred embodiment of the invention, the seventh condition - 7 - BC_GEN_0000156 1 TRA-040 1 2 3 indicated by the three bit output of the first decoder is whether an exception was encountered without writing to the history buffer. 6 7 8 According to the presently preferred embodiment, each entry in the event history buffer is forty-four bits. Each forty-four bit entry in the history buffer includes the current sixteen bit time stamp, twenty three bits from certain fields of the cause register or program counter, one bit indicating whether the entry is related to a jump or an exception, two bits identifying the processor number (in a multiprocessor system), one bit identifying whether the history buffer has overflowed, and a time stamp rollover bit. The history buffer preferably has a depth of at least sixteen entries. An exemplary implementation of the debugging interface is embodied on an ASIC chip having three processors. Each processor is provided with two decoders as described above and a single 19 event history buffer is provided on the chip. Nine pins on the chip are used to provide access to the three bit outputs of each first decoder. Three pins on the chip provide serial access (data, clock, and enable) to the contents of the event history 23 buffer. These twelve pins on the chip allow a diagnostic device 24 to be coupled to the chip during real time operations without 20 - 8 - BC_GEN_0000157 1 TRA-040 1 2 interfering with the operation of the chip. The outputs of the first decoders and the contents of the event history buffer can be recorded over time by the diagnostic device to provide a real time record of the processing events occurring in the chip during real time. This real time record taken together with knowledge of the program code being executed provides a true picture of the 6 processors' execution sequence in real time and thereby expedite debugging of code. 0672O Hout - S60 C 0 v Additional objects and advantages of the invention will become apparent to those skilled in the art upon reference to the detailed description taken in conjunction with the provided figures. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic block diagram of an exemplary implementation of a real time debugger interface according to the invention; and 19 20 Figure 2 is a schematic block diagram of a debugging system 22 coupled to a chip embodying a real time debugger interface 23 according to the invention. - 9 - BC_GEN_0000158 1 TRA-040 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 4 5 6 Referring now to Figures 1, an exemplary ASIC chip 10 incorporating a debugger interface according to the invention includes three processors 12a, 12b, 12c, sharing a common clock 16 via a clock bus 17. Each processor includes an instruction RAM (IRAM) 18a, 18b, 18c, an arithmetic logic unit (ALU) 20a, 200, 20c, and a "sequencer" 22a, 22b, 22c. Each sequencer includes a program counter 24a, 246, 24c and a cause register 26a, 26b, 26c. Each program counter contains an index of the instructions in an associated IRAM and a pointer to the index as the instructions are executed by the processor. The cause registers store current information about interrupts, exceptions, and other processor functions. da60AHIN SE According to one aspect of the invention, a first decoder 28a, 28b, 28c is coupled to each IRAM 18a, 186, 18c, and to each 18 sequencer 22a, 226, 22c, i.e., to each program counter and each cause register. Each first decoder has a three bit output 30a, 20 306, 30c which is available off the chip 10 via three pins (0, 1, 21 2) in real time. ☺ 22 23 24 As mentioned above, the three bit output of each first decoder 28 provides an indication of the processor activity during - 10 - BC_GEN_0000159 1 TRA-040 1 2 3 the last clock cycle. Thus, the decoder 28 is arranged to indicate whether the program counter has moved its pointer to a new instruction. The decoder also decodes the instruction in the IRAM to provide information about the instruction, and decodes the contents of the cause register to provide an indication of an exception encountered during the execution of an instruction. According to a presently preferred embodiment, the first decoder 28 generates a three bit output which is interpreted as shown in Table 1, below. 6 7 8 86220"#Z109060 - 11 - BC_GEN_0000160 1 TRA-040 Output Mnemonic Description 000 NC No Change 001 INC Program Counter Increment 010 JI Program Counter Jump Immediate 011 Program Counter Jump Register 100 ECP Exception Encountered 101 PBT Program Counter Branch Taken 110 RSD Reserved 111 ENH Exception Encountered, No History Buffer Entry Written Table 1 The output 000 indicates that there has been no change in the processor since the last clock cycle; i.e., the processor has not processed a new instruction and the program counter pointer has not changed. The output 001 indicates that the processor has processed the next instruction in the program; i.e., the program 8 counter pointer has incremented to the next instruction in the 9 index. The output 010 indicates that the last instruction 10 processed by the processor was a "hard coded" jump to an 11 instruction; i.e., the instruction in IRAM pointed to by the - 12 - BC_GEN_0000161 1 TRA-040 1 2 3 4 5 6 7 8 program counter includes code indicating that it is a jump instruction to an absolute address in the program. The output 011 indicates that the last instruction processed by the processor was a jump to an instruction based on the contents of a register; i.e., the instruction in IRAM pointed to by the program counter includes code indicating that it is a jump instruction to a location in the program determined by the value of a variable. The output 100 indicates that since the last clock cycle the processor has encountered an interrupt or an exception; i.e., the contents of the cause register contain code which indicates an interrupt or exception. The output 101 indicates that the last instruction processed by the processor was a pc branch taken; i.e., the instruction in IRAM pointed to by the program counter includes code indicating that it is a branch back to another instruction. The output 110 is not presently used, but is reserved for future use. The output 111 indicates that since the last clock cycle the processor has encountered an interrupt or an exception; and that no entry was made in the history buffer 17 The operation of the first decoder 28 and its output is 21 illustrated with reference to a simple code listing which is shown 22 below in Table 2. - 13 - BC_GEN_0000162 1 TRA-040 LINE NUMBER INSTRUCTION Input A B=5 C=2 D=B+C If D=7 then Goto 70 Goto A 10 B=4 Goto 30 End 090611440 hod 90 Table 2 The listing in Table 2 has one "immediate" or "hard coded" jump instruction at line 80 and a conditional branch at line 50. It also has one jump instruction, line 60, based on the contents of a register, i.e. the value of A which is input at line 10. The three bit output of the first decoder during execution of the instructions shown in Table 2 is illustrated in Table 3 below where the values of variables A, B, C, and D are also shown. 8 9 10 - 14 - BC_GEN_0000163 1 TRA-040 Mnemonic Current Next Line Line Three Bit Output INC 001 INC 001 INC 001 INC 001 PBT 101 INC 101 JI 010 INC 001 INC 001 INC 001 16 JR 011 Table 3 When the first instruction (listed in line 10) is executed, the first decoder indicates that a program counter increment (INC) 5 in the execution of the program has occurred and shows an output 6 of "001". As the program progresses from the instruction on line 8 9 10 11 10 through the instruction on line 40, the first decoder continues to indicate that a program counter increment (INC) in the execution of the program has occurred and continues to show an output of "001". When the instruction on line 50 is executed, the first decoder indicates that a program counter branch taken (PBT) - 15 - BC_GEN_0000164 1 TRA-040 has occurred and shows an output of "101". As seen in Tables 2 6 7 8 90 do and 3, the program branches to line 70 because the conditional expression of line 50 is true based on the variable D=7. Upon execution of line 70, the first decoder indicates that a program counter increment (INC) in the execution of the program has occurred and shows an output of "001". When the instruction on line 80 is executed, the first decoder indicates that an immediate jump (JI) has occurred and shows an output of "010". As seen in Tables 2 and 3, the program jumps to line 30. When the instructions on lines 30 and 40 are executed, the first decoder indicates that a program counter increment (INC) in the execution of the program has occurred and shows an output of "001". When line 50 is executed (now for the second time) the first decoder indicates that a program counter increment (INC) in the execution of the program has occurred and shows an output of "001" because the condition (D=7) for the jump in line 50 is no longer valid. Line 60 is now executed and a jump to a location stored in a register occurs. The first decoder therefore indicates a jump to register (JR) by showing an output of "011". 26240Ah 22 23 24 Referring once again to Figure 1, according to another aspect of the invention, each cause register 26a, 26b, 26c is coupled to the data input D of an event history buffer 14 and a second decoder 32a, 32b, 32c is coupled to each cause register and to the - 16 - BC_GEN_0000165 1 - TRA-040 1 2 w N A enable input E of the history buffer 14. The clock 16 provides the common clock signal to the clock input c of the history buffer 14 via the clock bus 17, and a timestamp register 19 is also coupled to the clock bus 17. The contents of the history buffer 14 are made available off chip by three pins for the data, clock, and enable (D, C, E) of the history buffer 14. According to this aspect of the invention, when certain conditions are detected by one of the second decoders 32, the history buffer is enabled via 5 6 7 .8 the appropriate decoder, and information from the cause register, nih 960o the timestamp register, and the program counter is stored in the history buffer. More particularly, the second decoder 32 enables the history buffer whenever the first decoder contains code which indicates that the processor is processing an instruction to jump to a location stored in a register, whenever the first decoder contains code indicating an exception was encountered, and whenever the first decoder contains code indicating a change in state of an interrupt line. According to a presently preferred embodiment, when the 20 history buffer is enabled, it captures forty-four bits of 21 information from the cause register or program counter, and the 22 timestamp register. The forty-four bits of information are 23 preferably organized as illustrated in Table 4 below. - 17 - BC_GEN_0000166 1 TRA-040 | 43 42 41 40 - 18 17 17 16 15 15-0 - Mode Proc Cause/PC HOVRF | TR Time Stamp Table 4 4 5 The first bit, bit location 43, is a mode identifier indicating whether the entry being stored has program counter information or cause register information. A two bit processor identification number is stored in binary form at bit locations 42, 41. This number is used to indicate which processor's information is being stored (in the case of a multiprocessor system). The next twenty-three bits at bit locations 40 through & 15 16 17 18 18 are used to store cause register information or program counter information depending on the mode as explained above. . If program counter information is being stored, the contents of the program counter are stored at bit locations 40 through 18. If cause register information is being stored, bit location 40 is used to indicate whether the exception occurred while the processor was executing an instruction in the branch delay slot. (This applies to pipelined processors such as RISC processors.) Bit locations 39 through 35 are used to store processor related exception conditions. Bit locations 34 through 18 are used to store an indication of all pending interrupts (external, software, co- processor. The HOVRF field at bit location 17 is used to indicate 19 20 21 - 18 - BC_GEN_0000167 1 TRA-040 1 2 3 whether the internal event history buffer has overflowed. The TR bit 16 is used to indicate a timestamp rollover and bits 15 through O are used to store a sixteen bit timestamp. According to the presently preferred embodiment, the forty-four bits captured in the history buffer 14 are serially output on data pin D over forty-four clock cycles (bit serial output). a 6 Nl11 As mentioned above, the event history buffer records information when an event (either an unmasked exception or a PC jump register instruction) has occurred. According to a presently preferred embodiment, this requires an additional mask register per cause register and a free running timestamp counter. The event masks are provided by a JTAG test register load instruction in the static debug interface. When the cause register bits corresponding to an exception are unmasked or a PC jump register instruction is encountered, an entry is made in the history 0 " buffer. ö 0: 0 20 21 PB Those skilled in the art will appreciate that the outputs of the first decoder 28 and the contents of the history buffer 14 provide a relatively complete indication of each processor's execution sequence in real time, particularly when viewed in light of the actual program code which is being executed. Therefore, 23 - 19 - BC_GEN_0000168 1 TRA-040 1 2 according to the invention, a debugging system may be coupled to the first decoders and history buffer as illustrated in Figure 2. 5 6 7 8 Turning now to Figure 2, the outputs 30a, 30b, 300 of the first decoders and the D, C, E terminals of the history buffer are coupled to a debugging computer 44 which preferably has a copy of the program code stored therein. The three-bit outputs 30a, 30b, 30c of the first decoders and the D, C, E terminals of the history buffer are preferably coupled to an interface buffer 40 which is coupled by a serial, parallel, or network connection 42 to the debugging computer 44. The interface buffer 40 is a rate decoupling buffer. In a present embodiment of the invention, the debugger interface is provided on a 100 MHz three processor system. In that system, the data rate for reading the event history buffer is approximately 1 gigabit/sec. Current PCs cannot keep up with that data rate. Therefore, the buffer 40 is provided to prevent the loss of event history data. 20 As the program is running on the ASIC 10, the debugging computer 44 collects information from the first decoders and the history buffer. The information collected by the computer 44 is associated with each line of code being executed by the ASIC by stepping through the copy of the code which is stored in the computer 44. When a bug is encountered, the complete history of 22 23 24 - 20 - BC_GEN_0000169 1 TRA-040 instruction execution leading up to the failure can be reviewed 2 with the computer 44. The debugging system is non-invasive and permits debugging of programs operating in real time. Ovo u A w N + There have been described and illustrated herein embodiments 6 of a real time debugger interface for embedded systems. While 7 particular embodiments of the invention have been described, it is 8 not intended that the invention be limited thereto, as it is intended that the invention be as broad in scope as the art will allow and that the specification be read likewise. Thus, while particular encoding schemes have been disclosed with reference to the first decoder output and the history buffer contents, it will be appreciated that other encoding schemes could be utilized provided that they achieve substantially the same results as described herein. Also, while the invention has been illustrated with reference to a three-processor ASIC chip, it will be recognized that the invention may be applied in other types of chips having greater or fewer processors. Moreover, while 19 particular configurations have been disclosed in reference to the 20 indications provided by the first decoders, it will be appreciated 21 that other configurations could be used as well, provided that they achieve substantially the same results as described herein. 23 It will therefore be appreciated by those skilled in the art that ... 22 - 21 - BC_GEN_0000170 1 TRA-040 1 2 yet other modifications could be made to the provided invention without deviating from its spirit and scope as so claimed. 09064/,042898 - 22 - BC_GEN_0000171 1 TRA-040 claims: 1. A processor having a real time debugging interface, said processor comprising: a) instruction memory means for storing instructions to be executed by said processor; b) program counter means coupled to said instruction memory means for indexing said instructions; c) cause register means for indicating information regarding interrupts and exceptions; and d) first decoder means for indicating information about an instruction executed by said processor during a clock cycle, said first decoder means being coupled to said instruction memory 860240"447449060 means, said program counter means, and said cause register means, said first decoder means having a first output, wherein said first output provides information regarding activity of said processor in real time. 2. A processor according to claim 1, said information regarding processor activity includes information as to at least one of a jump instruction has been executed, a jump instruction based on the contents of a register has been executed, a branch has been taken, and an exception has been encountered. - 23 - BC_GEN_0000172 1 TRA-040 3. A processor according to claim 1, wherein: said clock cycle is a processor clock cycle, and said first decoder means updates said information about each instruction executed by said processor for each said processor clock cycle. 4. A processor according to claim 3, wherein: said information about each instruction executed by said processor includes an indication whether or not an instruction has been executed since a previous processor cycle. 5. A processor according to claim 1, wherein: said first output is a three bit parallel output. 09064.71042298 - 24 - BC_GEN_0000173 1 TRA-040 6. A processor according to claim 1, further comprising: e) second decoder means coupled to said cause register means for indicating information about contents of said cause register means, said second decoder means having a second output; and f) event history buffer means for storing information regarding processor events, said event history buffer means having a data input, a data output, and an enable input, said data input being coupled to said cause register means and said enable input being coupled to said second output, wherein said second decoder means decodes contents of said cause register means and enables said event history buffer means to capture contents of said cause register means when contents of said cause register means indicate a particular event. 09064_7102298 7. A processor according to claim 6, wherein: said second decoder means enables said event history buffer means when contents of said cause register means indicate an event including at least one of a change in status of an interrupt line, an internal processor exception, and a jump instruction based on the contents of a register. 8. A processor according to claim 6, wherein: said data output of said event history buffer means is a bit serial output. - 25 - BC_GEN_0000174 1 TRA-040 9. A processor according to claim 6, wherein: said processor is embodied on a chip having a plurality of pins, said first output and said data output are provided via some of said plurality of pins. 10. A processor according to claim 9, wherein: said first output is an n-bit parallel output, and said data output is a serial output. 0622-0"+Z1906D - 26 - BC_GEN_0000175 1 TRA-040 VERIFIED STATEMENT CLAIMING SMALL ENTITY STATUS (37 CFR 1.9(f) and 1.27(b)) - INDEPENDENT INVENTOR As a below named inventor, I hereby declare that I am an independent inventor as defined in 37 CFR 1.9(c) for purposes of paying reduced fces under section 41 (a) and (b) of Title 35, United States Code, to the Patent and Trademark Office with regard to the invention entitled: REAL TIME DEBUGGER INTERFACE FOR EMBEDDED SYSTEMS described in ecification filed herewith [ ] application serial No. [] patent No., filed, issued I have not assigned, granted, conveyed or licensed and am under no obligation under contract or law to assign, grant, convey or license any rights in the invention to any person who could not be classified as an independent inventor under 37 CFR 1.9(c) if that person had made the invention, or to any concern which would not qualify as a small business concern under 37 CFR 1.9(d) or a nonprofit organization under 37 CFR 1.9(e). Each person, concern or organization to which I have assigned, granted, conveyed, or licensed or am under an obligation under contract or law to assign, grant, convey or license any rights in the invention is listed below: () no such person, concern, or organization [X] persons, concerns or organizations listed below* *Note: Separate verified statements are required from each named person, concern or organization having rights to the invention averring to their status as small entities. (37 CFR 1.27) NAME: TranSwitch Corporation ADDRESS: 2 Enterprise Drive, Shelton, CT 06484 [ ]Individual [X]Small Business Concern (]Nonprofit Organization kacknowledge the duty to file, in this application or patent, notification of any change in status resulting in loss of entitlement to small entity status prior to paying, or at the time of paying, the earliest of the issue fee or any maintenance fee due after the date on which status as a small entity is no longer appropriate. (37 CFR 1.28(b)) hereby declare that all statements made herein of my own knowledge are true and that all statements made on information and belief are elieved to be true; and further that these statements were made with the knowledge that willful false statements and the like so made are Punishable by fine or imprisonment, or both, under section 1001 of Title 18 of the United States Code, and that such willful false statements may jeopardize the validity of the application, any patent issuing thereon, or any patent to which this verified statement is directed. SIGNATURE DATE NAME OF INVENTOR, Subhash C. Roy SIGNATURE Sthe NAME OF INVENTOR; Paul Hembrook SIGNATUR Vaul W. Member NAME OF INVENFOR: Eugene L. Parrella SIGNATURE Lugne e path NAME OF INVENTOR: Richard Mariano SIGNATURE Buchand & Mauand Date 4/11/99 DATE_4/12/98 Date 4/7/98 DATE SIGNATURE DATE Date_4/17/90 BC_GEN_0000148 1 TRA-040 VERIFIED STATEMENT CLAMING SMALL ENTITY STATUS (37 CFR 1.9(f) and 1.27(c) - SMALL BUSINESS CONCERN I hereby declare that I am [ ] the owner of the small business concern identified below [X] an official of the small business concern empowered to act on behalf of the concern identified below: NAME OF CONCERN: TranSwitch Corporation ADDRESS OF CONCERN: 8 Progress Drive Shelton, CT 06484 I hereby declare that the above identified small business concern qualifies as a small business concern as defined in 13 CFR 121.3-18, and reproduced in 37 CFR 1.9 (d), for purposes of paying reduced fees under section 41(a) and (b) of Title 35, United States Code, in that the number of employees of the concern, including those of its affiliates, does not exceed 500 persons. For purposes of this statement, (1) the number of employees of the business concern is the average over the previous fiscal year of the concern of the persons employed on a full-time, part-time or temporary basis during each of the pay periods of the fiscal year, and (2) concerns are affiliates of each other when either, directly or indirectly, one concern controls or has the power to control the other, or a third party or parties controls or has the power to control both. I hereby declare that rights under contract or law have been conveyed to and remain with the small business concern identified above with regard to the invention, entitled: REAL TIME DEBUGGER INTERFACE FOR EMBEDDED SYSTEMS by inventor(s): Subhash C. Roy, Paul Hembrook, Eugene L. Parrella and Richard Mariano described in [X] the specification filed herewith [] application serial No., filed () patent No., issued lfthe rights held by the above identified small business concern are not exclusive, each individual, concern or organization having rights to the invention is listed below* and no rights to the invention are held by any person, other than the inventor, who could not qualify as a small business concern under 37 CFR 1.9(d) or by any concern which would not qualify as a small business concern under 37 CFR 1.9(d) or a nonprofit organization under 37 CFR 1.9(e). *Note: Separate verified statements are required from each named person, concern or organization having rights to the invention averring to their status as small entities. (37 CFR 1.27) NAME: ADDRESS: [ ]Individual [ ]Small Business Concern (Nonprofit Organization Hacknowledge the duty to file, in this application or patent, notification of any change in status resulting in loss of entitlement to small dality status prior to paying, or at the time of paying, the earliest of the issue fee or any maintenance fee due after the date on which status as a small entity is no longer appropriate. (37 CFR 1.28(b)) I hereby declare that all statements made herein of my own knowledge are true and that all statements made on information and belief are believed to be true; and further that these statements were made with the knowledge that willful false statements and the like so made are punishable by fine or imprisonment, or both, under section 1001 of Title 18 of the United States Code, and that such willful false statements may jeopardize the validity of the application, any patent issuing thereon, or any patent to which this verified statement is directed. NAME OF PERSON SIGNING: Santanu Das TITLE IN ORGANIZATION: President ADDRESS OF PERSON SIGNING: 14 Hunter Ridge Road Monroe, CT 06468 SIGNATURE: Santana dai 4,17.981 DATE: BC_GEN_0000149 1 TRA-040 11. An embedded system having a plurality of processors and a real time debugging interface, said system comprising: a) a plurality of instruction memory means for storing instructions to be executed by a respective one of said plurality of processors; b) a plurality of program counter means, each coupled to a respective one of said plurality of instruction memory means for indexing contents of said instruction memory means; c) a plurality of cause register means for indicating information regarding interrupts and exceptions for a corresponding one of said plurality of processors, each of said cause register means being coupled to a respective one of said processors; and 0906 14.671, 0412298 d) a plurality of first decoder means, each said first decoder means coupled to a respective one of said instruction memory means, to a respective one of said program counter means, and a respective one of said cause register means, each said first decoder means for indicating information about an instruction executed during a clock cycle by a respective one of said processors, each said first decoder means having a first output, wherein each said first output provides information regarding activity of said processor in real time. - 27 - BC_GEN_0000176 1 TRA-040 12. An embedded system according to claim 11, wherein: said information regarding processor activity includes information as to at least one of a jump instruction has been executed, a jump instruction based on the contents of a register has been executed, a branch has been taken, and an exception has been encountered. 13. An embedded system according to claim 11, wherein: said clock cycle is a processor clock cycle, and each said first decoder means updates said information about each instruction executed by a respective processor for each said processor clock cycle of said respective processor. 09064702898 14. An embedded system according to claim 13, wherein: each said information about each instruction executed by a respective processor includes an indication whether or not an instruction has been executed since a previous processor cycle of said respective processor. 15. An embedded system according to claim 11, wherein: each of said first outputs is a three bit parallel output. - 28 - BC_GEN_0000177 1 TRA-040 16. An embedded system according to claim 11, further comprising: e) a plurality of second decoder means, each coupled to a respective one of said plurality of cause register means, each said second decoder means for indicating information about contents of a respective cause register means; and f) an event history buffer means for storing information regarding processor events, said history buffer means having a data input, a data output, and an enable input, said data input being coupled to each of said plurality of cause register means and said enable input being coupled to each of said second outputs, wherein each of said second decoder means decodes contents of a respective cause register means and enables said event history 09064487141042298 buffer to capture contents of said respective cause register means when contents of said respective cause register means indicate a particular event. 17. An embedded system according to claim 16, wherein: each said second decoder means enables said event history buffer means when contents of a respective cause register means indicate an event including at least one of a change in status of an interrupt line, an internal processor exception, and a jump instruction based on the contents of a register. - 29 - BC_GEN_0000178 1 TRA-040 18. An embedded system according to claim 16, wherein: said data output of said event history buffer means is a bit serial output. 19. An embedded system according to claim 11, wherein: said system is embodied on a chip having a plurality of pins, said first and second outputs are provided via some of said plurality of pins. 20. An embedded system according to claim 19, wherein: each of said first outputs is an n-bit parallel output, and said second output is a serial output.. 0906475.0442298 21. A method of debugging a processor, said method comprising: a) providing information about processor activity in real time; and b) associating the instructions executed by the processor with the information about processor activity. - 30 - BC_GEN_0000179 1 TRA-040 22. A method according to claim 21, wherein: said step of providing information about processor activity includes providing information about every instruction executed by the processor. 23. A method according to claim 22, wherein: said step of providing information about processor activity includes providing information that the processor has not executed an instruction during the last processor cycle. 24. A method according to claim 21, wherein: the information about processor activity includes an indication of at least one of whether the last instruction 0906417" 14. 042298 executed was a jump, a jump based on the contents of a register, a branch taken, or an instruction which encountered an exception. 25. A method according to claim 21, further comprising: c) providing information regarding the status of the processor when certain processor events occur, said certain processor events including at least one of a change in status of an interrupt line, an internal processor exception, and the execution of a jump instruction based on the contents of a register. - 31 - BC_GEN_0000180 1 TRA-040 ABSTRACT OF THE DISCLOSURE oot AW N = A debugging interface includes a pair of decoders and an event history buffer coupled to the sequencer of a processor. The first decoder is coupled to the program counter of the sequencer 6 and the Instruction RAM of the processor. The second decoder is 7 coupled to the cause register of the sequencer and the event 8 history buffer is also coupled to the cause register. The first 9 decoder provides a three bit real time output which is indicative 10 of the processor activity on a cycle by cycle basis. The three 10 bit output indicates seven different conditions: whether the last instruction executed by the processor was an inc, an exception, an exception with no event history buffer entry, or a branch taken, whether there has been no instruction executed since the last clock cycle, and whether a jump was an immediate jump or a jump to a register. The event history buffer is loaded with more detailed information about the instruction last executed when the first 18 decoder indicates that the last instruction was an exception or a 19 jump to a register, and when there is a change in state of an 20 interrupt line or an internal processor exception. An exemplary implementation of the debugging interface is embodied on an ASIC chip having three processors. Each processor is provided with a first and second decoders and a single event history buffer for 24 all processors is provided on the chip. @ 3099 - 32 - BC_GEN_0000181 1 2l8a ALU IRAM Clock bloce Decoder Cause Reg. Timestamp Register 280 Program Counter 22a Decoder 270. [24a 12a 7200 22186 ALU IRAM Decoder 306 Cause Reg. Program Counter 28b Decoder ALU IRAM -260 Decoder вас 280 Cause Reg. Program Counter Decoder 320 42 DICE History Buffer 10 olole Figure 1 BC_GEN_0000182 09064671.. 2442298 ASIC 30b - 30a Figure 2 s A 6 Avans LWS >> > .n *Wro W Y >>>AVEVA w 2) A8YU > Us 03 $ 40 > VN Me Son o f 3.2 bigA AVIS S W Alyas Wox ing ... INAS www > WAS VREA Sonnenweg Avucun ... wyron M austions un solo es S pa >> Author >>> < << Majo n a BUFFER 1 viny S >> Swag Re Ovognew wio. . SUNS WAX A ty **** O utdin Wa y Womaso SEX, Poenarugo > xoxx ANO YU musu xe sus casas en voisid own w ho M AY >>> WM Men selles & >wfox Xo anis Ky www .AYRAMO Morynecon WAS A wWw w 36 > wr whorfo r yomoyon vette 2 & la NO ng QUE S >> Po ko house ? 59 $4,34 142 AVAR Art .us S hh BC_GEN_0000183 1 Docket No.TRA-040 DECLARATION FOR PATENT APPLICATION AND POWER OF ATTORNEY As below named inventor, I hereby declare that: My residence, post office address and citizenship are as stated below next to my name, and I believe I am the original, first and sole inventor (if only one name is listed below) or an original, first and joint inventor (if plural names are listed below) of the subject matter which is claimed for and for which a patent is sought on the invention entitled REAL TIME DEBUGGER INTERFACE FOR EMBEDDED SYSTEMS, the specification of which [X] is attached hereto. [ ] was filed on as application Serial Number and was amended on (if applicable) I hereby state that I have reviewed and understand the contents of the above identified specification, including the claims, as amended by an amendment referred to above. I acknowledge the duty to disclose information which is material to the examination of this application in accordance with Title 37, Code of Federal Regulations, Section 1.56(a). I verify that I am qualified as an independent inventor under Title 37, Code of Federal Regulations, Section 1.9(c), and my obligation to assign rights to this invention, if any, is to a qualified small business concern under Title 37, Code of Federal Regulations, Section 1.9(d). I hereby claim foreign priority benefits under Title 35, United States Code, Section 119 of any foreign application(s) for patent or inventor's certificate listed below and have also identified below any foreign application for patent or inventor's certificate having a filing date before that of the application on which priority is claimed: Prior Foreign Application(s) Priority claimed [ ] NO (Number) - [ ] YES D/M/YR FILED (Country) ___ [ ] YES [ ] NO (Number) (Country) D/M/YR FILED I hereby claim the benefit under Title 35, United States Code, Section 120 of any United States application(s) listed below and, insofar as the subject matter of each of the claims of this application is not disclosed in the prior United States application in the manner provided by the first paragraph of Title 35, United States Code, Section 112, I BC_GEN_0000184 1 acknowledge the duty to disclose material information as defined in Title 37, Code of Federal Regulations, Section 1.56(a) which occurred between the filing date of the prior application and the national or PCT international filing date of this application: (Application Ser. No) (Filing Date) (Status-Patented, pending, abandoned) (Application Ser. No) (Filing Date) (Status-Patented, pending, abandoned) As a named inventor, I hereby appoint the following attorney(s) and/or agent (s) to prosecute this application and transact all business in the Patent and Trademark Office connected therewith: David P. Gordon (29,996), David S. Jacobson (39,235), Thomas A. Gallagher (31,358) Address all telephone calls to David P. Gordon at (203) 329-1160 Address all correspondence to David P. Gordon, Esg. 65 Woods End Road Stamford, Connecticut 06905 U.S.A 090641 I hereby declare that all statements made herein of my own knowledge are true and that all statements made on information and belief are believed to be true; and further that these statements were made with the knowledge that willful false statements and the like so made are punishable by fine or imprisonment, or both, under Section 1001 of Title 18 of the United States Code and that such willful false statements may jeopardize the validity of the application or any patent issued thereon. SOLE OR FIRST INVENTOR Signature Date 042298 Date_4/17/99 Full Name "Subhash C. Roy Residence_168 Belltown Road #23, Stamford, CT 06905 Citizenship US P.O. Address same as residence SECOND JOINT INVENTOR Signature Haul W.41 entrar Full Name_Paul Hembrook Date 4/17/98 Residence_3 Summit Street, New Milford, CT 06776 Citizenship_US P.O. Address same as residence BC_GEN_0000185 1 a Date Date 4/17/98 THIRD JOINT INVENTOR Signature lugen a f Full Name_Eugene L. Parrella Residence_48 Settlers Farm Road, Monroe, CT 06468 Citizenship_US P.O. Address same as residence FOURTH JOINT INVENTOR Signature Bichard & Maund Date_4/17/38 Full Name_Richard Mariano Residence_140 Codfish Hill Road, Bethel, CT 06801 Citizenship US P.O. Address same as residence 8622:4047*29060 BC_GEN_0000186 1 TRA-040 REAL TIME DEBUGGER INTERFACE FOR EMBEDDED SYSTEMS BACKGROUND OF THE INVENTION 5 7 8 1. Field of the Invention The invention relates to systems and methods for debugging software in real time. More particularly, the invention relates to systems and methods for the real time debugging of firmware in embedded systems, e.g. ASIC chips having one or more processors on a single chip. to 2 2. State of the Art Software debugging may be accomplished in a number of ways, 14 some of which are not performed in real time. A traditional 5 debugging technique is to step through program instructions at a rate much slower than the rate at which the program is designed to run in real time. By stepping through the program instructions one-by-one, errors can be observed as they happen and the program 19 code lines executed immediately prior to the error can be analyzed 20 to find the cause of the error. This technique is not helpful, 21 however, if the error in program execution is the result of timing 22 errors or other types of errors which only occur when the program 23 is running at real time speed. As used herein, the term "real 18 - 1 - BC_GEN_0000150 1 TRA-040 1 time" means the rate at which a program must execute in order to process the incoming data rate which may be quite high. A widely used technique for debugging a program which is running in real time is called "tracing". Tracing involves 6 recording the transactions performed by the computer as it 7 8 9 executes the program code. The trace of activities performed by the computer during the time of a failure can be a useful guide in isolating possible causes of the failure. Homu ih po 960o Another useful debugging tool is to set breakpoints at selected places in the program. The breakpoints trap the flow of the software and provide insight into whether, when, and how certain portions of the software are entered and exited. An analysis of the flow of the software can provide information which is useful in isolating bugs. 18 Many state-of-the-art tracing and trapping methods are accomplished by a debug support circuit which is connected to the 20 system bus, i.e. the bus which couples the CPU to memory. See, for example, U.S. Patent Number 5,491,793 to Somasundaram et al. entitled "Debug Support in a Processor Chip." Connecting a debug 23 circuit to the system bus is convenient because addresses, 24 instructions, and data can be accessed via the system bus. 22 - 2 - BC_GEN_0000151 1 TRA-040 1 2 However, coupling the debug support circuit to the system bus increases the electrical load on the bus and interferes with the operation of the bus. Moreover, operation of the system bus may interfere with operation of the debug support circuit. In addition, the system bus may not provide all the information necessary for debugging a program running on a CPU which uses internal cache. These CPUs will not access the system bus if the information they need is available in cache. If an error occurs while the CPU is accessing internal cache, the debug support circuit will not be able to access the information it needs. 6 8 - - - - Another tracing and trapping method is disclosed in U.S. Patent Number 5,833,310 to Whistel et al. entitled "On-Chip In- Circuit-Emulator Memory Mapping and Breakpoint Register Modules." According to this method, an internal bus controller is coupled to - - 16 the memory address bus and a match register. When a memory de address written to the address bus matches an address in the match 20 register, a memory mapping module maps a memory cycle to an 19 external debug memory. The user can set specific bus event conditions for which memory is mapped by writing to a set of 21 breakpoint registers. A disadvantage of this method is that it 22 requires an additional set of I/O pins for the chip so that the 23 external debug memory can be coupled to the chip. This may - 3 - BC_GEN_0000152 1 TRA-040 1 require a significant number of pins since the addresses to be mapped may be 32 or 64 bits wide. 4 5 6 7 Still another tracing and trapping method is disclosed in U.S. Patent Number 5,513,346 to Satagopan et al. entitled "Error Condition Detector for Handling Interrupt in Integrated Circuits Having Multiple Processors." According to this method, an interrupt processor controller intercepts all interrupts and routes them to the appropriate processor in a multiprocessor chip. The interrupt processor controller includes logic which determines when an interrupt will cause an error because a previously instigated interrupt has not been cleared. When such an error is detected, a bit is set in an error detect register, the bit corresponding to an interprocessor interrupt channel. The bits in the register are Red and a single bit output indicates the occurrence of an error. The register may then be examined to determine the location of the interrupt error in the executing code. This method does not interfere with the system bus and does not require very many additional pins on the chip. However, the debugging information that it provides is limited. 19 20 21 23 deve The Motorola MPC-860 PowerQuiccmM includes a program development system interface port which provides a three bit 24 output indicative of the state of the program execution as the - 4 - BC_GEN_0000153 1 TRA-040 1 4 5 6 7 program is being executed. The MPC-860 is a 40 mHz communications controller but the development system interface port is only operable at a rate of 4 mHz. Thus, the port can not be used for real time debugging. The specifications for the MPC-860 are found in the "MPC-860 POWERQUICC USER'S MANUAL", Copyright 1996 Motorola, Inc., Schaumberg, IL, the complete disclosure of which is incorporated herein by reference. ASIC design using one or more embedded processors poses additional debugging challenges. The prior art methods of trapping instructions at a given point in time implies that the system must be stopped to allow debugging of firmware. Once the system is stopped, however, real time events and their timing relationships are lost. If there is a firmware bug which is only identifiable in the presence of live traffic (during real time operations) it is necessary to obtain contextual information about the error before the firmware is changed. 16 17 SUMMARY OF THE INVENTION 22 23 It is therefore an object of the invention to provide a debugging interface for tracing instructions without loss of real time context and event interaction. 24 - 5 - BC_GEN_0000154 1 TRA-040 2 It is also an object of the invention to provide a debugging interface which does not interfere with the operation of a processor or system bus. 6 7 It is another object of the invention to provide a debugging interface which does not require many additional pins on a processor chip. ^ o 6986640 It is a further object of the invention to provide a debugging interface which provides access to a substantial amount of information about the executed instructions. In accord with these objects which will be discussed in detail below, the debugging interface of the present invention includes a first decoder coupled to the sequencer of a processor and to the Instruction RAM (IRAM) of the processor. The first 17 decoder, according to the invention, provides a real time three 18 bit output on a cycle by cycle basis which is indicative of the 19 processor activity during the last clock cycle. According to a presently preferred embodiment, the three bit output indicates seven different conditions regarding processor activity. In 22 particular, the three bit output indicates whether or not a new 23 instruction has been executed since the last clock cycle, and if a 24 new instruction has been executed, whether the last instruction - 6 - BC_GEN_0000155